Assignment A1-001-A-GIT0723

Muhammad Shafiq B. Ibrahim

A1-001-A: Semiconductor Fabrication Process & Device Characterization for CMOS Technology
PART 1: MOSFET Device Structure
1.What are the advantages of CMOS over its Bipolar counterpart? Advantages of CMOS Lower power dissipation CMOS devices are voltage driven and use less power Bread broading experimental circuitary is easier with CMOS Draws little power at low frequency Can make analogue mixed signal on the same chip Have two degrees of freedom during design Can integrate more transistor or functions on the same chip Easy and cheap to fabricate Operates at faster speed

2.Draw the cross section structure of the NMOS & PMOS transistors. State clearly the Source (S), Gate (G) and the Drain (D)? NMOS Cross Section

PMOS Cross Section

3.What is body effect? Body effect refers to the change in the transistor threshold voltage (Vt) resulting from a voltage difference between the transistor source and body. Because the voltage difference between the source and body affects the Vt, the body can be thought of as a second gate that helps determine how the transistor turns on and off. The strength of the body effect is usually quantified by the body coefficient gamma.

The equation above explain the body effect where VTB is the threshold voltage with substrate bias present, and is the body effect parameter. Where VT0 is the zero value of VSB of threshold voltage and 2B is the approximate potential drop between surface and bulk across the depletion layer when VSB = 0 and gate bias is sufficient to insure that a channel is present.

PART 2: MOSFET Operation

1.Using the NMOS structure above, explain the operation of the transistor for the following situations: a. No gate voltage. b. Positive voltage applied at the gate. c. Small Drain to Source voltage, VDS applied. d. VDS is increased.

a. No gate voltage -Vgs = 0 - Ids = 0

-No channel exist.

b. Positive voltage applied at the gate. -channel formed -Ids is linear with Vds

c. Small Drain to Source voltage, VDS applied.

d. VDS is increased.

PART 3: MOSFET Characteristic

1.Draw the IDS VDS characteristic and explain the three main MOS operating regions.

There are three main operating region for MOS that are the cut off region, linear region and saturation region. The cut-off region shows an N-channel MOSFET with the source and drain connected to power and ground; the substrate, or body of the device, is also connected to ground. In particular, there will be no current flow in the channel region under the gate of the transistor, and therefore no current will flow between the source and drain of the device. Under these conditions, the MOSFET is turned off. For the linear regions it shows the same N-channel MOSFET with a positive charge applied to the gate of the device. Under these circumstances, if the gate is given a sufficiently large charge, negative charge carriers (electrons) will be attracted from the bulk of the substrate material into the channel region immediately below the oxide under the gate. When more electrons are attracted into this region than there are positive charge carriers (holes) in the channel, then the channel effectively behaves as an N type region, and current can flow between the source and the drain. When this happens, the MOSFET is turned on. Saturation region is due to the pinched off of the channel. This pinched off happen when the Vds supply is too large. When the channel in in the saturation mode the Vgs is greater than Vgd. The current flow cause the electron to move from drain to electron. When the electron is stacking on the source side too much, it cannot accept anymore and causing it to be pinched off.

2.State the IDS equation for all the regions

PART 4: Fabrication Process Step

1.Explain the following terms: a. Oxidation Oxidation is a process which converts silicon on the wafer into silicon dioxide. The chemical reaction of silicon and oxygen already starts at room temperature but stops after a very thin native oxide film. For an effective oxidation rate the wafer must be settled to a furnace with oxygen or water vapor at elevated temperatures. Silicon dioxide layers are used as high-quality insulators or masks for ion implantation. The ability of silicon to form high quality silicon dioxide is an important reason, why silicon is still the dominating material in IC fabrication. b. Threshold voltage implant Once the MOSFET is fabricated and if the threshold voltage has to be adjusted (increase or decrease) the only solution is to implant the dopants near the surface. This is known as threshold voltages adjustment implant and is given by VH= qD/Cox. qD is the charge implanted in the channel per unit area. c. Deposition A multitude of layers of different materials have to be deposited during the IC fabrication process. The two most important deposition methods are the physical vapor deposition (PVD) and the chemical vapor deposition (CVD). During PVD accelerated gas ions sputter particles from a sputter target in a low pressure plasma chamber. The principle of CVD is a chemical reaction of a gas mixture on the substrate surface at high temperatures. The need of high temperatures is the most restricting factor for applying CVD. This problem can be avoided with plasma enhanced chemical vapor deposition (PECVD), where the chemical reaction is enhanced with radio frequencies instead of high temperatures. An important aspect for this technique is the uniformity of the deposited material, especially the layer thickness. CVD has a better uniformity than PVD. d. Etching Etching is used to remove material selectively in order to create patterns. The pattern is defined by the etching mask, because the parts of the material, which should remain, are protected by the mask. The unmasked material can be removed either by wet (chemical) or dry (physical) etching. Wet etching is strongly isotropic which limits its application and the etching time can be controlled difficultly. Because of the so-called under-etch effect, wet etching is not suited to transfer patterns with submicron feature size. However, wet etching has a high selectivity (the etch rate strongly depends on the material) and it does not damage the material. On the other side dry etching is highly anisotropic but less selective. But it is more capable for transfering small structures.

e. Doping In production semiconductor, doping intentionally introduces impurities into an extremely pure (also referred to as intrinsic) semiconductor for the purpose of modulating its electrical properties. The impurities are dependent upon the type of semiconductor. Lightly and moderately doped semiconductors are referred to as extrinsic. f. Spacer oxide A conformal layer of dielectric silicon dioxide is deposited over the entire wafer. g. Ion implantation Ion implantation is the dominant technique to introduce dopant impurities into crystalline silicon. This is performed with an electric field which accelerates the ionized atoms or molecules so that these particles penetrate into the target material until they come to rest because of interactions with the silicon atoms. Ion implantation is able to control exactly the distribution and dose of the dopants in silicon, because the penetration depth depends on the kinetic energy of the ions which is proportional to the electric field. The dopant dose can be controlled by varying the ion source. Unfortunately, after ion implantation the crystal structure is damaged which implies worse electrical properties. Another problem is that the implanted dopants are electrically inactive, because they are situated on interstitial sites. Therefore after ion implantation a thermal process step is necessary which repairs the crystal damage and activates the dopants. h. Annealing Annealing is a high temperature process which allows doping impurities to diffuse further into the bulk and repairs lattice damage caused by the collisions with doping ions. In the semiconductor industry, silicon wafers are annealed, so that dopant atoms, usually boron, phosphorus or arsenic, can diffuse into substitutional positions in the crystal lattice, resulting in drastic changes in the electrical properties of the semiconducting material.

2.What is the majority carrier in the following materials? Majority carrer is the entity responsible for carrying the greater part of the current in a semiconductor. In n-type semiconductors the majority carriers are electrons; in p-type semiconductors they are positively charged holes Compare minority carrier. a. Phosphorus -Electron( n-type) b. Arsenic -Electron( n-type) c. Antimony -Electron( n-type) d. Boron -Hole( p-type) e. Gallium -Hole( p-type)

PART 5: CMOS Circuit Design and Technology Scaling

1.The ideal scaling theory follows three rules: a. Reduce all lateral and vertical dimensions by a. b. Reduce the threshold voltage and the supply voltage by a. c. Increases all the doping levels by a. How does the scaling affect the performance of the transistors? (Speed, leakage current, power consumptions, etc) Transistor scaling is the primary factor driving speed performance, scaling also, reduced gate delay by 30% allowing an increase in operating frequency of about 43%. reduced energy per transition by about 65% while saving 50% of power. doubled transistor density. To achieve this, transistor width, length, and oxide dimensions were scaled by 30%. As a result, the chip area decreased by 50% for the same number of transistors, and total parasitic capacitance decreased by 30%.

2.What is short channel effect? A short-channel effect is an effect whereby a MOSFET in which the channel length is the same order of magnitude as the depletion-layer widths (xdD, xdS) of the source and drain junction, behaves differently from other MOSFETs. As the channel length L is reduced to increase both the operation speed and the number of components per chip, the so-called short-channel effects arise.

PART 6: Using CMOS for Digital IC Design

1.Why is CMOS technology a preferred technology for digital IC? CMOS gates are very simple. The basic gate is a inverter, which is consist of only two transistors. This together with the low power consumption means it lends itself well to dense integration. CMOS logic takes very little power when held in a fixed state. The current consumption comes from switching as those capacitors are charged and discharged. It has good speed to power ratio compared to other logic types. Besides, the outputs actively drive both ways. They also have high input impedance. The input signal is driving electrodes with a layer of insulation (the metal oxide) between them and what they are controlling. 2.Draw and explain the operation of an inverter using the following technology a. Transistor Transistor Logic (TTL)

TTL Inverter For input low, current iR flows out the input (E of Q1) into the output of the inverter driving input. Q2 is in cutoff since it gets no base current from Q1. Q3 is in cutoff since it gets no base current from Q2. Output is high since iC3 0. for input high, current iR flows out C of Q1 into base of Q2. Q2 comes on in active mode and then moves into saturation. Q2's emitter current provides base current for Q3. Q3 comes on in active and then moves into saturation mode so output goes low, I.e vo VCE,SAT = 0.2V

b. CMOS

CMOS Inverter When the input is low at VIN, the resistance is high at NMOS, so it will limit the current that can flow from VOUT to the ground. PMOS is at low resistance when VIN is low, thus much current can flow from the supply to the ground. The resistance between the supply and VOUT is low so the voltage drop is small, hence the output is at high voltage. On the other hand, when the voltage of input VIN is high, the PMOS transistor is in a high resistance (OFF state) so it would limit the current flowing from the positive supply to the output, while the NMOS transistor is in a low resistance (ON state), allowing the output to drain to ground. Because the resistance between VOUT and ground is low, the voltage drop due to a current drawn into VOUT placing VOUT above ground is small. This will results in the output registering a low voltage. In conclusion, when the input is high for CMOS, the output is low and vice versa. Thus, it is called CMOS inverter.