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DDR333 COMPATIBILITY
DDR333 meets or surpasses all DDR266 timing requirements thus assuring full backwards compatibility with current DDR designs. In addition, these devices support concurrent auto-precharge and tRAS lockout for improved timing performance. The 256Mb, DDR333 device will support an (tREFI) average periodic refresh interval of 7.8us. The standard 66-pin TSOP package is offered for point-to-point applications where the FBGA package is intended for the multi-drop systems. The Micron 256Mb data sheet provides full specifications and functionality unless specified herein.
CONFIGURATION
Architecture Configuration Refresh Count Row Addressing Bank Addressing Column Addressing 64 Meg x 4 32 Meg x 8 16 Meg x 16 16 Meg x 4 x 4 banks 8 Meg x 8 x 4 banks 4 Meg x 16 x 4 banks 8K 8K (A0A12) 4 (BA0, BA1) 2K (A0A9, A11) 8K 8K (A0A12) 4 (BA0, BA1) 1K (A0A9) 8K 8K (A0A12) 4 (BA0, BA1) 512 (A0 A8)
OPTIONS
PART NUMBER
64M4 32M8 16M16 TG FJ -6 -6T -75Z none
Configuration 64 Meg x 4 (16 Meg x 4 x 4 banks) 32 Meg x 8 (8 Meg x 8 x 4 banks) 16 Meg x 16 (4 Meg x 16 x 4 banks) Plastic Package 66-Pin TSOP (OCPL) 60-Ball FBGA (16x9mm) Timing - Cycle Time 6ns @ CL = 2.5 (DDR333BFBGA)1 6ns @ CL = 2.5 (DDR333BTSOP)1 7.5ns @ CL = 2 (DDR266A)2 Self Refresh Standard
1. CL = CAS (Read) Latency 2. With a 50/50 clock duty cycle and a minimum clock rate @ CL = 2 ( -75Z) and CL = 2.5 (-6, -6T). 3. -75, -8 are also available; see base data sheet.
NOTE: 1. Supports PC2700 modules with 2.5-3-3 timing 2. Supports PC2100 modules with 2-3-3 timing
256Mb: x4, x8, x16 DDR333 SDRAM 256Mx4x8x16DDR333_B.p65 Rev. B; Pub. 10/01
Micron Technology, Inc., reserves the right to change products or specifications without notice. 2001, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRONS PRODUCTION AND DATA SHEET SPECIFICATIONS.
PRELIMINARY
SEATING PLANE C
1 A B
6.40 1.80 CTR 0.80 TYP PIN A1 ID BALL A1 1.20 MAX
6 A B C D E F G H J K L M
0.10 C
C D E F G H
8.00 0.05
61X 0.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PREREFLOW DIAMETER IS 0.40 BALL A9
J K L
11.00
C L 1.00 TYP
16.00 0.10
VSSQ NC VSS NC VDDQ DQ3 NC VSSQ NC NC VDDQ DQ2 NC VSSQ DQS VSS VREF DM CK CK# A12 CKE A11 A9 A8 A7 A6 A5 A4 VSS
NC VDDQ VSSQ NC VDDQ NC VSSQ NC VDDQ NC VDD A13 CAS# CS# BA0 A10 A1 A3
5.50 0.05
x8 (Top View)
Bottom View
1 A B C
SUBSTRATE: PLASTIC LAMINATE
6 A B C D E F G H J K L M
D E
SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or 62% Sn, 36% Pb, 2%Ag SOLDER BALL PAD: .33mm
F G H
J K L M
VSSQ DQ7 NC VDDQ NC VSSQ NC VDDQ NC VSSQ VSS VREF CK A12 A11 A8 A6 A4
DQ0 VDDQ VSSQ NC VDDQ NC VSSQ NC VDDQ NC VDD A13 CAS# CS# BA0 A10 A1 A3
D Z L B C D H J P F C
E F G H J K L M
VDD DQ2 DQ4 DQ6 LDQS LDM WE# RAS# BA1 A0 A2 VDD
DQ0 VSSQ VDDQ VSSQ VDDQ VDD CAS# CS# BA0 A10 A1 A3
Micron Technology, Inc., reserves the right to change products or specifications without notice. 2001, Micron Technology, Inc.
PRELIMINARY
22.22 0.08 0.71 0.65 TYP 0.32 .075 TYP 0.10 (2X)
SEE DETAIL A
(TOP VIEW)
x4 x8 x16 VDD VDD VDD NC DQ0 DQ0 VDDQ VDDQ VDDQ NC DQ1 NC DQ0 DQ1 DQ2 VSSQ VSSQ VssQ NC DQ3 NC NC DQ2 DQ4 VDDQ VDDQ VDDQ NC NC DQ5 DQ1 DQ3 DQ6 VSSQ VSSQ VssQ NC DQ7 NC NC NC NC VDDQ VDDQ VDDQ NC NC LDQS NC NC NC VDD VDD VDD DNU DNU DNU NC NC LDM WE# WE# WE# CAS# CAS# CAS# RAS# RAS# RAS# CS# CS# CS# NC NC NC BA0 BA0 BA0 BA1 BA1 BA1 A10/AP A10/AP A10/AP A0 A0 A0 A1 A1 A1 A2 A2 A2 A3 A3 A3 VDD VDD VDD x16 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS DNU VREF VSS UDM CK# CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS x8 VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS DNU VREF VSS DM CK# CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS x4 VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSSQ DQS DNU VREF VSS DM CK# CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS
PIN #1 ID
GAGE PLANE
0.25
0.10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
NOTE:
1. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
256Mb: x4, x8, x16 DDR333 SDRAM 256Mx4x8x16DDR333_B.p65 Rev. B; Pub. 10/01
Micron Technology, Inc., reserves the right to change products or specifications without notice. 2001, Micron Technology, Inc.
PRELIMINARY
H3
44
CKE
Input
H8
24
CS#
Input
Input Input
BA0, BA1
Input
A0, A1, A2 Input A3, A4, A5 A6, A7, A8 A9, A10, A11 A12
256Mb: x4, x8, x16 DDR333 SDRAM 256Mx4x8x16DDR333_B.p65 Rev. B; Pub. 10/01
Micron Technology, Inc., reserves the right to change products or specifications without notice. 2001, Micron Technology, Inc.
PRELIMINARY
I/O
I/O I/O
Data Input/Output: Data bus for x4 Data Strobe: Output with read data, input with write data. DQS is edge-aligned with read data, centered in write data. It is used to capture data. For the x16 , LDQS is DQS for DQ0-DQ7 and UDQS IS DQS for DQ8-DQ15. Pin 16 (H7) is NC on x4 and x8. No Connect: These pins should be left unconnected. Do Not Use: Must float to minimize noise on Vref DQ Power Supply: +2.5V 0.2V. Isolated on the die for improved noise immunity. DQ Ground. Isolated on the die for improved noise immunity. Power Supply: +2.5V 0.2V. Ground. SSTL_2 reference voltage. Address input A13 for 1Gb devices.
14, 17, 25, 43, 53 19, 50 B2, D2, C8, 3, 9, 15, 55, E8, A9 61 A1, C2, E2, 6, 12, 52, B8, D8 58, 64 F8, M7, A7 A1, A3, F2, M3 F1 F9 49 17 1, 18, 33 34, 48, 66
256Mb: x4, x8, x16 DDR333 SDRAM 256Mx4x8x16DDR333_B.p65 Rev. B; Pub. 10/01
Micron Technology, Inc., reserves the right to change products or specifications without notice. 2001, Micron Technology, Inc.
PRELIMINARY
CAPACITANCE (FBGA)
(Notes: 1-5, 14-17, 33; notes appear in DDR200/266 data sheets) (0C TA 70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V) PARAMETER Delta Input/Output Capacitance: DQs, DQS, DM (for x4 or x8 devices) DQ0-DQ7, LDQS, LDM (for lower byte of x16 devices), DQ8-DQ15, UDQS, UDM (for upper byte of x16 devices) Delta Input Capacitance: Command and Address Delta Input Capacitance: CK, CK# Input/Output Capacitance: DQs, DQS, DM (LDQS, LDM, UDM) Input Capacitance: Command and Address Input Capacitance: CK, CK# Input Capacitance: CKE DCIO DCIO DCIO DCI1 DCI2 CIO CI1 CI2 CI3 3.50 1.50 1.50 1.50 0.50 0.50 0.50 0.50 0.25 4.00 2.50 2.50 2.50 pF pF pF pF pF pF pF pF pF 13, 24 13, 24 13, 29 13, 29 13, 29 13 13 13 13 SYMBOL MIN MAX UNITS NOTES
CAPACITANCE (TSOP)
(Notes: 1-5, 14-17, 33; notes appear in DDR200/266 data sheets) (0C TA 70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V) PARAMETER Delta Input/Output Capacitance: DQs, DQS, DM (for x4 or x8 devices) DQ0-DQ7, LDQS, LDM (for lower byte of x16 devices), DQ8-DQ15, UDQS, UDM (for upper byte of x16 devices) Delta Input Capacitance: Command and Address Delta Input Capacitance: CK, CK# Input/Output Capacitance: DQs, DQS, DM (LDQS, LDM, UDM) Input Capacitance: Command and Address Input Capacitance: CK, CK# Input Capacitance: CKE DCIO DCIO DCIO DCI1 DCI 2 CIO CI 1 CI2 CI 3 4.0 2.0 2.0 2.0 0.50 0.50 0.50 0.50 0.25 5.0 3.0 3.0 3.0 pF pF pF pF pF pF pF pF pF 13, 24 13, 24 13, 24 13, 29 13, 29 13 13 13 13 SYMBOL MIN MAX UNITS NOTES
256Mb: x4, x8, x16 DDR333 SDRAM 256Mx4x8x16DDR333_B.p65 Rev. B; Pub. 10/01
Micron Technology, Inc., reserves the right to change products or specifications without notice. 2001, Micron Technology, Inc.
PRELIMINARY
na
tREFC tREFI tVTD tXSNR tXSRD
-6 (FBGA) MIN MAX -0.7 +0.7 0.45 0.55 0.45 0.55 6 13 7.5 13 0.45 0.45 1.75 -0.60 +0.60 0.35 0.35 0.35 0.75 1.25 0.2 0.2 tCH,tCL +0.70 -0.70 0.75 0.75 0.80 0.80 2.2 12 tHP - tQHS 0.50 18 42 70,000 60 72 18 18 0.9 1.1 0.4 0.6 12 0.25 0 0.4 0.6 15 1 tQH - tDQSQ 70.3 7.8 0 75 200
-6T (TSOP) -75Z MIN MAX MIN MAX UNITS NOTES -0.7 +0.7 -0.75 +0.75 ns tCK 0.45 0.55 0.45 0.55 30 tCK 0.45 0.55 0.45 0.55 30 6 13 7.5 13 ns 45,52 7.5 13 7.5 13 ns 45,52 0.45 0.50 ns 26,31 0.45 0.50 ns 26,31 1.75 1.75 ns 31 -0.60 +0.60 -0.75 +0.75 ns tCK 0.35 0.35 tCK 0.35 0.35 0.45 0.50 ns 25, 26 tCK 0.75 1.25 0.75 1.25 tCK 0.2 0.2 tCK 0.2 0.2 tCH,tCL tCH,tCL ns 34 +0.70 +0.75 ns 18,42 -0.70 -0.75 ns 18,43 0.75 0.90 ns 14 0.75 0.90 ns 14 0.80 1 ns 14 0.80 1 ns 14 2.2 2.2 ns 12 15 ns tHP tHP ns 25, 26 - tQHS - tQHS 0.60 0.75 ns 18 20 ns 46 42 70,000 40 120,000 ns 35 60 65 ns 72 75 ns 50 18 20 ns 18 20 ns tCK 0.9 1.1 0.9 1.1 42 tCK 0.4 0.6 0.4 0.6 12 15 ns tCK 0.25 0.25 0 0 ns 20, 21 tCK 0.4 0.6 0.4 0.6 19 15 15 ns tCK 1 1 tQH - tDQSQ tQH - tDQSQ ns 25 70.3 70.3 s 23 7.8 7.8 s 23 0 0 ns 75 75 ns tCK 200 200
256Mb: x4, x8, x16 DDR333 SDRAM 256Mx4x8x16DDR333_B.p65 Rev. B; Pub. 10/01
Micron Technology, Inc., reserves the right to change products or specifications without notice. 2001, Micron Technology, Inc.
PRELIMINARY