Report prepared by Ms S.

Vedavathi

FABRICATION OF MEMS PRESSURE SENSOR FOR LAB COURSE E3-222

Fabrication and characterization was done with guidance of Prof.K.N.Bhat This report details the fabrication and Characterization of Piezoresistive MEMS Pressure Sensors on double side polished p-type (100) silicon 2 inch wafers. Membrane structures of dimensions 500 X500 , 450 X450 , 400 X400 and thickness of 10 micron are realized using anisotropic wet chemical etching technique of bulk silicon. N-type single crystal piezoresistors are fabricated by phosphorous diffusion. The fabricated sensors are characterized for nominal resistance and offset voltage. Temperature compensation and signal conditioning using MAX1452 is also demonstrated. LIST OF SYMBOLS All the parameters are with reference to silicon piezoresistor. t Transverse stress l Longitudinal stress t Transverse piezoresistive coefficient l Longitudinal piezoresistive coefficient R Change in resistance R Resistance of piezoresistor Poissons ratio Vs Supply voltage Vout Output voltage INTRODUCTION: The Pressure sensors are an integral part of many systems. MEMS Pressure sensors offer low cost, on chip pressure sensing capability. Among the various transduction topologies available for the sensor, piezoresistive type is the most widely used. MEMS sensors offer compatibility with the CMOS fabrication process. This report deals with the fabrication and characterization of MEMS Pressure Sensors. The rest of report is organized as follows. Sec. I discuss briefly the theory of piezorestivity of silicon. Sec. II describes the fabrication sequence to realize the pressure sensor. Sec. III describes the procedure used to characterize the sensor, this section also describes a method of electronically compensating the non-idealities of the pressure sensor.

TABLE I: Longitudinal and transverse piezoresistance coefficients for silicon <100> wafers (Units of 1012 Pa1) with piezoresistors oriented along <110> and doping 1018 cm3

Fig. 1: Wheatstone bridge configuration of piezoresistors for pressure sensor. RA and RB are sensor resistors. A. Piezoresistance of Silicon The resistance of the silicon piezoresistor is a function of stress in the material and the orientation of the piezoresistors. The variation of resistance due to stress is given in Eqn. 1 [1].

Typical values of the piezoresistive coefficients for <110> oriented resistors are given in Tab. I [2]. B. Pressure Sensor Design The pressure sensor is realised using four piezoresistors arranged along <110> axis on a membrane in Wheatstone bridge configuration as shown in Fig. 1. The sensitivity depends on the orientation of piezoresistor and the location, the locations of piezoresistors on the membrane as shown in Fig. 2. The maximum stress on a piezoresistor for a square membrane of width 2a, thickness h and uniform applied pressure P is given by Eqn. 2.

For a 10 micron thick membrane of a=250 micron and pressure of 10 bar gives edge of 625 MPa which is lesser than yield strength of silicon (7 GPa). Using Eqn. 2 and Eqn. 1 gives.

Fig. 2: Placement of piezoresistors on the membrane.

Where is the Poisons ratio which is 0.3 for silicon. This gives R/R = 0.13825. Refering to Fig. 1 and assuming that all the resistors are equal the output voltage is given by Eqn. 4.

II. FABRICATION STEPS Initially 2 inch wafers of <100> prime quality double side polished Si wafers are taken. The thickness of the wafers is reduced to 230 micron by KOH etching (Sec. II-E2). The fabrication steps for realizing a membrane for the pressure sensor are shown in Fig. 3 and described below. Step 1: p-type wafers are cleaned with piranha cleaning described in Sec. II-A. Step 2: Thermal oxidation to grow 200 nm oxide as described in Sec. II-B1. Step 3: a) Photoresist is coated on the front surface of the samples and patterned as described in Sec. IIC. b) The back side of the wafer is coated with wax to prevent etching of back oxide. Step 4: The front oxide is etched as described in Sec. II-D for duration of 45 sec. Step 5: a) KOH etching of bulk silicon on the front side to obtain a test structure of depth 10 micron is done (Sec. II-E1). b) The wafers are again given a piranha clean (Sec. II-A). c) The wafers are thermally oxidized to grow 1 micron oxide as described in Sec. II-B2.

Step 6: Photoresist is coated on the back surface of the samples and patterns are transferred with the help of alignment marks. The parameters of photolithography are described in Sec. II-C. Step 7: The back oxide is etched as described in Sec. II-D for duration of 3.5 min. Step 8: Etching of bulk silicon from back side is carried out in two step process. a) Initial KOH etching is done for 2 hours to etch 120 of silicon as described in Sec. II-E2. b) This is followed by TMAH etching to the remaining 100 of silicon on the back side (Sec. II-F). A through hole through the test structure indicates a membrane of 10 . Step 9: Photolithography (Sec. II-C) is done to transfer the patterns of piezoresistors on thermally grown oxide on the front side of the wafer. This is followed by oxide etching described in Sec. II-D. The photoresist is removed in acetone followed by cleaning in IPA and blow drying with N2. Step 10: Phosphorous diffusion is done as described in Sec. II-G to realise n-type piezoresistors. The diffusion of phosphorous takes place in regions not covered by the oxide. Step 11: The native oxide formed will be formed when the wafers are kept for a long time. This is removed by 1:10 mixture of HF and DI water. This is followed by thermal evaporation of aluminium on the wafers (Sec. II-H) to form the contacts of piezoresistors. Step 12: The patterns for aluminium contacts are transferred through lithography (Sec. II-C) and this is followed by aluminium etching described in Sec. II-I. The photoresist is removed in acetone followed by cleaning in IPA and blow drying with N2.The wafers then undergo an annealing step (Sec. II-J). After which the wafers are characterized as described in Sec. III. An approach to calibrate the sensors is described in Sec. III-C. Note: After every chemical treatment the wafers are thoroughly cleaned with DI water and dried using N2 blowing. If the wafers are stored for a long time. It is cleaned and dipped in dilute HF to remove the native oxide. It is followed by DI rinse and blow drying with N2. The wafers are dehydrated on a hot plate at 250 C for about an hour A. Piranha Cleaning The wafers are cleaned using Piranha Solution. Piranha solution contains H2SO4:H2O2 in the ratio of 3:1 by volume. The reaction is exothermic. The wafers are dipped in the solution for 15 min. Organic impurities and alkali ions are removed due to strong oxidizing property of the solution. The surface of silicon is passivated with (OH) groups making it hydrophilic. After Piranha cleaning the wafers are dipped in dilute HF (HF: DI water: 1:50) at room temperature to remove the native oxide. This is followed by N2 blow drying. The completion of etching of the native oxide layer is confirmed by the appearance of hydrophobic Si surface (Si is hydrophobic, while SiO2 is hydrophilic)

Fig. 3: Steps to fabricate membrane for MEMS pressure sensor described is Sec. II. The following general precautions are to be observed during wafer cleaning. 1) At temperatures higher than 80 C H2O2 can dissociate and Si Wafer can get oxidized in an uncontrolled way. 2) Teflon containers are used for dilute HF dip after piranha cleaning. B. Thermal Oxidation Thermal oxidation is carried out for growing SiO2 layer on the cleaned Si surfaces. The SiO2 layer acts as a mask for Si etchants. 1) 200 nm SiO2 growth: A 200 nm thick SiO2 layer is required to be grown in the first step of oxidation using dry-wet- dry oxidation sequence. This layer acts as a mask for 10 bulk Si etching. The steps for thermal oxidation are as follows. Set the oxidation furnace temperature to 1000 C and purge the furnace with pure N2 gas with flow rate of 1 liter/min for 15 min. Load Wafers in oxidation furnace in a N2 ambient Carry out dry oxidation for 10 min.

 Next, bubble oxygen at a flow rate of 1 liter/min through DI water heated in the bubbler. The oxygen carries water vapors along with it to the wafer surface enabling wet oxidation to take place. Carry out wet oxidation for 25 min.

Carry out dry oxidation for 10 min. Hence a 200 nm of SiO2 is grown by the above process. At the end of this duration, the ambient is again switched to N2 and wafers are unloaded. The dry-wet-dry sequence used in the process helps achieve a good quality Si-SiO2 interface (enabled by dry oxidation) and at the same time a faster oxidation rate is achieved (due to wet oxidation). The color of 200 nm oxide is light yellow. 2) 1 SiO2 growth: A 1 thick SiO2 layer is grown in Step 5c of fabrication sequence by using dry-wet-dry oxidation sequence. This layer acts as a mask layer for realizing membrane for pressure sensor. The steps for thermal oxidation are as follows: Set the oxidation furnace zone temperature to 1000 C and purge the furnace with N2 gas at a flow rate of 1 liter/min. Load Wafers in oxidation furnace in a N2 ambient. Carry out dry oxidation for 10 min. Bubble oxygen through hot DI water. The oxygen carries water vapors along with it to the wafer surface enabling wet oxidation to take place. Carry out wet oxidation for 3 hours. Carry out dry oxidation for 10 min. The color of 1 oxide is green-violet. C. Photolithography Photolithography is carried out on the wafers to transfer the patterns onto the wafer for further etching process. The details of photolithography are given in Tab. II

TABLE II: Photolithography steps

D. Oxide Etching During the thermal oxidation (Sec. II-B), the back surface of wafers will be oxidised forming SiO2. This oxide should not be removed as it acts as mask against bulk silicon etching. The back oxide is protected with wax. Buffered HF (100 gm of NH4F, 150 ml of DI water = V with (V/3) of HF) is used to etch the front oxide. This gives etch rate of about 300 nm/min. Complete removal of the oxide can be noticed when the hydrophilic oxide turns to hydrophobic nature of the underlying silicon. The wafers are cleaned with Trichloroethylene to remove wax followed by acetone and IPA cleaning to remove the photoresist. The wafers are cleaned with DI water and dried (blow drying) with N2. E. KOH Etching KOH is an anisotropic etchant of silicon. Selectivity of KOH etching for <100> :< 110> :< 111> is 400:600:1. A limitation of KOH etching is that it attacks the oxide, also it is not preferred if the process involves fabrication of MOS transistors. Fig. 4 shows the etching profile using KOH. KOH etching steps are as follows. 1) 10 Test Structure Etching: The test structure of 10 is fabricated by etching of silicon with the following process parameters. 40 % (by weight) KOH solution is prepared. The solution is heated to 75C (etch rate of 40 /hour). The duration of etching is 6 min and 40 sec. 2) Back Side Etching: The membrane of 10 is fabricated by etching of silicon in two step process, initially by KOH etching for 2 hours followed by TMAH etching for 2 hours and 15 min. The first step involves KOH etching described below. 30 % (by weight) KOH solution is prepared. The solution is heated to 75C (etch rate of 60 /hour). 50 % IPA is added by volume to the solution to reduce the reaction rate (Low dielectric constant of IPA) and to get smooth surface. The IPA forms an immiscible mixture with KOH solution. IPA is added periodically to replenish the evaporated liquid. KOH etching is carried out for 2 hours to etch 120 of Si.

Fig. 4: Anistropic etching of Silicon using KOH or TMAH F. TMAH Etching TMAH (Tetramethyl ammonium hydroxide) is an anisotropic etchant of silicon. Selectivity of TMAH etching is <100> :< 111>: 40:1. Even though TMAH is less selective compared to KOH, TMAH has the following advantages over KOH etching. It almost does not attack the oxide or SiN. Selectivity against oxide is greater than 1000. It is highly compatible to CMOS processing.

 Ammonium persulphate is added periodically, this prevents formation of deposits on silicon and gives a smooth surface. Since KOH attacks oxide, the bulk silicon etching is carried out in a two step process. The TMAH etching is described below. 25 % TMAH solution is diluted to 5 % solution using DI water. The solution is heated to 75 C (etch rate of 45 micron/hour). Ammonium Persulphate (0.5 gm for 60 ml solution) is added every 15 min to avoid deposition of impurities on silicon surface. TMAH etching is done for duration of 2 hours and 15 min to etch additional 100 micron of Si and realize a membrane of 10 micron. After the bulk etching of Si, the oxide etches by 200 nm. Membranes of dimensions 500 micronX500micron, 450micronX450micron and 400micronX400micron are realized.

Fig. 5: Membrane realized after bulk etching of silicon.

Fig. 6: Intersection of <110> and < 110> planes formed by anisotropic etching of silicon.

Fig. 7: Alignment mark of the top surface as seen through the membrane, alignment marks are used to align the masks during photolithography.

G. Phosphorous Diffusion The single crystal piezoresistors of n-type are formed by diffusion of phosphorous. The phosphorous diffuses through the windows etched on thermally grown oxide of the p-type wafer. The piezoresistor patterns are shown in Fig. 8.

Fig. 8: Developed piezoresistor patterns after photolithography for oxide etching followed by phosphorous diffusion.

The procedure for phosphorous diffusion is detailed below, 1) The furnace is heated to the following temperature profile. Feedend: 932 C. Middle of furnace: 900 C. Load end: 945 C. 2) Nitrogen is flushed through the furnace for 10-15 min at flow rate of 1 liter/min to remove contaminants. Wafers are then placed horizontally in the furnace. 3) POCl3 is used as a precursor for diffusing of phosphorous which is kept at in an ice bath to maintain constant vapor pressure and hence uniform concentration in the furnace during reaction. Maintaining the concentration is essential to control dosage of phosphorous diffused into Si. 4) Nitrogen and Oxygen gases are bubbled through it at flow rates of 0.4 liter/min and 0.6 liter/min respectively. These gases carry POCl3 vapors to the wafers with help of carrier nitrogen at a flow rate of 3 liter/min. 5) Nitrogen helps in flushing the byproducts of the chemical reaction and oxygen aids the chemical reaction. The chemical equation for the reaction is given below: 4POCl3 + 3O2 2P2O5 + 5Si 2P2O5 + 6Cl2 4P + 5SiO2 (9) (10)

6) P2O5 reacts with silicon to form phosphosilicate glass (PSG) and phosphorous diffuses through silicon. 7) Diffusion process for 30 min on one sample wafer and 15 min on another is done. The formation of PSG is observed by a dark blue color on the wafer. 8) PSG is removed by a solution of 1.5 ml HF and 1 ml HNO3 in 30 ml DI water. PSG removal takes about 20 sec. After the diffusion of phosphorous the sheet resistivity reduces which is quantified below. The measurements are done using four point probe. Sheet resistance measurement Before doping: 24.6375 /sq After doping for 30 min: 10.203 /sq After doping for 15 min: 14.63 /sq H. Thermal Evaporation of Aluminum To make metallic contacts for the piezoresistors, aluminum is deposited on the substrate by thermal evaporation. Around, 100 nm of aluminum is deposited on the substrate by this process. The deposition conditions are described in Tab. III

TABLE III: Parameters for thermal evaporation of aluminum

The procedure to obtain the required pressure in the chamber for aluminum evaporation is similar to the procedure for RF sputtering as described in Appendix. A. The only difference is that the thermal evaporation is carried out at a lower pressure of 105 mbar without inert gas ambient or any applied

electric field between the substrate and the target. Aluminum is resistively heated with a tungsten filament. The metal melts and evaporates, these vapors move straight up (low pressure chamber) and deposit on the substrate. I. Aluminum Etching After the thermal deposition of aluminum on the samples, photolithography is done to define the patterns for contacts of piezoresistors. Aluminum etching is done with 19:4:1 solution of H3PO4: DI water: HNO3 which gives 1.6 nm/min at room temperature for a duration of 60 seconds. The pattern after etching of aluminum is shown in Fig. 9 and Fig. 10.

Fig. 9: Patterned aluminum contacts of open bridge configurations.

Fig. 10: Encircled region shows the contact between circuited piezoresistor and aluminum

J. Annealing After thermal deposition of aluminum, the wafers are annealed in forming gas N2: H2:: 9 : 1 gas with flow rate of 1 liter/min at 400 C for 35 min. This will reduce the resistance of the aluminum contacts due to expansion of crystal grain boundaries. III. CHARACTERIZATION OF PRESSURE SENSOR Post fabrication, characterization of the sensor chip is an important step in determining the sensor characteristics. Moreover, characterization is an important step because packaging process of the sensor is an involved process and therefore only good sensor dies should undergo packaging. Some of the nonidealities in a pressure sensor are: 1) Deviation from linear response for large pressures due to second order effects of piezoresistors. 2) Output voltage dependence on temperature. 3) Offset voltage at no applied pressure. The fabricated pressure sensor wafers are characterized for the following parameters: 1) Bridge resistances 2) Offset Voltage A. Bridge resistances The fabricated piezoresistor values are measured by taking I-V characteristics using Agilent 4155C Semiconductor Parameter Analyzer as shown in Fig. 12. Open bridge and closed bridge configurations are tested. The open bridge configuration shown in Fig. 11 allows us to measure resistance of every

individual piezoresistor, whereas from closed bridge we can measure the net bridge resistance and the offset voltage. Tab. IV lists the measured resistance values.

Fig. 11: open Bridge to measure the resistances of the individual resistors of the bridge. RA and RB are sensor resistors

TABLE IV: Open circuit bridge resistance measurements.

Fig. 12: Measurement setup to characterize the pressure sensor.

B. Offset Voltage Offset voltage is one of the non-idealities in the sensor and is defined as the sensor bridge output voltage for zero applied differential pressure. Offset voltage results from mismatch in bridge resistances. The mismatch in resistance values is caused by: 1) Deviation in resistor geometries that can cause change in fabricated resistance value. 2) Residual stresses in the membrane due to fabrication process that causes variations in resistance values due to piezoresistive effect. 3) Variation in contact pad resistances.

The closed bridge configuration is used for the measurement of offset voltage. The schematic of measurement is shown in Fig. 1. The measured sensor offset voltage values are listed in Tab. V.

TABLE V: Closed bridge offset voltage measurements.

C. Calibration of Pressure Sensors An ideal sensor should present a linear variation in output voltage for different pressure inputs and the sensitivity should be same over the complete temperature range. Due to the dependence of resistance of piezoresistors on temperature, the output voltage varies with temperature. This necessitates temperature compensation which can be done using a Precision Sensor Signal Conditioner MAX1452. The working of MAX1452 is described in this section. 1) Offset Correction Using MAX1452: Characterization of sensor chips over pressure and temperature show temperature sensitivity of piezoresistors. Compensation over temperature range is done using MAX1452 Signal Conditioning IC from MAXIM Inc. The functional block diagram of the IC is shown in Fig. 13 and its used for ratio metric operation is shown in Fig. 14. The IC has an on-chip EEPROM that holds the compensation coefficient values. These values are indexed by temperature measured by an on-chip temperature sensor which senses the temperature every 1 ms. Compensation against temperature is achieved by routing the compensation coefficient values through a Offset TC DAC to a programmable gain amplifier. Offset voltage correction is done by this method.

Fig. 13: Functional block diagram of MAX1452. [4]

Fig. 14: Ratiometric sensing circuit using MAX1452. [4]

D. Full Scale Output Correction This process is done in two steps, first a coarse gain correction of the PGA is done digitally to compensate for the non-linear behavior of the sensor. The second fine gain correction is achieved by changing current drive to the sensor bridge. Current is pumped to the sensor bridge and the bridge voltage is taken as the reference of full scale offset temperature control DAC (FSOTC-DAC) and temperature control DAC (TC-DAC). This makes the output of the FSOTC-DAC follow the bridge voltage (which varies with temperature). The FSOTC-DAC output voltage is used to compensate the current fed to the bridge. The bridge voltage is also used for the OTC DAC to add appropriate compensating voltage to the output of PGA. The calibration was carried on a Off-the shelf pressure sensor (Fig. 15) and the results are presented in Fig. 16 and Fig. 17. Experimental data shows variation in sensor output voltage with temperature for the same pressure input.

Fig. 15: Pressure sensor used for calibration with MAX1452.

Fig. 16: Variation (Without compensation) of output voltage of the sensor with temperature (40 V/C) for a given variation of the pressure applied.

Fig. 17: Variation (With compensation) of the output given by MAX1452 for different temperatures (7 V/C wrt bare sensor output). This figure shows that the variation with temperature is reduced.

CONCLUSION MEMS Piezoresistive Pressure Sensors were successfully fabricated with membrane structures of dimensions 500 X500, 450X450 , 400X400 and thickness of 10 . The membranes are realized using anisotropic wet chemical etching technique of bulk silicon. n-type single crystal piezoresistors are fabricated by phosphorous diffusion. The fabricated piezoresistors had an average resistance of 1 K due to considerable contact resistance and maximum offset voltage of 40 mV/V equivalent to 4 % offset. Utility of MAX1452 for temperature compensation was demonstrated on a commercial off-the shelf Pressure Sensor. The temperature sensitivity of output reduced from 40 V/C to 7 V/C.