EC2028 - Electronics Circuit Laboratory-I

Slots: Q, R, SA+SB, T Course Faculty: Dr. Rama Komaragiri (Q, R); Mr. Jaikumar M.G (SA+SB, T),

Experiment 1: Clipper and Clamper circuits

Ref: Section 2.3 in Donald A Neamen Instructions: 1) The students are supposed to assemble at least 5 Clipper circuits, which includes the following types: (i) Parallel clipper circuit (ii) Series clipper circuit (iii) Double clipper Output waveforms, Transfer characteristics and other behaviors need to be observed and analyzed Students are supposed to assemble at least 5 Clamper circuits.

Experiment 2: Study of Biasing Circuits

Reference: Donald A Neamen, Sedra & Smith Instructions: 1) Refer the data sheet of BC547 and SL100, note down the different break down voltages, (Minimum, Typical and Maximum) and maximum collector current. 2) Design and assemble the biasing circuits (Fixed bias and Voltage Divider Bias) for the given BC547 transistor to operate it at points A, B and C in the given load line below.

Fig. 1: Load line for experiment 2 3) Measure collector voltage (Vc), Emitter voltage (Ve) and Base voltage (Vb) of the transistor. Verify the operating point and Vbe value in each case. 4) Apply a sine wave of amplitude (20mV-50mV pp, 1 kHz) in the voltage divider circuit in the above set up through a 10F capacitor. 5) Vary the amplitude of the input waveform and observe output waveform at collector of the transistor through another 10F capacitor. 6) Find the maximum amplitude of input signal that can be given to this circuit so that the output is un-distorted. 7) Replace BC547 transistor with SL100 transistor and repeat step (3).
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Note: Simulation results may be submitted along with the lab report in the subsequent week.

Experiment 3: Study of CE amplifier-1

Reference: Donald A Neamen, Sedra & Smith Instructions: 1) Design and assemble a C-E amplifier circuit with voltage divider biasing for the given BC547 transistor to operate it at point A in the load line given below.

Fig. 2: Load line for experiment 3 2) Measure collector voltage (Vc), Emitter voltage (Ve) and Base voltage (Vb) of the transistor. Verify the operating point. 3) Apply a 1 kHz sine wave of 20mV pp, to the base of the transistor through a suitable capacitor (CC1, Approx. 10F). 4) Vary the amplitude of the input waveform and observe output waveform at collector of the transistor through another capacitor (CC2, Approx. 10uF). Tabulate the output voltage and calculate gain. Repeat this for at least 3 different input amplitudes. 5) Add a load (RL = 10K) across the output (After CC2). Apply a sine wave of 20mVpp. (i) Measure the voltage across RL and calculate gain. (ii) Repeat (a) for three different values of RL (RL<< Rc, RLRc, RL >>Rc). 6) Measure the input impedance and output impedance without any RL. Compare with the theoretical values. 7) Place a capacitor with a suitable value CE (approximately 47F) parallel to the emitter resistor RE. Observe the output without RL. Measure the gain as did in step 4. Make sure that there is no distortion at the output waveform before taking measurements. 8) Repeat step 6, keeping CE. 9) Observe the changes in gain, input impedance and output impedance with and without CE. Note: (a) Additional references on finding input impedance and output impedance may be required. (b) Simulation results may be submitted along with the lab report in the subsequent week.

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Experiment 4: Study of CE amplifier -2 (Frequency response)

Reference: Donald A Neamen, Sedra & Smith Instructions: Part 1: 1) Design a CE amplifier to operate at 2mA, 6V, plot its frequency response and estimate the bandwidth. 2) Design steps: In order to make the operating point at the middle of the load line, assume the dc conditions VRc = 40% of Vcc, VRe = 10% of Vcc and Vce = 50% of Vcc. Hence take Vcc to be 12V. Now apply KVL to the output loop to find Rc and Re. Take Ic=Ie. Design of voltage divider R1 and R2: Assume the current through R1 as 10Ib and that through R2 as 9Ib for a stable voltage across R1 and R2 independent of the variations of the base current. Now VR2 is voltage drop across R2=VBE + VRE, i.e., VR2 = VBE + VRE = 0.7 + 1.2 = 1.9 V; Also, VR2=9IbR2 =1.9V. But Ib = Ic/. Take as 200 for BC 547 and find the value of R2. Now VR1 = voltage across R1 = VCC -VR2 = 12 V - 1.8 V = 10.2 V. Also, VR1 = 10Ib R1 = 10.2 V. Then find R1. Design of coupling capacitors CC1 and CC2: XC1 should be less than the input impedance of the transistor. Here, Rin is the series impedance. Then XC1 <= Rin/10. Here Rin = R1 || R2 || (1 +re) because Re is bypassed. Hence find CC1 (Take f=100 Hz). Similarly, XC2 <= Ro/10, where Ro = Rc. Hence find CC2. Design of bypass capacitors CE: to bypass the lowest frequency (say 100Hz), XCE should be less than or equal to the resistance RE. i.e., XCE <= RE/10. Hence find CE. 3) Assemble the circuit with the designed components and note down the dc conditions. Measure Vb, Vce and Ic and ensure that they are same as the designed values. 4) Apply a 20 mV p-p (small signal), 5 kHz sinusoid to the input of the amplifier through CC1 and observe the output amplitude without distortion. Calculate the mid-band gain. It should be almost equal to gmRc. 5) Vary the frequency of the input from 100 Hz to say 1 MHz in suitable steps (take more readings in the rising and falling portions of the response). Keep the input amplitude constant at each frequency and observe the output p-p amplitude. Tabulate and plot the frequency response of the amplifier. (Plot the voltage gain in decibels versus the log of frequency to get a better dynamic range). From the plot calculate the bandwidth of the amplifier. 6) Now remove CE from the circuit and repeat step 5. Plot the two frequency responses in the same graph. 7) Find out the mid-band gain bandwidth product in both cases. Part 2: Square wave Testing 1) Apply three different square waves of 20mV p-p amplitude at 100Hz, 10 kHz and 200 kHz to the input of the same CE amplifier. 2) Observe and note down the output waveform in each case. From the waveforms, calculate the upper and lower cut off frequencies and hence the bandwidth of the amplifier.

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Experiment 5: Study of RC coupled two stage CE amplifier (Cascade)

Reference: Donald A Neamen, Sedra & Smith Instructions: 1) Design and set up two identical CE amplifiers to operate at 2mA, 6V. You can use the same design procedure adopted in the previous experiment. 2) Set up both the amplifiers separately. Apply a small signal to the input of both the amplifiers after verifying the dc conditions and find out the mid-band gains. 3) Now cascade both the amplifiers through CC2 of the first stage. Apply a small signal through a voltage divider at the input. Find out the mid-band gain after obtaining an undistorted output. You may use a 10k pot as load at the second stage and vary the pot to get an undistorted maximum at the output. Note down the value of the pot resistance at which you get an undistorted maximum. Account for the changes in the expected and observed values of the gain. (You may use the voltage divider configuration shown below for applying the input).

Fig. 3: Example voltage divider configuration for experiment 5 4. Obtain the frequency response of the cascaded stage. Tabulate and plot the frequency response. From the response calculate the bandwidth of the cascaded amplifier. 5. Now replace the emitter resistor at the first stage by a partially bypassed one. You may use a combination of a 180 and 470 in series here and bypass the 470 resistor. 6. Apply a suitable small signal at the input through the voltage divider. Obtain an undistorted output and plot the frequency response of this amplifier. Here again you may use a suitable resistance as the load to get an undistorted maximum output.

Experiment 6: Study of JFET Common Source amplifier and its frequency response
Reference: Donald A Neamen, Sedra & Smith Instructions: 1) Design and set up a common source JFET amplifier for a mid-band gain of 10 and plot its frequency response 2) Design steps: Use JFET BFW 10. Let RG=1 M. From the JFET characteristic curves select IDSS= 9.5 mA, Vp=5.5V. Let ID=1 mA. Now transconductance (gm) is given by:

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gm =
Voltage gain Av=gm RD, Hence RD= 2k.

2 I DSS ID Vp I DSS

2

(1.1)

V I D = I DSS 1 GS Vp

(1.2)

For maximum symmetrical swing ID=IDSS/2; Hence VGS=0.3Vp=1.6V. Now VGS=ID Rs; Rs= 330. VDsat=VGS-Vp = 3.9V. VDS = IDRD+ VDsat; VDD= VDS+ID(RD+RS); VDD=25V. Zin=RG=1 M; Xcc1=Zin/10; CC1= 0.022F; XCc2=Zo/10=RD/10; Cc2=6.8F; XCs=RS/10; CS=47F

Fig. 4: Schematic of JFET CS amplifier 3) Assemble the circuit and check the DC conditions. Apply a 100mV p-p sinusoidal signal to the gate input of the amplifier and observe the output at a frequency of say 5kHz. Verify that the mid-band gain is same as the designed value. 4) Vary the input signal from 50 Hz to 2 MHz in suitable steps. Observe, tabulate and plot the frequency response. From the response calculate the bandwidth. 5) Measure the input and output impedances of the amplifier. Compare with the corresponding values of a CE amplifier.

Experiment 7: Transistor Switching Circuits

Reference: Donald A Neamen, Sedra & Smith Instructions: Part 1: 1) Design the following circuit. Assume Ic = 2mA, Vcc = 10V, VCESat=0.2V, = 200. Design Steps:

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RC = RB =
Where

VCC VCESat and IC Vi VBESat I BSat

I BSat = IC Vi

(1.3)

(1.4)

Input to the circuit is a pulse.

Fig. 5: Transistor Switching Circuits 2) Observe the output for voltage levels; rise time, fall time etc. for the following cases: i) Input frequencies 1 kHz and 5 kHz. ii) Higher frequencies (eg. 500 kHz). Part 2: 1) Design the following circuit. Assume Ic = 10mA, VLED= 1.5V and assume RB as in previous case. Observe the behavior of LED with varying frequency at input.

Fig. 6: Circuit for LED behavior

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Part 3: Design the following circuit shown in fig. 7.

Fig. 7: Circuit for part 3, experiment 7 Design steps:

VC = V f + (Vint V f ) e t / RC C

(1.5)

Assume VC= 3V, Vf=VCC, Vint=VCESat, RC same as previous case. Observe the output for the following cases: (i) C as the calculated value. (ii) C = (1/2)*calculated value. (iii) C = 2*calculated value. Part 4: Design the following circuit with given assumption. Assume Ic = 30mA (Taking 12V, 500 relay), =50. Observe the behavior of bulb in two cases when Vi = 5V, Vi = 0.

Fig. 8: Circuit for part 4, experiment 7

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Experiment 8: Study of RC Phase Shift Oscillator

Reference: Donald A Neamen, Sedra & Smith Instructions: To design an RC phase shift oscillator to generate a sine wave of 5kHz frequency.

Fig. 9: Circuit for part 4, experiment 8 1) Design the basic amplifier to operate at the Q-point (0.2 mA, 5V); gain=100, Vcc=10V. 2) Check the dc conditions and give a small signal at the input to ensure that the amplifier gives you a good voltage gain. Now connect the feedback network as shown in the fig. 9 after removing the coupling capacitor. Check the output Vf on the CRO. It should almost be in phase with the input. 3) Now remove the input signal, connect the port of feedback network to the base of basic amplifier as shown in the figure below, connecting the resistance that will come as input resistance to the amplifier, as a variable (R5) and adjust that to get the exact regenerated signal with exact phase. 4) Measure the frequency and amplitude of the sinusoidal signal thus obtained, on the CRO. 5) Change the value of the capacitances (C3, C4 and C5) to double their previous value and observe the effect on the output. 6) To design the feedback network let us consider a value of resistance, which is greater than hie so that network can be balanced by adjusting the value of resistance that will come into series with the input of amplifier. If R=1.8k, assuming hie of the transistor to be 1.3k. Design for a frequency of 5 kHz (you have to find the value of capacitances, C3, C4, C5).
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