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The basic communications system has: 1.1.1 Transmitter: The sub-system that takes the information signal and processes it prior to transmission. The transmitter modulates the information onto a carrier signal, amplifies the signal and broadcasts it over the channel 1.1.2 Channel: The medium which transports the modulated signal to the receiver. Air acts as the channel for broadcasts like radio. May also be a wiring system like cable TV or the Internet. 1.1.3Receiver: The sub-system that takes in the transmitted signal from the channel and processes it to retrieve the information signal. The receiver must be able to discriminate the signal from other signals which may using the same channel (called tuning), amplify the signal for processing and demodulate (remove the carrier) to retrieve the information. It also then processes the information for reception (for example, broadcast on a loudspeaker).

Figure 1.1 Basic blockdiagram of communication system


An AM receiver processes amplitude-modulated signals received by its antenna. It delivers an output that is a reproduction of the signal that originally modulated the rf

carrier at the transmitter. The signal can then be applied to some reproducing device, such as a loudspeaker, or to a terminal device, such as a teletypewriter. Actual AM receivers vary widely in complexity. Some are very simple; others contain a large number of complex circuits. 1.3 FUNCTIONS: Whatever its degree of sophistication, a receiver must perform certain basic functions to be useful. These functions, in order of their performance, are reception, selection, detection, and reproduction. 1.3.1 Reception Reception occurs when a transmitted electromagnetic wave passes through the receiver antenna and induces a voltage in the antenna. 1.3.2 Selection Selection is the ability of the receiver to select a particular frequency of a station from all other station frequencies appearing at the antenna of the receiver. 1.3.3 Detection Detection is the action of separating the low (audio) frequency intelligence from the high (radio) frequency carrier. A detector circuit is used to accomplish this action. 1.3.4Reproduction Reproduction is the action of converting the electrical signals to sound waves, which can then be interpreted by your ear as speech, music, and the like. An example of this might be the stereo speakers in your car. 1.4 RECEIVER CHARACTERISTICS Sensitivity, noise, selectivity, and fidelity are important receiver characteristics. These characteristics will be useful to you when performing receiver tests. They can help you

to determine whether a receiver is working or not or in comparing one receiver to another. 1.4.1 Sensitivity: The ability of a receiver to reproduce weak signals is a function of the sensitivity of a receiver. The weaker a signal that can be applied to a receiver and still produce a certain value of signal output, the better the sensitivity rating. Sensitivity of a receiver is measured under standardized conditions. It is expressed in terms of the signal voltage, usually in the microvolts that must be applied to the antenna input terminals to give an established level of the output. The output may be an ac or dc voltage measured at the detector output or a power measurement (measured in decibels or watts) at the loudspeaker or headphone terminals. 1.4.2 Noise : All receivers generate a certain amount of noise, which you must take into account when measuring sensitivity. Receiver noise may originate from the atmosphere (lightning) or from internal components (transistors, tubes). Noise is the limiting factor of sensitivity. You will find sensitivity is the value of input carrier voltage (in microvolts) that must be applied from the signal generator to the receiver input to develop a specified output power. 1.4.3 Selectivity: Selectivity is the degree of distinction made by the receiver between the desired signal and unwanted signals. You will find the better the ability of the receiver to reject unwanted signals, the better its selectivity. The degree of selection is determined by the sharpness of resonance to which the frequency-determining circuits have been engineered and tuned. You usually measure selectivity by taking a series of sensitivity readings. As you take the readings, you step the input signal along a band of frequencies above and below the circuit resonance of the receiver; for example, 100 kilohertz below to 100 kilohertz above the tuned frequency. As you approach the tuned frequency, the input level required to maintain a given output level will fall. As you pass the tuned

frequency, the required input level will rise. Input voltage levels are then compared with frequency. They can be plotted on paper or you might view them on an oscilloscope. They would appear in the form of a response curve. The steepness of the response curve at the tuned frequency indicates the selectivity of the receiver. 1.4.4 Fidelity: The fidelity of a receiver is its ability to accurately reproduce, in its output, the signal that appears at its input. You will usually find the broader the band passed by frequency selection circuits, the greater your fidelity. You may measure fidelity by modulating an input frequency with a series of audio frequencies; you then plot the output measurements at each step against the audio input frequencies. The resulting curve will show the limits of reproduction. You should remember that good selectivity requires that a receiver pass a narrow frequency band. Good fidelity requires that the receiver pass a broader band to amplify the outermost frequencies of the sidebands. Receivers you find in general use are a compromise between good selectivity and high fidelity. 1.5 SUPERHETERODYNE RECEIVER: The superheterodyne is the type receiver most familiar to you. You probably see one daily in your home in the form of an AM and/or fm radio. We will discuss the basic workings of both AM and fm types and their differences. 1.5.1 Heterodyning: As you know the intermediate frequency is developed by a process called heterodyning. This action takes place in the mixer stage (sometimes called a converter or first detector). Heterodyning is the combining of the incoming signal with the local oscillator signal. When heterodyning the incoming signal and the local oscillator signal in the mixer stage, four frequencies are produced. They are the two basic input frequencies and the sum and the difference of those two frequencies. The amplifier that follows (IF amplifier) will be tuned to the difference frequency. This difference frequency is known as the intermediate frequency (IF). A typical value of IF for an AM

communications receiver is 455 kilohertz. The difference frequency is a lower frequency than either the rf input or oscillator frequencies. This lower frequency gives slightly better gain but does increase the chances of image frequency interference. Image frequencies will be discussed later in this chapter. 1.5.2 Detection: Once the IF stages have amplified the intermediate frequency to a sufficient level, it is fed to the detector. When the mixer is referred to as the first detector, this stage would be called the second detector. The detector extracts the modulating audio signal. The detector stage consists of a rectifying device and filter, which respond only to the amplitude variations of the IF signal. This develops an output voltage varying at an audio-frequency rate. The output from the detector is further amplified in the audio amplifier and is used to drive a speaker or earphones. 1.6 FREQUENCY MODULATED RECEIVER: The function of a frequency-modulated receiver is the same as that of an AM superheterodyne receiver. You will find some important differences in component construction and circuit design caused by differences in the modulating technique.

Figure 1.2 Superheterodyne reciever

Figure 1.10 is a block diagram showing waveforms of a typical fm superheterodyne receiver. Comparison of block diagrams in figures 2-9 and 2-10 shows that in both AM

fm receivers, the amplitude of the incoming signal is increased in the rf stages. The

mixer combines the incoming rf with the local oscillator signal to produce the intermediate frequency, which is then amplified by one or more IF amplifier stages. You should note that the fm receiver has a wide-band IF amplifier. The bandwidth for any type of modulation must be wide enough to receive and pass all the side-frequency components of the modulated signal without distortion. The IF amplifier in an fm receiver must have a broader bandpass than an AM receiver. Sidebands created by fm differ from the AM system. You should recall that the AM system consists of a single set of side frequencies for each radio-frequency signal modulated. An fm signal inherently occupies a wider bandwidth than AM because the number of extra sidebands that occur in an fm transmission is directly related to the amplitude and frequency of the audio signal. You should observe that only two fundamental sections of the fm receiver are electrically different from the AM receiver. These are the discriminator (detector) and the limiter. Beyond the IF stage, the two receivers have a marked difference. AM demodulation involves the detection of variations in the amplitude of the signal; fm demodulation is the process of detecting variations in the frequency of the signal. In fm receivers a DISCRIMINATOR is a circuit designed to respond to frequency shift variations. A discriminator is preceded by a LIMITER circuit, which limits all signals to the same amplitude level to minimize noise interference. The audio frequency component is then extracted by the discriminator, amplified in the af amplifier, and used to drive the speaker. 1.6.1 Advantages: In normal reception, fm signals are almost totally absent of static while AM signals are subject to cracking noises and whistles. Fm followed AM in development

and has the advantage of operating at a higher frequency where a greater amount of frequencies are available. Fm signals provide much more realistic sound reproduction because of an increase in the number of sidebands. This increase in the number of sidebands allows more of the original audio signal to be transmitted and, therefore, a greater range of frequencies for you to hear. As you can see, fm requires a wide bandpass to transmit signals. Each transmitting station must be assigned a wide band in the fm frequency spectrum. During fm transmissions, the number of significant sidebands that must be transmitted to obtain the desired fidelity is related to the deviation (change in carrier' frequency) divided by the highest audio frequency to be used. At this point you may want to review chapter 2 of NEETS, Module 12, Modulation Principles. For example, if the deviation is 40 kilohertz and the highest audio frequency is 10 kilohertz, the modulation index is figured as shown below:

In this example, a modulation index of 4 equates to 14 significant sidebands. Because the audio frequency is 10 kilohertz and there are 14 side-bands, the bandwidth must accommodate a 140-kilohertz signal. You can see this is considerably wider than the 10to-15-kilohertz bandpass used in AM transmitting. 1.7 FREQUENCY CONVERSION: Frequency conversion is accomplished by using the heterodyne principle of beating two frequencies together to get an intermediate frequency. So far, you have only become familiar with single conversion; however, some receivers use double or triple conversion. These methods are sometimes referred to as double or triple heterodyning. Receivers using double or triple conversion are very selective and suppress IMAGE SIGNALS to yield sharp signal discrimination. (Image signals are undesired, modulated carrier signals that differ by twice the intermediate frequency from the frequency to which the superheterodyne receiver is tuned.) Double and triple conversion receivers

also have better adjacent channel selectivity than can be realized in single conversion sets. In military communications receivers you may sacrifice fidelity to improve selectivity. This is permitted because intelligence (voice, teletypewriter) can be carried on a fairly narrow band of frequencies. Entertainment receivers, on the other hand, must reproduce a wider band of frequencies to achieve their high-fidelity objective. 1.8 SINGLE-SIDEBAND: You know from studying the single-sideband transmitter material in this chapter you may transmit only one sideband of an AM signal and retain the information transmitted. Now you will see how a single-sideband signal is received. 1.8.1 Advantag:

Figure 1.3 Comparison of AM and ssb transmitted signals.

Figure 1.3 illustrates the transmitted signal for both AM and ssb. Ssb communications has several advantages. When you eliminate the carrier and one sideband, all of the transmitted power is concentrated in the other sideband. Also, an ssb signal occupies a smaller portion of the frequency spectrum in comparison to the AM signal. This gives us two advantages, narrower receiver bandpass and the ability to place more signals in a small portion of the frequency spectrum. Ssb communications systems have some drawbacks. The process of producing an ssb signal is somewhat more complicated than simple amplitude modulation, and frequency stability is much more critical in ssb communication. While we don't have the annoyance of heterodyning from adjacent signals, a weak ssb signal is sometimes completely masked or hidden from the receiving station by a stronger signal. Also, a carrier of proper frequency and amplitude must be reinserted at the receiver because of the direct relationship between the carrier and sidebands. Figure 1.4 is a block diagram of a basic ssb receiver. It is not significantly different from a conventional superheterodyne AM receiver. However, a special type of detector and a carrier reinsertion oscillator must be used. The carrier reinsertion oscillator must furnish a carrier to the detector circuit. The carrier must be at a frequency which corresponds almost exactly to the position of the carrier used in producing the original signal. .

Figure 1-4 Basic ssb receiver Rf amplifier sections of ssb receivers serve several purposes. Ssb signals may exist in a small portion of the frequency spectrum; therefore, filters are used to supply

the selectivity necessary to adequately receive only one of them. These filters help you to reject noise and other interference. Ssb receiver oscillators must be extremely stable. In some types of ssb data transmission, a frequency stability of 2 hertz is required. For simple voice communications, a deviation of 50 hertz may be tolerable. These receivers often employ additional circuits that enhance frequency stability, improve image rejection, and provide automatic gain control (agc). However, the circuits contained in this block diagram are in all single-sideband receivers. 1.8.2 Carrier Reinsertion : The need for frequency stability in ssb operations is extremely critical. Even a small deviation from the correct value in local oscillator frequency will cause the IF produced by the mixer to be displaced from its correct value. In AM reception this is not too damaging, since the carrier and sidebands are all present and will all be displaced an equal amount. Therefore, the relative positions of carrier and sidebands will be retained. However, in ssb reception there is no carrier, and only one sideband is present in the incoming signal. The carrier reinsertion oscillator frequency is set to the IF frequency that would have resulted had the carrier been present. For example, assume that a transmitter with a suppressed carrier frequency of 3 megahertz is radiating an upper sideband signal. Also assume that the intelligence consists of a 1-kilohertz tone. The transmitted sideband frequency will be 3,001 kilohertz. If the receiver has a 500-kilohertz IF, the correct local oscillator frequency is 3,500 kilohertz. The output of the mixer to the IF stages will be the difference frequency, 499 kilohertz. Therefore, the carrier reinsertion oscillator frequency will be 500 kilohertz, which will maintain the frequency relationship of the carrier to the sideband at 1 kilohertz. Recall that 1 kilohertz is the modulating signal. If the local oscillator frequency should drift to 3,500.5 kilohertz, the IF output of the mixer will become 499.5 kilohertz. The carrier reinsertion oscillator, however, will still be operating at 500 kilohertz. This

will result in an incorrect audio output of 500 hertz rather than the correct original 1kilohertz tone. Suppose the intelligence transmitted was a complex signal, such as speech. You would then find the signal unintelligible because of the displacement of the side frequencies caused by the local oscillator deviation. The local oscillator and carrier reinsertion oscillator must be extremely stable.


2.1 Objectives: 1.Know the relationship of carrier frequency, modulation frequency and modulation index to efficiency and bandwidth 2.Compare FM systems to AM systems with regard to efficiency, bandwidth and noise. 2.2 Modulation: The information signal can rarely be transmitted as is, it must be processed. In order to use electromagnetic transmission, it must first be converted from audio into an electric signal. The conversion is accomplished by a transducer. After conversion it is used to modulate a carrier signal. A carrier signal is used for two reasons: To reduce the wavelength for efficient transmission and reception (the optimum antenna size is or of a wavelength). A typical audio frequency of 3000 Hz will have a wavelength of 100 km and would need an effective antenna length of 25 km! By comparison, a typical carrier for FM is 100 MHz, with a wavelength of 3 m, and could use an antenna only 80 cm long. To allow simultaneous use of the same channel, called multiplexing. Each unique signal can be assigned a different carrier frequency (like radio stations) and still share the same channel. The phone company actually invented modulation to allow phone conversations to be transmitted over common lines. The process of modulation means to systematically use the information signal (what you want to transmit) to vary some parameter of the carrier signal. The carrier signal is usually just a simple, single-frequency sinusoid (varies in time like a sine wave). The basic sine wave goes like V(t) = Vo sin (2 f t + ) where the parameters are defined below: V(t) -the voltage of the signal as a function of time. Vo - the amplitude of the signal (represents the maximum value achieved each cycle)

f -the frequency of oscillation, the number of cycles per second (also known as Hertz = 1 cycle per second) the phase of the signal, representing the starting point of the cycle. To modulate the signal just means to systematically vary one of the three parameters of the signal: amplitude, frequency or phase. Therefore, the type of modulation may be categorized as either AM: amplitude modulation FM: frequency modulation or PM: phase modulation Note: PM may be an unfamiliar term but is commonly used. The characteristics of PM are very similar to FM and so the terms are often used interchangeably. 2.3 Frequency Modulation: Frequency modulation uses the information signal, Vm(t) to vary the carrier frequency within some small range about its original value. Here are the three signals in mathematical form:

Information: Vm(t) Carrier: Vc(t) = Vco sin ( 2 fc t + ) FM: VFM (t) = Vco sin (2 [ fc + ( f/Vmo) Vm (t) ] t + ) We have replaced the carrier frequency term, with a time-varying frequency. We

have also introduced a new term: f, the peak frequency deviation. In this form, you should be able to see that the carrier frequency term: f c + (f/Vmo) Vm (t) now varies between the extremes of fc - f and fc + f. The interpretation of f becomes clear: it is the farthest away from the original frequency that the FM signal can be. Sometimes it is referred to as the "swing" in the frequency. We can also define a modulation index for FM, analogous to AM:

= f/fm , where fm is the maximum modulating frequency used. The simplest interpretation of the modulation index, , is as a measure of the peak frequency deviation, f. In other words, represents a way to express the peak deviation frequency as a multiple of the maximum modulating frequency, fm, i.e. f = fm. Example: suppose in FM radio that the audio signal to be transmitted ranges from 20 to 15,000 Hz (it does). If the FM system used a maximum modulating index, , of 5.0, then the frequency would "swing" by a maximum of 5 x 15 kHz = 75 kHz above and below the carrier frequency.

Figure 2.1 simple FM signal Here, the carrier is at 30 Hz, and the modulating frequency is 5 Hz. The modulation index is about 3, making the peak frequency deviation about 15 Hz. That means the frequency will vary somewhere between 15 and 45 Hz. How fast the cycle is completed is a function of the modulating frequency. 2.4 FM Spectrum: A spectrum represents the relative amounts of different frequency components in any signal. Its like the display on the graphic-equalizer in your stereo which has leds

showing the relative amounts of bass, midrange and treble. These correspond directly to increasing frequencies (treble being the high frequency components). It is a well-know fact of mathematics, that any function (signal) can be decomposed into purely sinusoidal components (with a few pathological exceptions) . In technical terms, the sines and cosines form a complete set of functions, also known as a basis in the infinitedimensional vector space of real-valued functions (gag reflex). Given that any signal can be thought to be made up of sinusoidal signals, the spectrum then represents the "recipe card" of how to make the signal from sinusoids. Like: 1 part of 50 Hz and 2 parts of 200 Hz. Pure sinusoids have the simplest spectrum of all, just one component:

Figure 2.2 Sinusoidal Signals and its Frequency spectrum In this example, the carrier has 8 Hz and so the spectrum has a single component with value 1.0 at 8 Hz The FM spectrum is considerably more complicated. The spectrum of a simple FM signal looks like:

Figure 2.3 FM signal and its spectrum

The carrier is now 65 Hz, the modulating signal is a pure 5 Hz tone, and the modulation index is 2. What we see are multiple side-bands (spikes at other than the carrier frequency) separated by the modulating frequency, 5 Hz. There are roughly 3 side-bands on either side of the carrier. The shape of the spectrum may be explained using a simple heterodyne argument: when you mix the three frequencies (f c, fm and f) together you get the sum and difference frequencies. The largest combination is f c + fm + f, and the smallest is fc - fm - f. Since f = fm, the frequency varies ( + 1) fm above and below the carrier.

Figure 2.4 More realistic example is to use an audio spectrum In this example, the information signal varies between 1 and 11 Hz. The carrier is at 65 Hz and the modulation index is 2. The individual side-band spikes are replaced by a more-or-less continuous spectrum. However, the extent of the side-bands is limited (approximately) to ( + 1) fm above and below. Here, that would be 33 Hz above and below, making the bandwidth about 66 Hz. We see the side-bands extend from 35 to 90 Hz, so out observed bandwidth is 65 Hz. You may have wondered why we ignored the smooth humps at the extreme ends of the spectrum. The truth is that they are in fact a by-product of frequency modulation (there is no random noise in this example). However, they may be safely ignored because they are have only a minute fraction of the total power. In practice, the random noise would obscure them anyway. 2.5 FM DEMODULATION:

In order to be able to receive FM a receiver must be sensitive to the frequency variations of the incoming signals. As already mentioned these may be wide or narrow band. However the set is made insensitive to the amplitude variations. This is achieved by having a high gain IF amplifier. Here the signals are amplified to such a degree that the amplifier runs into limiting. In this way any amplitude variations are removed. In order to be able to convert the frequency variations into voltage variations, the demodulator must be frequency dependent. The ideal response is a perfectly linear voltage to frequency characteristic. Here it can be seen that the centre frequency is in the middle of the response curve and this is where the un-modulated carrier would be located when the receiver is correctly tuned into the signal. In other words there would be no offset DC voltage present. The ideal response is not achievable because all systems have a finite bandwidth and as a result a response curve known as an "S" curve is obtained. Outside the bandwidth of the system, the response falls, as would be expected. It can be seen that the frequency variations of the signal are converted into voltage variations which can be amplified by an audio amplifier before being passed into headphones, a loudspeaker, or passed into other electronic circuitry for the appropriate processing.

Figure 2.5 Characteristic "S" curve of an FM demodulator

To enable the best detection to take place the signal should be centred about the middle of the curve. If it moves off too far then the characteristic becomes less linear and higher levels of distortion result. Often the linear region is designed to extend well beyond the bandwidth of a signal so that this does not occur. In this way the optimum linearity is achieved. Typically the bandwidth of a circuit for receiving VHF FM broadcasts may be about 1 MHz whereas the signal is only 200 kHz wide. 2.6 FM demodulators: There are a number of circuits that can be used to demodulate FM. Each type has its own advantages and disadvantages, some being used when receivers used discrete components, and others now that ICs are widely used. Below is a list of some of the main types of FM demodulator or FM detector. In view of the widespread use of FM, even with the competition from digital modes that are widely used today, FM demodulators are needed in many new designs of electronics equipment. 1.Slope FM detector 2.Foster-Seeley FM detector 3.Ratio detector 4.PLL, Phase locked loop FM demodulator 5.Quadrature FM demodulator 6.Coincidence FM demodulator Each of these different types of FM detector or demodulator has its own advantages and disadvantages. These FM demodulators are described in further pages of this tutorial. 2.7 FM PLL demodulator: Phase locked loop, PLL FM demodulator or detector is a form of FM demodulator that has gained widespread acceptance in recent years. PLL FM detectors can easily be made from the variety of phase locked loop integrated circuits that are

available, and as a result, PLL FM demodulators are found in many types of radio equipment ranging from broadcast receivers to high performance communications equipment. The PLL FM demodulation integrated circuits started to appear when integrated circuit technology developed to the degree to allow RF analogue circuits to be manufactured. Although high frequencies are not normally needed, for PLL FM demodulators, the circuit must be capable of operating at the intermediate frequency of the receiver, and for receivers using FM this was often 10.7 MHz. Although by today's standards, this is not high, it was necessary for the technology to reach this state before PLL FM demodulators became available. 2.7.1 PLL FM demodulation basics: The way in which a phase locked loop, PLL FM demodulator works is relatively straightforward. It requires no changes to the basic phase locked loop, itself, utilising the basic operation of the loop to provide the required output. The way in which a PLL FM demodulator operates is quite straightforward. The loop consists of a phase detector into which the incoming signal is passed, along with the output from the voltage controlled oscillator (VCO) contained within the phase locked loop. The output from the phase detector is passed into a loop filter and then used as the control voltage for the VCO.

Figure 2.6 PLL FM demodulation block diagram

2.7.2 Phase locked loop (PLL) FM demodulator With no modulation applied and the carrier in the centre position of the passband the voltage on the tune line to the VCO is set to the mid position. However if the carrier deviates in frequency, the loop will try to keep the loop in lock. For this to happen the VCO frequency must follow the incoming signal, and in turn for this to occur the tune line voltage must vary. Monitoring the tune line shows that the variations in voltage correspond to the modulation applied to the signal. By amplifying the variations in voltage on the tune line it is possible to generate the demodulated signal. 2.7.3 PLL FM demodulator performance: The PLL FM demodulator is normally considered a relatively high performance form of FM demodulator or detector. Accordingly they are used in many FM receiver applications. The PLL FM demodulator has a number of key advantages: Linearity: The linearity of the PLL FM demodulator is governed by the voltage to

frequency characteristic of the VCO within the PLL. As the frequency deviation of the incoming signal normally only swings over a small portion of the PLL bandwidth, and the characteristic of the VCO can be made relatively linear, the distortion levels from phase locked loop demodulators are normally very low. Distortion levels are typically a tenth of a percent. Manufacturing costs: The PLL FM demodulator lends itself to integrated circuit

technology. Only a few external components are required, and in some instances it may not be necessary to use an inductor as part of the resonant circuit for the VCO. These facts make the PLL FM demodulator particularly attractive for modern applications. 2.7.4 PLL FM demodulator design considerations:

When designing a PLL system for use as an FM demodulator, one of the key considerations is the loop filter. This must be chosen to be sufficiently wide that it is able to follow the anticipated variations of the frequency modulated signal. Accordingly the loop response time should be short when compared to the anticipated shortest time scale of the variations of the signal being demodulated. A further design consideration is the linearity of the VCO. This should be designed for the voltage to frequency curve to be as linear as possible over the signal range that will be encountered, i.e. the centre frequency plus and minus the maximum deviation anticipated. In general the PLL VCO linearity is not a major problem for average systems, but some attention may be required to ensure the linearity is sufficiently good for hi-fi systems. 2.7.5 Summary: The PLL FM demodulator is one of the more widely used forms of FM demodulator or detector these days. Its suitability for being combined into an integrated circuit, and the small number of external components makes PLL FM demodulation ICs an ideal candidate for many circuits these days. 2.8 Example: FM Radio: FM radio uses frequency modulation, of course. The frequency band for FM radio is about 88 to 108 MHz. The information signal is music and voice which falls in the audio spectrum. The full audio spectrum ranges form 20 to 20,000 Hz, but FM radio limits the upper modulating frequency to 15 kHz (cf. AM radio which limits the upper frequency to 5 kHz). Although, some of the signal may be lost above 15 kHz, most people can't hear it anyway, so there is little loss of fidelity. FM radio maybe appropriately referred to as "high-fidelity." If FM transmitters use a maximum modulation index of about 5.0, so the resulting bandwidth is 180 kHz (roughly 0.2 MHz). The FCC assigns stations ) 0.2 MHz apart to prevent overlapping signals (coincidence? I think not!). If you were to fill

up the FM band with stations, you could get 108 - 88 / .2 = 100 stations, about the same number as AM radio (107). This sounds convincing, but is actually more complicated (agh!). FM radio is broadcast in stereo, meaning two channels of information. In practice, they generate three signals prior to applying the modulation: the L + R (left + right) signal in the range of 50 to 15,000 Hz. a 19 kHz pilot carrier. the L-R signal centered on a 38 kHz pilot carrier (which is suppressed) that ranges from 23 to 53 kHz . So, the information signal actually has a maximum modulating frequency of 53 kHz, requiring a reduction in the modulation index to about 1.0 to keep the total signal bandwidth about 200 kHz. 2.9 FM PERFORMANCE: 2.9.1 Bandwidth: As we have already shown, the bandwidth of a FM signal may be predicted using: BW = 2 ( + 1 ) fm where -is the modulation index and fm -is the maximum modulating frequency used. FM radio has a significantly larger bandwidth than AM radio, but the FM radio band is also larger. The combination keeps the number of available channels about the same. The bandwidth of an FM signal has a more complicated dependency than in the AM case (recall, the bandwidth of AM signals depend only on the maximum modulation frequency). In FM, both the modulation index and the modulating frequency affect the bandwidth. As the information is made stronger, the bandwidth also grows.

2.9.2 Efficiency:
The efficiency of a signal is the power in the side-bands as a fraction of the total. In FM signals, because of the considerable side-bands produced, the efficiency is generally high. Recall that conventional AM is limited to about 33 % efficiency to prevent distortion in the receiver when the modulation index was greater than 1. FM has no analogous problem. The side-band structure is fairly complicated, but it is safe to say that the efficiency is generally improved by making the modulation index larger (as it should be). But if you make the modulation index larger, so make the bandwidth larger (unlike AM) which has its disadvantages. As is typical in engineering, a compromise between efficiency and performance is struck. The modulation index is normally limited to a value between 1 and 5, depending on the application.

2.9.3 Noise:
FM systems are far better at rejecting noise than AM systems. Noise generally is spread uniformly across the spectrum (the so-called white noise, meaning wide spectrum). The amplitude of the noise varies randomly at these frequencies. The change in amplitude can actually modulate the signal and be picked up in the AM system. As a result, AM systems are very sensitive to random noise. An example might be ignition system noise in your car. Special filters need to be installed to keep the interference out of your car radio. FM systems are inherently immune to random noise. In order for the noise to interfere, it would have to modulate the frequency somehow. But the noise is distributed uniformly in frequency and varies mostly in amplitude. As a result, there is virtually no interference picked up in the FM receiver. FM is sometimes called "static free, " referring to its superior immunity to random noise. 2.10 Summary: In FM signals, the efficiency and bandwidth both depend on both the maximum modulating frequency and the modulation index.

Compared to AM, the FM signal has a higher efficiency, a larger bandwidth and better immunity to noise.

Design entities and configurations The design entity is the primary hardware abstraction in VHDL. It represents a portion of a hardware designthat has well-defined inputs and outputs and performs a well-defined function. A design entity may representan entire system, a subsystem, a board, a chip, a macro-cell, a logic gate, or any level of abstraction in between.A configuration can be used to describe how design entities are put together to form a complete design. A design entity may be described in terms of a hierarchy of blocks, each of which represents a portion of the whole design. The top-level block in such a hierarchy is the design entity itself; such a block is an external block that resides in a library and may be used as a component of other designs. Nested blocks in the hierarchy are internal blocks, defined by block statements
3.1Entity declarations:

An entity declaration defines the interface between a given design entity and the environment in which it issued. It may also specify declarations and statements that are part of the design entity. A given entity declaration may be shared by many design entities, each of which has a different architecture. Thus, an entity declaration can potentially represent a class of design entities, each with the same interface. entity_declaration ::= entity identifier is entity_header entity_declarative_part [ begin entity_statement_part ] end [ entity ] [ entity_simple_name ] ;

Generics provide a channel for static information to be communicated to a block from its environment. The following applies to both external blocks defined by design entities and to internal blocks defined by block statements. generic_list ::= generic_interface_list The generics of a block are defined by a generic interface list. Each interface element in such a generic interface list declares a formal generic. 3.1.2 Ports: Ports provide channels for dynamic communication between a block and its environment. port_list ::= port_interface_list

Architecture bodies: An architecture body defines the body of a design entity. It specifies the

relationships between the inputs and outputs of a design entity and may be expressed in terms of structure, dataflow, or behavior. Such specifications may be partial or complete. architecture_body ::= architecture identifier of entity_name is architecture_declarative_part begin architecture_statement_part end [ architecture ] [ architecture_simple_name ] ; 3.3 Subprograms And Packages 3.3.1 Subprogram declarations: A subprogram declaration declares a procedure or a function, as indicated by the appropriate reserved word. subprogram_declaration ::= subprogram_specification ; subprogram_specification ::= procedure designator [ ( formal_parameter_list ) ] | [ pure | impure ] function designator [ ( formal_parameter_list ) ] return type_mark

The specification of a procedure specifies its designator and its formal parameters (if any). The specification of a function specifies its designator, its formal parameters (if any), the subtype of the returned value (the result subtype), and whether or not the function is pure. A function is impure if its specification contains the reserved word impure; otherwise, it is said to be pure. A procedure designator is always an identifier. A function designator is either an identifier or an operator symbol 3.3.2 Subprogram bodies: A subprogram body specifies the execution of a subprogram. subprogram_body ::= subprogram_specification is subprogram_declarative_part begin subprogram_statement_part end [ subprogram_kind ] [ designator ] ; 3.3.3 Package declarations: A package declaration defines the interface to a package. The scope of a declaration within a package can be extended to other design units. package_declaration ::= package identifier is package_declarative_part end [ package ] [ package_simple_name ] ; 3.3.4 Package bodies A package body defines the bodies of subprograms and the values of deferred constants declared in the interface to the package. package_body ::= package body package_simple_name is package_body_declarative_part end [ package body ] [ package_simple_name ] ; 3.4 Data Types: 3.4.1 Scalar Types: Scalar type can be classified into four types.they are -- Enumeration -- Integer -- Physical -- Floating Point Enumeration types:

An enumeration type definition defines an enumeration type. enumeration_type_definition ::= ( enumeration_literal { , enumeration_literal } ) enumeration_literal ::= identifier | character_literal Integer types: An integer type definition defines an integer type whose set of values includes those of the specified range. integer_type_definition ::= range_constraint. Physical types: Values of a physical type represent measurements of some quantity. Any value of a physical type is an integral multiple of the primary unit of measurement for that type. physical_type_definition ::= range_constraint units primary_unit_declaration { secondary_unit_declaration } end units [ physical_type_simple_name ] Floating point types: Floating point types provide approximations to the real numbers. Floating point types are useful for models in which the precise characterization of a floating point calculation is not important or not determined. floating_type_definition ::= range_constraint 3.4.2 Composite types: Composite types are used to define collections of values. These include both arrays of values (collections of values of a homogeneous type) and records of values (collections of values of potentially heterogeneous types). Array types An array object is a composite object consisting of elements that have the same subtype. The name for an element of an array uses one or more index values belonging to specified discrete types. The value of an array object is a composite value consisting of the values of its elements unconstrained_array_definition ::= array ( index_subtype_definition { , index_subtype_definition } )

of element_subtype_indication constrained_array_definition ::= array index_constraint of element_subtype_indication Record types: A record type is a composite type, objects of which consist of named elements. The value of a record object is a composite value consisting of the values of its elements. record_type_definition ::= record element_declaration { element_declaration } end record [ record_type_simple_name ] 3.4.3 Access types: An object declared by an object declaration is created by the elaboration of the object declaration and is denoted by a simple name or by some other form of name. In contrast, objects that are created by the evaluation of allocators (see 7.3.6) have no simple name. Access to such an object is achieved by an access value returned by an allocator; the access value is said to designate the object.
access_type_definition ::= access subtype_indication

3.4.4 File types A file type definition defines a file type. File types are used to define objects representing files in the hostsystem environment. The value of a file object is the sequence of values contained in the host system file. file_type_definition ::= file of type_mark 3.5 Data Objects: 3.5.1 Object declarations An object declaration declares an object of a specified type. Such an object is called an explicitly declared object. Constant declarations A constant declaration declares a constant of the specified type. Such a constant is an explicitly declared constant. constant_declaration ::=

constant identifier_list : subtype_indication [ := expression ] ; If the assignment symbol ":=" followed by an expression is present in a constant declaration, the expression specifies the value of the constant; the type of the expression must be that of the constant. The value of a constant cannot be modified after the declaration is elaborated. Signal declarations A signal declaration declares a signal of the specified type. Such a signal is an explicitly declared signal. signal_declaration ::= signal identifier_list : subtype_indication [ signal_kind ] [ := expression ] ; signal_kind ::= register | bus Variable declarations A variable declaration declares a variable of the specified type. Such a variable is an explicitly declared variable. variable_declaration ::= [ shared ] variable identifier_list : subtype_indication [ := expression ] ; File declarations A file declaration declares a file of the specified type. Such a file is an explicitly declared file. file_declaration ::= file identifier_list : subtype_indication [ file_open_information ] ; 3.6 Operators: 3.6.1.Logical Operators: The logical operators and, or, nand, nor, xor, xnor, and not are defined for predefined types BIT and BOOLEAN. They are also defined for any one-dimensional array type whose element type is BIT or BOOLEAN. For the binary operators and, or, nand, nor, xor, and xnor, the operands must be of the same base type. Moreover, for the binary operators and, or, nand, nor, xor, and xnor defined on one-dimensional array types, the operands must be arrays of the same length, the operation is performed on matching elements of the arrays, and the result is an array with the same index range as the left operand. 3.6.2.Relational Operators.

Relational operators include tests for equality, inequality, and ordering of operands. The operands of each relational operator must be of the same type. The result type of each relational operator is the predefined type BOOLEAN.

Operator Operation = /= < <= > >= Operand Type Equality Any Type Inequality Any Type Less Than Any ScalarType or Descrete type Less Than or Equal Any ScalarType or Descrete type Any ScalarType or GreaterThan Descrete type Greater Than or Any ScalarType or Equal Descrete type Result Type Boolean Boolean Boolean Boolean Boolean Boolean

3.6.3.Shift Operators. The shift operators sll, srl, sla, sra, rol, and ror are defined for any one-dimensional array type whose element type is either of the predefined types BIT or BOOLEAN.
Operator Operation sll srl sla sra rol ror Shift lef Logical Shift right Logical Shift left arithmetic Shift right arithmetic Rotate left Logical Rotate right Logical Left operand type Any one-dimensional array type whose element type is BIT or BOOLEAN Any one-dimensional array type whose element type is BIT or BOOLEAN Any one-dimensional array type whose element type is BIT or BOOLEAN Any one-dimensional array type whose element type is BIT or BOOLEAN Any one-dimensional array type whose element type is BIT or BOOLEAN Any one-dimensional array type whose element type is BIT or BOOLEAN Right operand Type INTEGER INTEGER INTEGER INTEGER Same as left INTEGER Same as left INTEGER sSame as left Result type Same as left Same as left Same as left

3.6.4.Adding Operators.

The adding operators + and are predefined for any numeric type and have their conventional mathematical meaning. The concatenation operator & is predefined for any one-dimensional array type.



Left operand type

Right operand Type

Result Type

+ &

Addition Subtraction

Any numeric type Any numeric type Any array type Any array type The element type The element type

Same type Same type Same type Same type Same array type Same element type Any array type Any element type Same array type Same array type Same array type Any array type


3.6.5. Multiplying Operators: The operators * and / are predefined for any integer and any floating point type and have their conventional mathematical meaning; the operators mod and rem are predefined for any integer type. For each of these operators, the operands and the result are of the same type.
Left operand type Right operand Type Result Type



* / mod rem

Multiplication Division Modulus Remainde

Any integertype Any floating point type Any integer type Any floating point type Any integer type Any integer type

Same type Same type Same type Same type Same type Same type

Same type Same type Same type Same type Same type Same type

3.6.6. Miscellaneous operators: The unary operator abs is predefined for any numeric type.



Operand type

Result type

Absolute value

Any numeric type

Same numeric type

The exponentiating operator ** is predefined for each integer type and for each floating point type. In either case the right operand, called the exponent, is of the predefined type INTEGER.
Operator Operation Left operand type Right operand Type Result Type



Any integer type Any floating point type


Same as left Same as left

In VHDL mainly there are three types modeling styles.These are 1.Behaviorial Modeling. 2. Data Flow Modeling. 3. Structural Modeling. 3.7 Behaviorial Modeling: 3.7 .1 Process statement A process statement defines an independent sequential process representing the behavior of some portion of thedesign. process_statement ::= [ process_label : ] [ postponed ] process [ ( sensitivity_list ) ] [ is ] process_declarative_part begin process_statement_part end [ postponed ] process [ process_label ] ;

where the sensitivity list of the wait statement is that following the reserved word process. Such a process statement must not contain an explicit wait statement. Similarly, if such a process statement is a parent of a procedure, then that procedure may not contain a wait statement.

3.7.2 Sequential statements: The various forms of sequential statements are described in this section. Sequential statements are used to define algorithms for the execution of a subprogram or process; they execute in the order in which they appear. Wait statement The wait statement causes the suspension of a process statement or a procedure. wait_statement ::= [ label : ] wait [ sensitivity_clause ] [ condition_clause ] [ timeout_clause ] ; sensitivity_clause ::= on sensitivity_list sensitivity_list ::= signal_name { , signal_name } condition_clause ::= until condition condition ::= boolean_expression timeout_clause ::= for time_expression Assertion statement: An assertion statement checks that a specified condition is true and reports an error if it is not. assertion_statement ::= [ label : ] assertion ; assertion ::= assert condition [ report expression ] [ severity expression ] Report statement: A report statement displays a message. report_statement ::= [ label : ] report expression [ severity expression ] ; If statement: An if statement selects for execution one or none of the enclosed sequences of statements, depending on the value of one or more corresponding conditions. if_statement ::=

[ if_label : ] if condition then sequence_of_statements { elsif condition then sequence_of_statements } [ else sequence_of_statements ] end if [ if_label ] ; If a label appears at the end of an if statement, it must repeat the if label. For the execution of an if statement, the condition specified after if, and any conditions specified after elsif, are evaluated in succession (treating a final else as elsif TRUE then) until one evaluates to TRUE or all conditions are evaluated and yield FALSE. If one condition evaluates to TRUE, then the corresponding sequence of statements is executed; otherwise, none of the sequences of statements is executed. Case statement: A case statement selects for execution one of a number of alternative sequences of statements; the chosen alternative is defined by the value of an expression. case_statement ::= [ case_label : ] case expression is case_statement_alternative { case_statement_alternative } end case [ case_label ] ; case_statement_alternative ::= when choices => sequence_of_statements The expression must be of a discrete type, or of a one-dimensional array type whose element base type is a character type. This type must be determinable independently of the context in which the expression occurs, but using the fact that the expression must be of a discrete type or a one-dimensional character array type. Each choice in a case statement alternative must be of the same type as the expression; the list of choices specifies for which values of the expression the alternative is chosen. Loop statement: A loop statement includes a sequence of statements that is to be executed repeatedly, zero or more times. loop_statement ::=

[ loop_label : ] [ iteration_scheme ] loop sequence_of_statements end loop [ loop_label ] ; iteration_scheme ::= while condition | for loop_parameter_specification parameter_specification ::= identifier in discrete_range Next statement: A next statement is used to complete the execution of one of the iterations of an enclosing loop statement (called loop in the following text). The completion is conditional if the statement includes a condition. next_statement ::= [ label : ] next [ loop_label ] [ when condition ] ; Exit statement: An exit statement is used to complete the execution of an enclosing loop statement (called loop in the following text). The completion is conditional if the statement includes a condition. exit_statement ::= [ label : ] exit [ loop_label ] [ when condition ] ; Return statement A return statement is used to complete the execution of the innermost enclosing function or procedure body .return_statement ::= [ label : ] return [ expression ] ; Null statement A null statement performs no action. null_statement ::= [ label : ] null ;

3.8 Data Flow Modeling: The various forms of concurrent statements are described in this section. Concurrent statements are used to define interconnected blocks and processes that jointly describe the overall behavior or structure of a design. Concurrent statements execute asynchronously with respect to each other.

3.8.1 Block statement: A block statement defines an internal block representing a portion of a design. Blocks may be hierarchically nested to support design decomposition.

block_statement ::= block_label : block [ ( guard_expression ) ] [ is ] block_header block_declarative_part begin block_statement_part end block [ block_label ] ; If a guard expression appears after the reserved word block, then a signal with the simple name GUARD of predefined type BOOLEAN is implicitly declared at the beginning of the declarative part of the block, and the guard expression defines the value of that signal at any given time (see 12.6.4). The type of the guard expression must be type BOOLEAN. Signal GUARD may be used to control the operation of certain statements within the block (see 9.5). 3.8.2 Concurrent procedure call statements: A concurrent procedure call statement represents a process containing the corresponding sequential procedure call statement. concurrent_procedure_call_statement ::= [ label : ] [ postponed ] procedure_call ; For any concurrent procedure call statement, there is an equivalent process statement. The equivalent process statement is a postponed process if and only if the concurrent procedure call statement includes the reserved word postponed.

Concurrent assertion statements: A concurrent assertion statement represents a passive process statement concurrent_assertion_statement ::= [ label : ] [ postponed ] assertion ;

containing the specified assertion statement.

3.8.4 Concurrent signal assignment statements

A concurrent signal assignment statement represents an equivalent process statement that assigns values to signals. concurrent_signal_assignment_statement ::= [ label : ] [ postponed ] conditional_signal_assignment | [ label : ] [ postponed ] selected_signal_assignment

3.8.5 Conditional signal assignments: The conditional signal assignment represents a process statement in which the signal transform is an if statement. target <= options waveform1 when condition1 else waveform2 when condition2 else waveform3 when condition3 else ---------------------------waveformN-1 when condition-1 else waveformN when conditionN; 3.8.6 Selected signal assignments: The selected signal assignment represents a process statement in which the signal transform is a case statement. with expression select target <= options waveform1 when choice_list1 , waveform2 when choice_list2 , waveform3 when choice_list3, ---------------------------waveformN-1 when choice_listN-1, waveformN when choice_listN ; 3.9 .Structural Modeling: 3.9.1 Component declarations: A component declaration declares a virtual design entity interface that may be used in a component instantiation statement. A component configuration or a configuration specification can be used to associate a component instance with a design entity that resides in a library. component_declaration ::= component identifier [ is ] [ local_generic_clause ]

[ local_port_clause ] end component [ component_simple_name ] ; Each interface object in the local generic clause declares a local generic. Each interface object in the local port clause declares a local port.If a simple name appears at the end of a component declaration, it must repeat the identifier of the component declaration. 3.9.2 Component instantiation statements: A component instantiation statement defines a subcomponent of the design entity in which it appears, associates signals or values with the ports of that subcomponent, and associates values with generics of that subcomponent. This subcomponent is one instance of a class of components defined by a corresponding component declaration, design entity, or configuration declaration. component_instantiation_statement ::= instantiation_label : instantiated_unit [ generic_map_aspect ] [ port_map_aspect ] ; instantiated_unit ::= [ component ] component_name | entity entity_name [ ( architecture_identifier ) ] | configuration configuration_name


The design of the All Digital FM Receiver circuit in this project uses Phase Locked Loop (PLL) as the main core. The task of the PLL is to maintain coherence between the input (modulated) signal frequency,iand the respective output frequency,ovia phase comparison. This self-correcting ability of the system also allows the PLL to track the frequency changes of the input signal once it is locked. Frequency modulated input signal is assumed as a series of numerical values (digital signal) via 8-bit of analog to digital conversion (ADC) circuit. The FM Receiver gets the 8 bit signal every clock cycle and outputs the demodulated signal. The All Digital FM Receiver circuit is designed using VHDL, then simulated and synthesized using ModelSim SE 6 simulator and Xilinx ISE 6.3i, respectively. FPGA implementation also provided, here we use Virtex2 device. The real measurement is done using ChipScope Pro 6.3i 4.1. Architecture Description:
The system of All Digital FM Receiver consists of a digital PLL cascaded with digital low pass filter. The block diagram of system is shown in Fig. 1.

Figure 4.1 Digital FM receiver architecture

4.1.2 Phase Detector :

Phase Detector (PD) detects phase error between input signal and output signal from NCO. This operation employs a multiplier module. The input signal is frequency modulated, so the input signal Vi(n) can be expressed as follows,

Feedback loop mechanism of the PLL will force NCO to generate sinusoidal signal with the same frequency of , then

Output of phase detector is product of these two signals, using familiar trigonometric identity we obtain

Kd is the gain of the phase detector. The first term in (3) corresponds to high frequency component. The second term corresponds to the phase difference between Vi(n) and Vo(n). By removing the first term thru loop filtering, the phase difference can be obtained. The block diagram of phase detector is a multiplier shown in Fig. 2.

Figure 4.2 Internal diagram of Phase detector

Summary of operation: input1 is fmin (modulated data), input2 is NCOs output. Both input are 2s complement in <8,0,t> format, please see [8] for details. unit delay is used to synchronize operation, then inputs values are multiplied, where input1 as multiplicand and input2 as multiplier, product will be 16 bit in <16,0,t> format, then we scale it by cropping the 8 most bits and feed it to the output in <8,0,t> format. In the VHDL model, we use Booths Multiplication algorithm instead of simple signed arithmetic multiplier operation (denoted by ). Arithmetic multiplier will consume large area, while Booths multiplication algorithm for 8bit multiplication only needs eight 8-bit adders which is much save in area consumption. For this algorithm, as shown in Fig. 3, the individual partial products determined from the multiplicand may be: added to, subtracted to, or may not change the final product at all based on the following rules: the multiplicand is subtracted from the partial product upon encountering the first 1 in a string of 1s in the multiplier, the multiplicand is added to the partial product upon encountering the first 0 provided that there was no previous 1 in a string of 0s in the multiplier,

the partial product does not change when the bit is identical to the previous multiplier bit.

Fig. 4.3 Paper and pencil illustration of Booths algorithm

4.1.2 Loop Filter:

Loop filter will remove the high frequency component in (3). Fig. 4 shows the block diagram of a first order loop filter used in the receiver system. In the VHDL model of this block, we need to treat a sign extension from <8,0,t> to <12,4,t> and a multiplication by constant of 15/16. Summary of operation: input C is multipliers output in <8,0,t> format. Output is D1 <12,4,t>. D1 will be
multiplied by 15/16 and then the product is summed back to C dtemp <12,4,t> is internal signal which is the summing result of C and D1. C must be changed to <12,4,t> before summation, hence,

dtemp will be assigned to D1. Then dtemp x 15/16 = dtemp x (1 1/16) = dtemp (dtemp x 1/16) = dtemp - E E =dtemp x 1/16, in reality 1/16 multiply can be implemented by just 4 bit right shift operation. Then no multiplier is required.
dtemp <12,4,t> dtemp(11 downto 0) E <12,4,t> = dtemp x 1/16 dtemp(11)&dtemp(11)&dtemp(11)&dtemp (11)&dtemp(11 downto 4)

Fig. 4.4 Block diagram of first order loop filter

First order loop filter as shown in Fig. 4 is a low pass filter with the transfer function

Which has a pole on the real axis at z = 0.9375. From stability property of discrete time filter, we know that H(z) is stable since its pole is located within the unit circle

4.1.3. Numerical Controlled Oscillator:

Numerical Controlled Oscillator (NCO) will take the corrective error voltage, and then shift its output frequency from its free-running value to the input signal frequency ()dVniand thus keep the PLL in lock. The block diagram can be seen in Fig. 5 as follows,

Fig.4 5 Block diagram of NCO Here we assume the NCO free running frequency is 1 MHz and the system clock frequency is 16 MHz; there are 16 sampling points in one cycle of 1 MHz free running frequency. When input is zero, NCO has to generate output equal to free running frequency. Since there are 16 sampling points in one cycle of free running frequency, so the offset must be 1/16. The greater input will produce greater frequency, and vice versa.

Fig. 4.6 Data values in one cycle of cosine ROM

The system is a simple integrator which accumulates the input value and maps it into predefined cosine ROM. All 1024 values were given ( file: cos.txt) to define one cycle of cosine signal, but we actually dont need to use all of these values. Since one cycle can be divided to four quarter, we only need to define the first quarter with 257 values. The remains quarters are duplicated form the first quarter, where the opposite sign is applied to second and third quarter. Illustration is shown in Fig 6. Summary of operation: input D2 and offset are added, note that signed extension form <12,-6,t> to <18,0,u>. the addition result then accumulated by modulo accumulator, then we take 10 most bits as ROM address. Address will be mapped to data values in ROM.

4.1.4. FIR Filter :

The last stage of the receiver system is to perform signal shaping. Here we use 16 tap Finite Impulse Response (FIR) filter to perform digital low pass filter. This filter is essentially average filter since its output is equal to the average value of its input over the last n-tap samples, where n is number of tap used [4]. This configuration needs 16 coefficients, but simplification is taken by assuming all of the coefficients are the same, 1/16. In reality 1/16 multiply can be implemented by just 4 bit right shift operation. Then no multiplier is required.

Fig. 4.7 Block diagram of FIR filter

4.2. Functional Explanation:

Digital PLL system is composed of three basic parts: (1) Phase Detector (PD), (2) Loop filter, (3) Numerical-controlled oscillator (NCO). The complete block diagram of the All Digital FM receiver circuit is shown in Fig. 8. With no signal input applied to the system. The NCO control voltage Vd(n) is equal to zero. The NCO operates at a set frequency, fo(or the equivalent radian frequency, o) which is known as the free running frequency. When an input signal is applied to the system, the phase detector compares the phase and the frequency of the input with the NCO frequency and generates an error voltage Ve(o) that is related to the phase and the frequency difference between the two signals. This error voltage is then filtered, amplified by factor of A = 1/1024, and applied to the control terminal of the NCO. In this manner, the control voltageVd(n) forces the NCO frequency to vary in a direction that reduces the frequency difference

Fig. 4.8 Complete block diagram of All Digital FM Receiver system

between o and the input signal. If the input frequency i is sufficiently close to o,the feed back nature of the PLL causes the NCO to synchronize or lock with the incoming signal. Once in lock, the NCO frequency is identical to the input signal except for a finite phase difference.

This net phase difference of e where

is necessary to generate the corrective error voltage Vd(n) to shift the NCO frequency from its free-running value to the input signal frequency i and thus keep the PLL in lock. This self-correcting ability of the system also allows the PLL to track the frequency changes of the input signal once it is locked,hence it can be act as a FM demodulator in receiver system. Another means of describing the operation of the PLL is to observe that the phase detector is in actuality a multiplier circuit that mixes the input signal with the NCO signal. This mix produces the sum and difference frequencies shown

in (3). When the loop is in lock, the NCO duplicates the input frequency so that the difference frequency component is zero, hence, the output of the phase

comparator contains only a DC component. The loop filter removes the sum frequency component back to the NCO. The single most important point to realize when designing with the PLL is that it is a feedback system and, hence, is characterized mathematically by the same equations that apply to other, more conventional feedback control systems [5]. Mathematical model of the all digital PLL system can be derived to analyze the transient and steady state response. The block diagram of the all digital PLL system in z domain (discrete time) and its transformation in s domain (continuous time) is shown in Fig. 9. but passes the DC component which is then amplified and fed

Fig. 4.9 Block diagram of PLL system in analyzing transient response Since a physical control system involves energy storage, the output of the system, when subjected to an input, cannot follow the input immediately but exhibits a transient response before a steady state can be reached [3]. The transfer function of the system is

Hence, the PLL system is a second order system. In the test for stability we subjected the system with test signal representing a unit step of frequency at constant phase, this test signal correspond with actual input signal which is a FM modulated signal [5]. Using MATLAB, we can plot unit step response curve for the system as shown in Fig. 10. We see that the system is stable with overshoots at the transient state.

Fig. 4.10 Unit step response for PLL system used in FM receiver system

4.3 General Implementation Flow:

The generalized implementation flow diagram of the project is represented as follows in the figure 4.11Initially the market research should be carried out which covers the previous version of the design and the current requirements on the design. Based on this survey, the specification and the architecture must be identified. Then the RTL modeling should be carried out in Verilog HDL with respect to the identified architecture. Once the RTL modeling is done, it should be simulated and verified for all the cases. The functional verification should meet the intended architecture and should pass all the test cases. Once the functional verification is clear, the RTL model will be taken to the synthesis process. Three operations will be carried out in the synthesis process such as Translate Map Place and Route

Figure 4.11 General Implementation Flow Diagram The developed RTL model will be translated to the mathematical equation format which will be in the understandable format of the tool. These translated equations will be then mapped to the library that is, mapped to the hardware. Once the mapping is done, the gates were placed and routed. Before these processes, the constraints can be given in order to optimize the design. Finally the BIT MAP file will be generated that has the design information in the binary format which will be dumped in the FPGA board.

4.4 Summary:
The implementation requirement which includes the primary input and primary output of the design and the proper notation and conventions were discussed. General implementation flow of the design were represented and explained in order to understand the proper flow. Implementation details have been discussed which includes implementation style of each process.


5.1 Simulation Results: 5.1.Phase Detector: Simulated results of Phase Detector shown in figure.It consists of two

inputs,one of the input is frequency modulated input(input1) and other one is output of Numerical Controle Oscillator.FM input1 is a sequence of samples that can be obtained from the sampling and quantization of continuos signal. Phase Detector gives output as a combination of summing frequency and

difference frequency,this output can be applied for the loop filter.

Frequency modulated input

Phase Detector NCO Output Output Figure 5.1 Phase detector simulation result input1 is fmin (modulated data), input2 is NCOs output. Both input are 2s complement in <8,0,t> format, please see [8] for details. unit delay is used to synchronize operation, then inputs values are multiplied, where input1 as multiplicand and input2 as multiplier,

5.2.Loop Filter:

Output of the phase detecror as a input for the loop filter

Summing frequency Figure 5.2 Loopfilter simulation result

Difference frequency

difference frequency .Here Loop Filter is a first order lowpass filter.When ever Cis given to Loop Filter then it separate the summing and difference frequencies,eliminates the summing frequency .Difference frequency can be applied to the NCO as a input. 5.3.Numerical Controle Oscillator: Simulated results of Numerical Controle Oscillator (NCO) can be shown in the following figure.It takes the input from the Loop Filter which is a difference voltage

Output of loop filter as a input to the NCO

Output of NCO .It can applied as a input to phase detector

Figure 5.3 simulation result of NCO

and changes its output frequency according to the this difference voltage so that frequency modulated frequency is equal to the output of NCO. 5.4.FIR Filter: Output of the loop filter as a input to FIR filter.

Demodulated output Figure 5.4 Simulation results of FIR filter Simulated results of the FIR Filter is shown in figure.It takes the input from the loop filter and producing the demodulated output 5.5.Top level Model: Finally,top level design of Digital FM Reciever can be simulated and verified.It takes the frequency modulated input and gives the output as a demodulated output.

Frequency modulated input

demodulated output

Figure 5.5 simulation result of Digital FM reciever

5.2 Introduction to FPGA:

FPGA stands for Field Programmable Gate Array which has the array of logic module, I /O module and routing tracks (programmable interconnect). FPGA can be configured by end user to implement specific circuitry. Speed is up to 100 MHz but at present speed is in GHz. Main applications are DSP, FPGA based computers, logic emulation, ASIC and ASSP. FPGA can be programmed mainly on SRAM (Static Random Access Memory). It is Volatile and main advantage of using SRAM programming technology is reconfigurability. Issues in FPGA technology are complexity of logic element, clock support, IO support and interconnections (Routing). In this work, design of an ATM Controller is made using Verilog HDL is synthesized on FPGA family through XILINX ISE Tool. This process includes following: Translate Map Place and Route 3.3.1 FPGA Flow The basic implementation of design on FPGA has the following steps. Design Entry Logic Optimization Technology Mapping Placement Routing Programming Unit Configured FPGA Above shows the basic steps involved in implementation. The initial design entry of may be Verilog HDL, schematic or Boolean expression. The optimization of the Boolean expression will be carried out by considering area or speed.

Figure 5.6 Logic Block In technology mapping, the transformation of optimized Boolean expression to FPGA logic blocks, that is said to be as Slices. Here area and delay optimization will be taken place. During placement the algorithms are used to place each block in FPGA array. Assigning the FPGA wire segments, which are programmable, to establish connections among FPGA blocks through routing. The configuration of final chip is made in programming unit.

5.3 Synthesis Results:

The developed Digital FM Reciever design is simulated and verified their functionality. Once the functional verification is done, the RTL model is taken to the synthesis process using the Xilinx ISE tool. In synthesis process, the RTL model will be converted to the gate level netlist mapped to a specific technology library. This Digital FM Reciever Controller design can be synthesized on the family of Spartan 3E. Here in this Spartan 3E family, many different devices were available in the Xilinx ISE tool. In order to synthesis this design the device named as XC3S500E has been chosen and the package as FG320 with the device speed such as -4. The design of Digital FM Reciever is synthesized and its results were analyzed as follows.

5.4.Device utilization summary: Table 5.1:Digital FM Reciever status:

Table 5.2: Device utilization summary:

Table 5.3:Performance summary:

Table 5.4:Detailed report:

This device utilization includes the following. Logic Utilization Logic Distribution Total Gate count for the Design The device utilization summery is shown above in which its gives the details of number of devices used from the available devices and also represented in %. Hence as the result of the synthesis process, the device utilization in the used device and package is shown above. 5.5Timing Summary:

Speed Grade: -6 Minimum period: 17.820ns (Maximum Frequency: 56.117MHz). Minimum input arrival time before clock: 1.329ns. Maximum output required time after clock: 4.575ns. Maximum combinational path delay: No path found.
In timing summery, details regarding time period and frequency is shown are approximate while synthesize. After place and routing is over, we get the exact timing summery. Hence the maximum operating frequency of this synthesized design is given

as 56.117MHz and the minimum period as 1.329ns. Here, OFFSET IN is the minimum input arrival time before clock and OFFSET OUT is maximum output required time after clock. 5.6.RTL Schematic:

Figure 5.7 RTL Schematic view of Digital FM reciever

Figure 5.8 Internal architecture of RTL schematic view Digital FM reciever

The developed Digital FM Reciever Controller design is modelled and is simulated using the Modelsim tool. The simulation results are discussed by considering different cases. The RTL model is synthesized using the Xilinx tool in vertex-2 and their synthesis results were discussed with the help of generated reports.

In this chapter, the design of a Digital FM Reciever is made using VHDL and is verified by using MODEL SIM Tool. In this simulation we compilile the whole low level designs along with top level design.After compiliation,the whole design was simulated,in simulation we checked the functionality for all possible conditions.Finally,the whole design is verified by using ModelSim tool.This tool helps us to identify whether the design working properly or not. After compiliation completed successfully,the whole design taken for the synthesis using Xi Linx ISE 10.1.In the process of synthesis ,first I am choosen the FPGA device as Spartan 3E family,device is XC3S500E ,package is FG320.By using this Spartan 3E family,I faced some problems,thats why I changed the FPGA as
Virtex2 device from XiLinx with XC2V2000 technology and FF896 package.For this there no problems are raised.Finally,synthesis completed,Inthis synthesis I analyzed time analysis with I am getting Minimum period: 17.820ns (Maximum Frequency:


[1] Modeling PLL, in Integrated Circuits Application Note AN178 Philips Semiconductors, 1988. [2] Douglas J. Smith, HDL Chip Design, Doone Publication, 1996 [3] John G. Proakis, Dimitri G. Manolakis, Digital Signal Processing, Prentice Hall, 1996. [4] Katsuhiko Ogata, Modern Control Engineering, Prentice Hall, 2002. [5] Naresh K. Sinha, Linear Systems, John Wiley and Sons. Inc, 1991. [6] P.E. Allen, All Digital Phase Locked Loop, " in Lecture Note CMOS Phase Locked Loops, 2003. [7] Roland E. Best, Phase Locked Loop, Theory, Design, and Applications, McGraw Hill, 2003.

Future Scope:
In this design of Digital FM Reciever,whole design is simulated and synthesized.This design can be extended to future projects 1.This design can be implemented using FPGA device. 2.We can increase size of the frequency modulated signal for the future projects. 3.This project can be useful for the communication based projects because of its simple architecture and less noise