R.M.K.

COLLEGE OF ENGINEERING AND TECHNOLOGY R S M Nagar,Puduvoyal 601 206

LECTURE PLAN 2013-14 ( III Semester / II Year) Individual Time Table
Name of the Faculty Department Subject Code & Name Year / Semester Branch : Ms. VIJAYAKUMARI.D : ECE : EC2203 / DIGITAL ELECTRONICS : II/III SEC D :ECE Tuesday Wednesday Thursday Friday Saturday DE DE DE DE Days Period I II III IV V VI VII DE

Tentative dates for Unit tests and Model Exam Unit Test I Unit Test II Model Exam : 31.07.13 to 7.8.13 : 30.08.13 to 7.9.13 : 17.10.13 to 26.10.13

Sl. No
1.

Duration
From To

Planned Lecture Date

3.7.13

Topics to be covered
Introduction-Number system-Number base conversions Boolean algebra Boolean postulates and Theorem- Boolean expression

Teaching Aids to be used

Lecture Date

Remarks by the faculty

Steps taken to cover the incomplete portions, if any & Signature of the Staff Member

Signature of Principal

2.

4.7.13

3.

6.7.13 (2)

Minimization of Boolean expressionminterms -maxterms- SOP- POSKmap-2V,3V,4V- without dont care conditions Kmap-with dont care conditions Tabulation Method Practice problems- Gate implementation NAND-NOR implementation Signature of HOD TTL & CMOS logic-Tristate gates Date: Black Board

4.

9.7.13

UNIT I
3.7.13 5. 6. 7. 8. 9. 18.7.13 10.7.13 11.7.13 13.7.13 (2) 16.7.13 17.7.13 18.7.13

Prepared By: Approved By:

RMKCET/COM/F/15

Sl. No
1. 2.

Duration
From To

Planned Lecture Date

20.7.13 (2) 23.7.13

Topics to be covered
Combinational circuit- design procedure Half adder-Full adder-Half sub tractor- Full sub tractor

Teaching Aids to be used

Lecture Date

Remarks by the faculty

Steps taken to cover the incomplete portions, if any & Signature of the Staff Member

Signature of Principal

3. 4. 5. 6. 7. 8. 9.

24.7.13 25.7.13

Parallel Binary adder/subtractor Fast adder-carry lookahead adder BCD adder-Binary multiplier-binary divider Multiplexer and Demultiplexr Decoder and encoder Priority encoder- Parity generators Code converters- Magnitude Comparator (2 bit & 4 bit) Signature of HOD Date: Black Board

UNIT II
20.7.13 6.8.13

27.7.13 (2) 30.7.13 31.7.13 1.8.13 2.8.13 6.8.13

Prepared By: Approved By:

RMKCET/COM/F/15

Sl. No
1. 2.

Duration
From To

Planned Lecture Date

7.8.13 8.8.13

Topics to be covered
Sequential ckts- Flipflops Latches Realization of one flip flop using other- serial adder/subtractor

Teaching Aids to be used

Lecture Date

Remarks by the faculty

Steps taken to cover the incomplete portions, if any & Signature of the Staff Member

Signature of Principal

3.

10.8.13 (2)

4. 5. 6. 7. 8. 9.

UNIT III
7.8.13 22.8.13

13.8.13 14.8.13 17.8.13 (2) 20.8.13 21.8.13 22.8.13

Asynchronous ripple counter- asynchronous up/down counter- synchronous up/down counter Programmable counters- design of counters Design of modulo-n counter Shift registers-types- universal shift registers Shift register counters Ring counter- shift counter Sequence generator

Black Board

Signature of HOD Prepared By: Approved By:

Date:

RMKCET/COM/F/15

Sl. No
1.

Duration
From To

Planned Lecture Date

24.8.13(2)

Topics to be covered
Classification of memories- RAM-ROM organisation PROM EPROM EEPROM Memory cycle -Memory decoding Memory expansion Static RAM cell Bipolar RAM cell MOSFET RAM cell- Dynamic RAM cell PLD- PLA-PAL-FPGA Implementation of combinational ckt using ROM,PROM,PLA,PAL-Problems

Teaching Aids to be used

Lecture Date

Remarks by the faculty

Steps taken to cover the incomplete portions, if any & Signature of the Staff Member

Signature of Principal

2. 3. 4. 5. 6. 7. 8. 9.

27.8.13 28.8.13 29.8.13

UNIT IV
24.8.13 11.9.13

31.8.13 3.9.13 4.9.13 7.9.13 10.9.13 11.9.13

Black Board

Signature of HOD

Date:

Prepared By: Approved By:

RMKCET/COM/F/15

Sl. No
1.

Duration
From To

Planned Lecture Date

12.9.13

Topics to be covered
Synchronous sequential ckts- General modelclassification

Teaching Aids to be used

Lecture Date

Remarks by the faculty

Steps taken to cover the incomplete portions, if any & Signature of the Staff Member

Signature of Principal

2.

14.9.13(2)

Design procedure of synchronous sequential ckts- problems

3. 4. 5. 6. 7. 8. 9.

17.9.13

ASM chart Problems Analysis Procedure of synchronous sequential ckts Analysis problems Design of fundamental mode and pulse mode ckts Analysis of asynchronous ckts problems Design of Hazard free switching ckts Design of combinational and sequential ckts using Verilog. Signature of HOD Date: Black Board

UNIT V
12.9.13 28.9.13

18.9.13 19.9.13 21.9.13(2) 24.9.13 25.9.13 26.9.13 28.9.13(2)

Prepared By: Approved By:

RMKCET/COM/F/15