Shailendra Kumar Rajput

Shailendrarajput89@gmail.com

:+917411348596

PROFESSIONAL EXPERIENCE
1.8 years of experience in frontend VLSI domain as Design Verification engineer at Sasken Communication Technologies Ltd., India.

TECHNICAL EXPERIENCE
Assembly Language Hardware Design Language Hardware Verification Language Verification Methodology Scripting Languages Operating Systems Responsibilities Areas of Interest : ARM and 8086 ALP. : VHDL and Verilog. : System Verilog, Specman-e. : UVM, eRM. : Perl. : Linux. : ARM SOC verification, TB/Testcase development and debugging and fixing, Functional and Code coverage analysis. : ARM architecture, System Verilog, UVM, Verilog.

EXPERIENCE SUMMARY
Having 1.8 years of experience as Design Verification engineer with 1 year of relevant experience at ARM Embedded Technologies. Effective involvement in SOC level verification of ARM v7 and v8 processors. Strong understanding in ARM architecture. Real time exposure of Testcase writing in ARM assembly language programming. Good debugging skills at assembly level. Knowledge in Tb building, test scenario generation, debugging and coverage. Good hands on experience in Verilog, System Verilog and UVM methodologies. Sound knowledge in C and C++ programming.

PROJECT DETAILS
1. ARM V7 SOC Verification Performed SOC level verification for ARM V7 Processor. Responsibilities: My role was to get effectively involved in debugging the tests cases written for various test scenarios. Updating the Perl scripts for running regressions.

Responding to customer queries through mails and phone as well. Efficient involvement in the final AVK Kit release including documentation of the kit.

Tools: VCS tool OS: ARM validation tools. ARM assembly tools. Subversion(SVN) Unix

Languages: ARM assembly PERL scripting

Project Description: Following points were aimed at in this project ARM V7 to be used in simple microcontroller devices. Provide highest performance at low power. Involve TrustZone and Jazellex features. Provide MMU for OS and multitasking Achieve Deterministic and predictable behavior.

2. ARM V8 SOC Verification This is project developing AVS suites for the v8 Architecture. AVS suites checks adherence to an architecture definition so that a. ARM cores of same architecture version are software compatible with each other. b. Cores from Architecture licensees are s/w compatible with all other cores (ARM and others) of the same Architecture version.

3. Verification of AHB to AXI Bridge using UVM

The main function of this bridge is to convert read/write transactions of AHB protocol into read/write transactions of AXI protocol. Bridge can be used in multi-master/multi-slave configuration with different frequencies at both sides. Duration: 4 months Language: System Verilog Methodology: UVM

Responsibilities Test plan, Assertion plan and Coverage plan creation. Coding of AXI slave UVC. Coding of Testcases and analysis of coverage reports. Coding of AXI monitor, checker and transaction class.

4. Module level Verification of Image Stat using eRM Image Stat is a statistics generator for review by the software to determine if the image is usable for further image processing. Responsibilities: My role was to develop 3 modules namely BFM, OUTPUT RECEIVER and PROTOCOL CHECKER. BFM passes the fields from sequence driver to the DUT.OUTPUT RECEIVER receives response from DUT, thus aids protocol and data checking. PROTOCOL CHECKER checks for the validation of the OCP protocol. Tools: Cadence composer Simvision Specman Subversion(SVN) OS: Unix Languages: Specman e 5. GDMA(GENERAL DIRECT MEMORY ACCESS) Reference model development

The General DMA works based on the concept of channel. Data transfer happens between in two phases 1. from Source to DMA. 2. from DMA to Destination Responsibilities: My task was to develop two modules namely CHANNEL SCHEDULER and CONTEXT MANAGER. CHANNEL SCHEDULER block is responsible for scheduling which channel is to be serviced next. A channel is granted access to read/write port by the arbitration logic. CONTEXT MANAGER block is responsible for updating next running byte address and number of elements remaining for transfer. Tools: Cadence composer Simvision Specman Subversion(SVN)

EDUCATIONAL QUALIFICATION
Education B.E. (Electronics & Communication Engineering) Class 12 Class 10 College/University Cambridge Institute of Technology, Bangalore / VTU K.V ASC Center (South), Bangalore / CBSE K.V ASC Center (South), Bangalore / CBSE Year 2011 2007 2005 78 83 Percentage 85

GENERAL SKILLS & ACHEIVEMENTS

Team-Player with good communication skill. Topper of the college for 2nd, 3rd& 4th years of B.E. Awarded with gold medal for academic excellence for the year 2008-2009. Awarded with gold medal for academic excellence for the year 2009-2010.

Self-motivated, Adaptable, Responsible and punctual. Quick learner and goal oriented. Good Mentoring capability.

PERSONAL PROFILE
Name Nationality Date of Birth Languages : Shailendra Kumar Rajput : Indian : August 22nd, 1990 : English, Hindi.

DECLARATION
I do hereby declare that the information given above is true and correct to best of my knowledge. I also bear the responsibility for accuracy of above-mentioned particulars.

Shailendra Kumar Rajput