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concentrated in one location Different types and sizes of memories Memories doubly embedded inside embedded cores Test access to these memories from only a few chip I/O pins
Built-in self-test (BIST) is considered the best solution for testing embedded memories within SOCs
It offers a simple and low-cost means without
Test Generator
Response Verification
Test Controller
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NOR/NAND
Decoder
(ROM Array)
Buffer Outputs
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Counter
RO M
MISR
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Test Controller
Test C ollar
RA M
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RAM BIST
In general, two BIST approaches have been proposed for the RAMs
FSM-based RAM BIST ROM-based RAM BIST
Controller
Generate control signals to the test pattern
Comparator
microprogram ROM A wide range of test capabilities due to ROM programming flexibility
End
Microprogram
ROM
Test Collar
TPG
RA M
Go/No-Go Comparator
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Normal I/Os
End
FSM
Test Collar
TPG
RA M
Go/No-Go Comparator
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W0
S
2
S3
S S
S
W1 End
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S4
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Collar
Comp ar
CLK BNS
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Shift_cmd
BSC=0
Get_cmd
Apply
DONE=0
ENA=1
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Serial BIST
Todays telecommunication ICs often have a variety if multiport memories on one chip Typical RAM BISTs evaluate all the bits of a memory word in parallel as it is read We can encounter significant problems when applying these BIST schemes to chips that have multiple embedded RAMs of varying sizes and port configurations
The area cost of these BIST designs would be
unacceptably high
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Only a small amount of additional circuitry is required Only a few lines are needed to connect the RAM to the test controller Several RAM blocks easily share the BIST controller hardware The serial-access mode does not compromise the RAM cycle time
Existing memory designs do not need any modification to use the serial interface
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Serial-Data-Path Connection
dRow
Ci
ecoder Column decoder
Latch
C i+1
Latch
I
Ii Oi
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O
i+1 i+1
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in
content
out
0 1 101 00 00 00 2 3 4 010 1 X
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X R0 W1 R0 W1 R0 W1 R0 W1 X 1 1 1 1 1 1 1
0 0 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 1
0 0 0 0 0 0 1 1 1
0 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
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00
0 0 X
5 6 7 8
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Assume that a RAM has W words, and each word contains C bits A Read operation is denoted by R0, R1, or Rx, depending on the expected value at the serial output (x=dot care) For a write operation, the terms W0 or W1 are used and only the serial input is forced to the value indicated The SMarch modified from March C- is as C C C C follcows(RxW 0) ( R0,W 0) ; ( R0,W 1) ( R1,W 1)
( R1,W 0) ( R0,W 0) ; ( R0,W 1) ( R1,W 1)
C C C C C C C C
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Counters
Control Data out Data in Address Multiplexer
Timing
SO
lsb
SI
msb
generator
C-1
Multiplexer
C C
Multiplexer
Address
Data in
Data out
Control
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Counters
Controller SO SI
Timing generator
Address
R d/Write
GO
Done
DeMux
SO Counters
Address
SI
Timing generator
Controller
SO
SO
n m wire n
n m wire
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Processor
Test Collar
TPG
RA M
Go/No-Go Comparator
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ADD R
DATA O
DATAO_bist Mux_sel
Embedded CPU
Clock_cpu
BIST core
On-chip bus
Embedded Memory
Ctrl_cpu
Ctrl_bist
control
DATAI_cpu
DATAI_bist
DATAI_sys
DATAI
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BIST core
DATAO_cpu DATAO_bist
R
B G
R
A
Lowest/highest addr
Address
counter
ADDR_bist
ADDR_cpu
Address
R
EA
decorder
AH
Up/down
Read/Write Control
R
M E
R
FLA G
R
I R
R
ED
Controller
Data background
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Data registers
Register
R BG R AL R AH R ME R IR R FLAG R
R
ED
EA
Function Store background data Store lowest address Store highest address Store current March element Instruction register of BIST circuit Status register of BIST circuit Erroneous response of defective cell Address of defective cell
Source: Prof. C. W. Wu, NTHU
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Test program write March instructions to RME Test program write START to RIR
(Wa)
(Ra,Wa) (Ra,Wa)
(Ra,Wa) (Ra,Wa)
(Ra)
yes
Write ERROR to RFLAG Write error response to RED Write faulty addr to REA
No No
March element complete
SOC Testing
Flash Memory
Source
TAM
MPEG
SRAM
SRAM
DRAM
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Off-chip Source/Sink
1. Pins determine bandwidth 2. More TAM area 3. Requires expensive ATE
CPU
UDL TAM
Source MPEG
SRAM SRAM
ADC
FPGA
Wrapper
On-chip Source/Sink
CPU
Flash Memory
UDL
DSP
Sink
1. Close to Core-under-test 2. Less TAM area 3. BIST IP area 4. Requires lightweight ATE
Source
MPEG
Sink
Source
SRA M SRAM
DRAM
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Core1
CoreN
Fout
WSI
WIR
WIR
WSO
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Test stimuli
WPI
WBR
Functional data
Functional data
WBY
WSI WIR
WSO
WSC
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Memories in SOCs
ADC FPGA Flash Memory CPU
UDL DSP
DRAM
SRAM
SRAM BIST
SRAM
BIST
MPEG
SRAM BIST
SRAM
DRAM
BIST
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Memory cores in an SOC can be categorized into two types in term of testability
BIST-ready memory cores Non-BIST memory cores
controlling pins The total BIST controlling pins is huge if each BIST-ready memory cores has its own BIST controlling pins
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SRAM
SRAM BIST
MBI
SRAM
BIST
MBI MBI
MBI
BIST SRAM
MPEG
BIST SRAM
DRAM
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Instruction Register
Store the instructions
RUN_BIST, RUN_DIAGN, EXPORT_STATUS, TAM_CONTROL
Bypass Register
It is selected if the corresponding memory core is not tested
Monitor Register
Monitor the error flag (indicating whether a memory fault is
detected or not)
Status Register
Record the key status values, such as Fail output from the
BIST
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be high after N-K clock cycles if the concurrent output of the (K+1) through the N memory cores are fault free
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BIST Controller
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1500-Compilant BIST
T ConAP troller
Wra
TA
P
BIST
RAM
pper
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TAP controller
TAM
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Control Unit
Test Program
Memory Adapter
Address Bus
Data Bus
Control Signals
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Control Unit
Manage the test program execution Include an Instruction Register (IR) and
Program Counter (PC) The control unit allows the correct update of some registers located in Memory Adapter This part simplifies the processor reuse in different applications without the need for any re-design
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Memory Adapter
Control Address registers (Current_address) Control Memory registers
Current_data Received_data
Result registers
Status, Error, and Result registers
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Meaning
Current_address Add_Max Direction flag BACKWARD Current_address Add_Min Direction flag FORWARD Current_data DataBackGround[Dbg_index] Dbg_index Dbg_index+1 Current_data NOT (Current_data) Current_data Memory[Current_address] Memory[Current_address] Current_data
Source: Appello D., et. al. ITC03
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W I R W B Y
W D R
W C D R Processor
TAP controller
W B R
M e mo ry
SelectWIR
Test Program
CORE
WSO
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Summary
ROM BIST has been presented ROM-based and FSM-based RAM BIST have been introduced Serial BIST methodology for embedded memories has also presented BIST approaches for testing multiple RAMs in an SOC have also been addressed
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