Chapter 01

The PIC18 Microcontroller
Chapter 1: Introduction to PIC18 The PIC18 Microcontroller Han-Way Huang Minnesota State University University, Mankato
Copyright @ 2005 Thomson Delmar Learning
H. Huang Transparency No.1-1
What is a computer? Software Hardware Computer Hardware Organization

P ro c e sso r C o m m o n B us ( addr e s s , data, & c o ntr o l) C o ntr o l U nit
D atapath
Ar ithm e tic L o gic U nit
M e m o ry P r o gr am D ata Sto r age Sto r age O utput U nits Input U nits
R e gis te r s
Figur e 1 .1 C o m pute r O r ganizatio n
The processor Th
Registers -- storage locations in the processor Arithmetic logic unit Control unit program p g counter contains the address of the next instruction to be executed status register flags the instruction execution result
The microprocessor
A processor implemented on a very large scale integration (VLSI) chip Peripheral chips are needed to construct a product
The Microcontroller
The processor and peripheral functions implemented on one VLSI chip
Features of the PIC18 microcontroller

8-bit CPU 2 MB program memory space 256 bytes to 1KB of data EEPROM Up to 3968 bytes of on-chip SRAM 4 KB to 128KB flash program memory Sophisticated timer functions that include: input capture, output compare, PWM, real-time interrupt, and watchdog timer Serial communication interfaces: SCI, SCI SPI, SPI I2C, I2C and CAN Background debug mode (BDM) M Memory protection t ti capability bilit Instruction pipelining Operates at up to 40 MHz crystal oscillator
- 10-bit A/D converter
Embedded Systems - A product that uses one or more microcontrollers as controller (s). - End users are only interested in the functionality of the product but not on the microcontroller itself. - Cell phones, home security system, automobiles, and many other products are examples of embedded products.
Semiconductor memory y Random-access memory (RAM): same amount of time is required to access any location on the same chip R d l memory (ROM): Read-only (ROM) can only l b be read db but t not t written itt t to b by th the processor
Random-access memory Dynamic random-access memory (DRAM): need periodic refresh Static random-access memory (SRAM): no periodic refresh is required
Read-only memory Mask programmed read-only Mask-programmed read only memory (MROM): programmed when being manufactured Programmable read-only memory (PROM): can be programmed by the end user
Erasable programmable ROM (EPROM) 1. electrically programmable many times 2. erased by ultraviolet light (through a window) 3 erasable 3. bl in i bulk b lk (whole ( h l chip hi in i one erasure operation) ti ) Electrically erasable programmable ROM (EEPROM) 1. electrically programmable many times 2. electrically erasable many times 3. can be erased one location, one row, or whole chip in one operation Flash memory 1. electrically programmable many times 2. electrically erasable many times 3. can only be erased in bulk (either a block or the whole chip)
Computer software Computer programs are known as software A program is a sequence of instructions
Machine instruction A sequence of binary digits which can be executed by the processor Hard d to understand, d d program, and d debug d b for f human h being b i
Assembly language Defined by assembly instructions An assembly instruction is a mnemonic representation of a machine instruction A Assembly bl programs must t be b translated t l t d before b f it can be b executed t d -translated by an assembler Programmers need to work on the program logic at a very low level and cant achieve high g p productivity. y
High-level language
Syntax of a high-level language is similar to English A translator is required to translate the program written in a high-level language -- done by a compiler Allows the user to work on the program logic at higher level.
Source code
A program written in assembly or high-level language
Object code
The output of an assembler or compiler
Source code and object code examples

address object j code line no. Source code ---------------------------------------------------------------------------------------------00001E 0E06 00010 movlw 0x06 000020 6E11 00011 movwf 0x11,A , 000022 0E07 00012 movlw 0x07 000024 6E12 00013 movwf 0x12,A 000026 0000 6 0E08 0 08 00014 000 movlw ov w 0x08 0 08 000028 6E13 00015 movwf 0x13,A 00002A 0E05 00016 movlw 0x05 00002C 5E10 00017 subwf 0x10,F,A 00002E 5E11 00018 subwf x11,F,A
Radix Specification p - Hexadecimal (or hex) number is specified by adding the prefix 0x or by enclosing the number with single quotes and preceding it by an H. - 0x02, 0x1234, H H`2040 2040 are hex numbers - Decimal numbers are enclosed by single quotes and preceded by letter D. - D`10 and D`123 are decimal numbers - Octal and binary numbers are similarly specified. - O`234 is an octal number; B01011100 is a binary number.
Memory Addressing Memory consists of a sequence of directly addressable locations. Al location i is i referred f d to as an information i f i unit i. A memory location can be used to store data, instruction, and the status of peripheral devices. A memory y location has two components: p an address and its contents.
Address
Contents
Figure 1.2 The components of a memory location
The PIC18 Memory Organization Data Memory and Program Memory are separated Separation of data memory and program memory makes possible the simultaneous access of data and instruction. Data memory are used as general-purpose registers or special function registers On-chip p Data EEPROM are p provided in some PIC18 MCUs
Separation of Data Memory and Program Memory

Inside the c chip
Program Memory Space (a portion of this space is on th c the chip)
21-bit progam address
12-bit register address
Data Memory Space

(Special function registers and general l purpose RAM)
PIC18 CPU
16-bit instruction bus 8-bit data bus
Figure 1.3 The PIC18 memory spaces
PIC18 Data Memory

- Implemented in SRAM and consists of general-purpose registers and
special-function registers. Both are referred to as data registers. - A PIC18 C 8 MCU CU may ay have ave up to 4096 096 bytes o of data memory. e o y. - Data memory is divided into banks. Each bank has 256 bytes. - General-purpose registers are used to hold dynamic data. - Special-function registers are used to control the operation of peripheral functions. - Only one bank is active at any time. The active bank is specified by the BSR register. register - Bank switching is an overhead and can be error-prone - PIC18 implements the access bank to reduce the problem caused by bank switching. - Access bank consists of the lowest 96 bytes and the highest 160 bytes of the data memory space.

BSR<3:0> = 0000 Access RAM Bank 0 GPRs GPRs
1FFh 200h 000h 05Fh 060h 0FFh 100h
= 0001
Bank 1
= 0010
Bank 2
GPRs
2FFh 300h Access Bank A Access RAM l low 3FFh 400h Access RAM high SFRs 000h 05Fh 060h 0FFh
= 0011
Bank 3
GPRs
Bank 4 to B k 13 Bank = 1110
GPRs
DFFh E00h
Bank 14
GPRs Unused
EFFh F00h F5Fh F60h FFFh
= 1111
Bank 15 SFRs
Note. 1. BSR is the 4-bit bank select register. Figure 1.4 Data memory map for PIC18 devices (redraw with permission of Microchip)
Program Memory Organization - The program counter (PC) is 21-bit long, which enables the user program to access up to 2 MB of program memory. - The PIC18 has a 31-entry return address stack to hold the return address for subroutine call. - After power-on, the PIC18 starts to execute instructions from address 0. - The location at address 0x08 is reserved for high-priority interrupt service routine. - The location at address 0x18 is reserved for low low-priority priority interrupt service routine. - Up to 128KB (at present time) of program memory is inside the MCU chip. - Part P t of f the th program memory is i located l t d outside t id of f the th MCU chip. hi

P C < 2 0 :0 > 21
s ta c k le v e l 1 . . . s ta c k le v e l 3 1 R e s e t V e c to r H ig h P r io r ity I n te r r u p t V e c to r 000000 h 000008h
L o w P r io r ity I n te r r u p t V e c t o r
000018h User Memory y Space
O n - c h ip a n d e x te r n a l p ro gra m m e m o ry
y x x xx x h
U n im p le m e n t e d p ro gra m m e m o ry R e a d '0 '
1FFFFFh N o te . y c a n b e 0 o r 1 w h e re a s x c a n b e 0 -F F ig u r e 1 . 5 P I C 1 8 P r o gr a m m e m o r y O r g a n iz a tio n ( r e d r a w w ith p e r m is s io n o f M ic r o c h ip )
The PIC18 CPU Register - The group of registers from 0xFD8 to 0xFFF are dedicated to the general control of MCU operation. - The h CPU registers i are listed li d in i Table bl 1.2. - The WREG register is involved in the execution of many instructions. - The STATUS register holds the status flags for the instruction execution and is shown in Figure 1.6.
Table 1.2 PIC T C18 CPU reg isters address N am e Description n
0xFFF 0xFFE 0xFFD 0xFFC 0xFFB 0xFFA 0xFF9 0xFF8 0xFF7 0xFF6 0xFF5 0xFF4 0xFF3 0xFF2 0xFF1 0xFF0 0xFEF 0xFEE 0xFED 0xFEC 0xFEB 0xFEA 0xFE9 0xFE8 0xFE7 0xFE6 0xFE5 0xFE4 0xFE3 0xFE2 0xFE1 0xFE0 0xFDF 0xFDE 0xFDD 0xFDC 0xFDB 0xFDA 0xFD9 0xFD8
TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL IN TCON INTCON 2 INTCON 3 IN DF0 (1) 1) POSTINC0 (1 ( POSTDEC0 1) PREINC0 (1)) PLUSW 0 (1) FSR0H FSR0L W REG IN DF1 (1) 1) POSTINC1 (1 ( POSTDEC1 1) PREINC1 (1)) PLUSW 1 (1) FSR1H FSR1L BSR IN DF2 (1) 1) POSTINC2 (1 (1) ( POSRDEC2 PREINC2 (1)) PLUSW 2 (1) FSR2H FSR2L STATUS
Top of sta ack (upper) Top of sta ack (high) Top of sta ack (low ) Stack poi nter rogram counte er latch Upper pr High pro gram counter latch byte Program counter low b Table poi inter upper by yte Table poi inter high byte e Table poi inter low byte Table latc ch High pro duct register duct register Low prod Interrupt control regist ter ter 2 Interrupt control regist ter 3 Interrupt control regist ointer 0 Indirect f ile register po em ent pointer 0 (to GPRs) Post incre Post decr em ent pointer r 0 (to GPRs) Preincrem m ent pointer 0 (to GPRs) Add W RE EG to FSR0 File select t register 0 hi gh byte File select t register 0 low w byte W orking register Indirect f ile register po ointer 1 Post incre em ent pointer 1 (to GPRs) Post decr em ent pointer r 1 (to GPRs) m ent pointer 1 (to GPRs) Preincrem Add W RE EG to FSR1 File select t register 1 hi gh byte File select t register 1 low w byte Bank sele ect register Indirect f ile register po ointer 2 em ent pointer 2 (to GPRs) Post incre Post decr em ent pointer r 2 (to GPRs) m ent pointer 2 (to GPRs) Preincrem Add W RE EG to FSR2 File select t register 2 hi gh byte File select t register 2 low w byte Status reg goster
N ote 1. This is not a phys sical regiser
7 6 --N OV Z DC 5 --
0 C

tive bit N: Negat 1 = ari ithmetic result is negative 0 = ari ithmetic result is positive OV: Ove erflow bit 1 = Ov verflow occurred d for signed arithm metic 0 = No o overflow occur rred Z: Zero f flag 1 = Th he result of an ari ithmetic or logic o operation is zero. 0 = Th he result of an ari ithmetic or logic o operation is not z zero. DC: Digi it carry/borrow bi it For AD DDWF, ADDLW W, SUBLW, SUB BWF instructions. . 1 = A carry-out from th he 4th low-order bit of the result o occurred. 0 = No o carry-out from the 4th low-order r bit of the result occurred. For bo orrow, the polarit ty is reversed. For rotate (RRF, RL LF) instruc ctions, this bit is loaded with eithe er the bit 4 or bit 3 of the source e register. C: Carry/ /borrow bit For AD DDWF, ADDLW W, SUBLW, SUB BWF instructions. . 1 = A carry-out from th he most significan nt bit of the resul lt occurred. o carry-out from the most significant bit of the resu ult has 0 = No oc ccurred. For bo orrow, the polarit ty is reversed. For rotate (RRF, RL LF) instruc ctions, this bit is loaded with eithe er the high or low w order bit of the source register. he STATUS register (0xFD8) (red draw with permis ssion of Microchi ip) Figure 1.6 Th
The PIC18 Pipelining p g

- The PIC18 Divide most of the instruction execution into two stages: instruction fetch and instruction execution. - Up to two instructions are overlapped in their execution. execution One instruction is in fetch stage while the second instruction is in execution stage. - Because of pipelining, each instruction appears to take one instruction cycle to complete. complete
TCY0 MOVLW 55h MOVWF PORTB BRA sub_1 BSF PORTA,BIT3 Instruction @address sub_1 Note: All instructions are single cycle, except for any program branches. Figure 1.7 An example of instruction pipeline flow
Copyright @ 2005 Thomson Delmar Learning H. Huang Transparency No.1-22
TCY1 execute 1 fetch 2
TCY2
TCY3
TCY4
TCY5
fetch 1
execute 2 fetch 3 execute 3 fetch 4 flush fetch sub_1 execute sub_1
Instruction Format
- Format for byte oriented instructions
15 opcode 10 9 d 8 a 7 f 0
d = 0 for result destination to be WREG register. d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Figure 1.8 Byte-oriented file register operations (redraw with permission of Microchip)
Byte-to-byte Operations
15 opcode 15 1111 12 11 f (destination file register) 12 11 f (source file register) 0 0
f = 12-bit file register address Figure 1.9 Byte to byte move operations (2 words) (redraw with permission of Microchip)
Bit-oriented file register operations

15 opcode 12 11 b 9 8 a 7 f 0
b = 3-bit position of bit in the file register (f). a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Figure 1.10 1 10 Bit-oriented Bit oriented file register operations (redraw with permission of Microchip)
Copyright @ 2005 Thomson Delmar Learning H. Huang Transparency No.1-24
Literal operations - A literal is a number to be operated on directly by the CPU

15 opcode k = 8-bit immediate value Figure 1.11 Literal operations (redraw with permission of Microchip) 8 7 k 0
Control operations - These instructions are used to change the program execution sequence and making subroutine calls.
15 opcode 15 1111 n = 20-bit immediate value 15 opcode 15 1111 S = fast bit 15 opcode 15 opcode 11 10
7 n<7:0> (literal)
7 n<19:8> (literal)
GOTO label
8 S 8
7 n<7:0> (literal) 7 n<19:8> (literal)
CALL funct_name
0 n<10:0> (literal) 8 7 n<7:0> (literal) 0 BC label BRA label
Figure 1.12 Control operations (redraw with permission of Microchip)
Access Bank - In Figures 1.8 to 1.12, PIC18 uses 8 bits to specify a data register (f field). - Eight bits can specify only 256 registers. - This limitation forces the PIC18 to divide data registers (up to 4096 bytes) into banks. y one bank is active at a time. - Only - When operating on a data register in a different bank, bank switching is needed. - Bank switching incurs overhead and may cause program errors. errors - Access bank is created to minimize the problems of bank switching. - Access bank consists of the lowest 96 bytes in general-purpose registers and the highest 160 bytes of special function registers. - When operands are in the access bank, no bank switching is needed.
Examples of the Use of Access Bank 1. addwf 0x20,F,A ; add the data register at 0x20 in access bank with WREG ; register and store the sum in 0x20. 2 subwf 0x30,F,BANKED 2. 0x30 F BANKED ; subtract the value of WREG from the data register ; 0x30 in the bank specified by the current contents ; of the BSR register. The difference is stored in ; data register 0x30. 3. addwf 3 dd f 0x40,W,A 0 40 W A ; add dd the h WREG register i with i h data d register i at 0x40 0 40 in i ; access bank and leaves the sum in WREG.
PIC18 Addressing Modes - Register direct: Use an 8-bit value to specify a data register. movwf 0x20,A ; the value 0x20 is register direct mode
- Immediate Mode : A value in the instruction to be used as an operand
addlw 0x10 movlw 0x30
; add hex value 0x10 to WREG ; load 0x30 into WREG
- Inherent Mode: an implied operand andlw 0x3C daw ; the operand WREG is implied ; the operand WREG is implied
- Indirect Mode: A special function register (FSRx) is used as a pointer to the actual data register. Format INDFx POSTINCx POSTDECx PREINCx PLUSWx x = 0, 0 1, 1 2 Example movwf movff movf addwf movff INDF0 POSTINC0,PRODL POSTDEC0,W PREINC1,F PLUSW2,PRODL
PIC18 Instruction Examples p Data Movement Instruction lfsr movf movff FSR1,0xB00 PRODL,W 0x100,0x300 ; place the value 0xB00 in FSR1 ; copy PRODL into WREG ; copy data register 0x100 to data register 0x300 ; copy WREG to PRODL ; swap the upper and lower 4 bits of PRODL ; load 3 into BSR ; WREG 0x10
movwf PRODL,A swapf movb PRODL,F 3
movlw 0x10
Add Instructions addwf addwfc dd f 0x20,F,A PRODL W A PRODL,W,A ; add data register and WREG and place sum in WREG ; add dd WREG, WREG PRODL, PRODL and d carry and dl leave sum ; in WREG ; increment WREG by y5
addlw
0x5
Subtract Instructions subfwb subwf subwfb sublw PRODL F PRODL,F PRODH,W 0x10,F,A 0x10 ; PRODL [WREG] [PRODL] borrow flag ; WREG [PRODH] [WREG] ; 0x10 [0x10] [WREG] borrow flag ; WREG 0x10 [WREG]
RISC Simple instruction set R l and Regular d fixed fi d instruction i t ti format f t Simple address modes Pipelined instruction execution Separated data and program memory Most operations are register to register Take shorter time to design and debug Provide large number of CPU registers
CISC Complex instruction set Irregular instruction format Complex address modes May also pipeline instruction execution Combined data and program memory Most operations can be register to memory Take longer time to design and debug Provide smaller number of CPU registers

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The PIC18 Microcontroller

Copyright @ 2005 Thomson Delmar Learning

H. Huang Transparency No.1-1

The PIC18 Microcontroller

What is a computer? Software Hardware Computer Hardware Organization

Ar ithm e tic L o gic U nit

M e m o ry P r o gr am D ata Sto r age Sto r age O utput U nits Input U nits

Figur e 1 .1 C o m pute r O r ganizatio n

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The PIC18 Microcontroller

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H. Huang Transparency No.1-3

The PIC18 Microcontroller

Features of the PIC18 microcontroller

- 10-bit A/D converter

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H. Huang Transparency No.1-4

The PIC18 Microcontroller

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H. Huang Transparency No.1-5

The PIC18 Microcontroller

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The PIC18 Microcontroller

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The PIC18 Microcontroller

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The PIC18 Microcontroller

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The PIC18 Microcontroller

Source code and object code examples

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The PIC18 Microcontroller

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The PIC18 Microcontroller

Figure 1.2 The components of a memory location

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The PIC18 Microcontroller

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The PIC18 Microcontroller

Separation of Data Memory and Program Memory

Program Memory Space (a portion of this space is on th c the chip)

21-bit progam address

12-bit register address

Data Memory Space

Figure 1.3 The PIC18 memory spaces

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The PIC18 Microcontroller

PIC18 Data Memory

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The PIC18 Microcontroller

Bank 4 to B k 13 Bank = 1110

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