5.

CMOS Inverter

Institute of Microelectronic Systems

Overview

Logic levels Noise Margin CMOS Inverter static behaviour dynamic behaviour

Courtesy Quiller Electronics Limited

Institute of Microelectronic Systems

5: CMOS Inverter

Inverter as simplest logic gate

V+ V + v R v
O O

vI

VO

V DD R i vI M
S

VCC R v
O

i vI

v
C

VI

5: CMOS Inverter

Institute of Microelectronic Systems

Logic Voltage Levels

VOL: Nominal voltage v corresponding to a low logic O state at the output of a logic V + gate for vI = VOH. V Slope = -1 OH Generally V- VOL. VOH: Nominal voltage corresponding to a high logic state at the output of a logic gate for vI = VOL. Generally VOH V+. Slope = -1 VIL: Maximum input voltage that will be recognised as a low V OL input logic level. NM NML H VIH: Minimum input voltage that will 0 V V V V be recognised as a high input V- 0 OL IL IH OH logic level.
Institute of Microelectronic Systems

v V +

5: CMOS Inverter

Noise Margins
V+ vO "1" vI

NML: Noise margin associated with a low input level NML = VIL - VOL NMH: Noise margin associated with a high input level NMH = VOH - VIH

V OH NMH VIH Undefined Logic State V IL NM L VOL "0" V-

"1"

"0"

5: CMOS Inverter

Institute of Microelectronic Systems

Dynamic Response of Logic Gates

v
I

Rise time tr: time required for the transition from V10% to V90%. Fall time tf: time required for the transition from V90% to V10%.
V10% = VOL + 0.1(VOH - VOL) V90% = VOL + 0.9(VOH - VOL)

VOH

90% 50% V
OH

+V 2

OL

VOL
(a)

10% tr vO tf t

Propagation delay P: difference in time between the input and output signals reaching V50%.
V50% = (VOH + VOL)/2

VOH

PHL

PLH
V
OH

90% +V 50%
OL

VOL
(b)

10% t 1 t t2 f t3 t t4 t r

P =
5: CMOS Inverter

PLH + PHL
2

Switching waveforms for an idealised inverter (a) Input voltage signal (b) Output voltage waveform
Institute of Microelectronic Systems

MOS Inverter with Resistive Load

DD

=5V

NMOS switching device MS designed to force vO to VOL Resistor load R to pull the output up toward the power supply VDD VOH = VDD (driver in cut off iD = 0) VOL determined by W/L ratio of MS
v
I

R v i
D O

+
M
S

DS

5: CMOS Inverter

Institute of Microelectronic Systems

Example
V = 5V
DD

V DD = 5V
DD

R v =V
O OH

R =5V

95 k

v =V 0 M v =V <V
I OL

50 A M
S

OL

+
S

TH

v =V
I

OH

=5V

2.06 1 (b)

DS

= 0.25 V

(a)

5: CMOS Inverter

Institute of Microelectronic Systems

On - Resistance
V
DD

DD

R VOH v = V OL
I

R VOL v =V
I OH

R on (a) (b)

R on

Ron =

vDS = iD

1 K 'n W L v vGS VTN DS 2

VOL = VDD

Ron 1 = VDD R Ron + R 1+ Ron

5: CMOS Inverter

Institute of Microelectronic Systems

Transistor Alternatives to the Load Resistor

VDD ML vO vI MS vI MS VDD

ML vO

(a) NMOS inverter with gate of the load device connected to its source

(b) NMOS inverter with gate of the load device grounded

V DD ML vO vI MS VI

VGG

V DD ML vO MS

(c) Saturated load inverter

(d) Linear load inverter

Institute of Microelectronic Systems

5: CMOS Inverter

10

CMOS Inverter Technology

V
SS

(0 V) S n+

V D n+ vo D p+ n-well S p+

DD

(5 V) B n+

B p+ Ohmic contact

NMOS transistor PMOS transistor p-type substrate Ohmic contact

C M O S T ra n sisto r P a ra m e te rs N M O S D e vice VTO 2 F K' 1 V 0 .5 0 25

V

P M O S D e vice -1 V 0 .7 5
V

0 .6 0 V A /V 2
Institute of Microelectronic Systems

0 .7 0 V 1 0 A /V 2

5: CMOS Inverter

11

Complementary MOS (CMOS) Logic Design

Inverter with resistive load power dissipation when the input is high. If an NMOS and PMOS transistor is v I used CMOS. One transistor is always off while the other is on no static power consumption.

VDD = 5 V M

VDD = 5 V R onp

G D D G M S

v v
O

R onn

5: CMOS Inverter

Institute of Microelectronic Systems

12

CMOS voltage transfer Characteristic

1
4.0V VIL

M N off M N saturated M P linear v o = v I - VTP M and M P saturated

vo
2.0V

3 M P saturated M N linear v o= v I - VTN

VIH

5 M P off

0V 0V 1.0V

4
2.0V v I 3.0V

4.0V

5.0V

5: CMOS Inverter

Institute of Microelectronic Systems

13

Regions of Operation of Transistors in a Symmetrical Inverter

Region Input Voltage vI Output Voltage vO VOH = VDD High NMOS Transistor PMOS Transistor

vI VTN VTN < vI vO + VTP vI VDD/2 vO + VTN < vI (VDD + VTP) vI (VDD + VTP)

Cutoff

Linear

Saturation

Linear

VDD/2

Saturation

Saturation

Low VOL = 0

Linear Linear

Saturation Cutoff

5: CMOS Inverter

Institute of Microelectronic Systems

14

What happens, if the inverter is not symmetrical?

6.0V 6.0V

V DD = 5 V
4.0V

V DD = 4 V V DD = 3 V v O= vI

vO= vI
4.0V

KR= 5 K R= 1 K R = 0.2

2.0V

V DD = 2 V

2.0V

0V 0V 1.0V 2.0V 3.0V 4.0V 5.0V 6.0V

0V 0V 1.0V 2.0V 3.0V 4.0V 5.0V

vI

vI

Symmetrical inverter (Kn = Kp)

Asymmetrical inverter (KR = Kn / Kp)

5: CMOS Inverter

Institute of Microelectronic Systems

15

Calculation of VIL
Equating currents for saturated nMOS and nonsaturated pMOS device (Region 2):

K Kn (Vin VTn )2 = p 2(VDD Vin VTp )(VDD Vout ) (VDD Vout )2 2 2

The derivation condition (dVout / dVin) = -1 has to be evaluated for IDn(Vin) = IDp(Vin , Vout):

dVout (dI Dn / dVin ) (I Dp / Vin ) = = 1 dVin I Dp / Vout

Evaluating the derivation gives:

Kn = 2Vout + K n VTn VDD VTp 1 + VIL K Kp p

This equation has to be solved together with the first equation VIL
5: CMOS Inverter Institute of Microelectronic Systems 16

Calculation of VIH
At the point VIH the NMOS device is nonsaturated and the PMOS transistor is saturated (region 4):

K 2 Kn 2 [ ] = p (VDD VIH VTp ) 2(VIH VTn )Vout Vout 2 2

The derivation condition (dVout / dVin) = -1 has to be evaluated for IDn(Vin, Vout) = IDp(Vin):

dVout (dI Dp / dVin ) (I Dn / Vin ) = = 1 I Dn / Vout dVin

which gives:

Kp Kp (VDD VTp ) 1 + 2 VIH = V + V + out Tn K K n n

This equation forms together with the first equation a quadratic in VIH which has to be solved. Institute of
5: CMOS Inverter Microelectronic Systems 17

Calculation of Vth

For Vth = Vin = Vout both transistors are saturated ( is assumed to be 0):
4.0V Kp 2 Kn 2 (Vth VTn ) = (VDD Vth VTp ) 2 2 vo

V IL

Vin=Vout

Solving for Vth yields:

Vth =

VTn + K p / K n (VDD VTp ) 1+ K p / Kn

2.0V

M N and M P saturated

VIH 0V 0V 1.0V 2.0V

4
3.0V

5
4.0V 5.0V

vI
Vth
Institute of Microelectronic Systems

5: CMOS Inverter

18

Design of CMOS inverter (I)

NMH = VOH - VIH = VDD - VIH NML = VIL - VOL = VIL - 0 = VIL KR = Kp / Kn
W Remember: K n = K 'n L n
4.0 Noise Margin (Volts) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1 2 3 4 5 6 KR 7 8
NM L

NM

W K p = K'p L p

Influence of the symmetry via W/L of transistors!

9 10 11

5: CMOS Inverter

Institute of Microelectronic Systems

19

Design of CMOS inverter (II)

The ratio (W/L) in CMOS design is used to set the level of Vth. The ratio required to establish a given inverter threshold voltage is: To get a symmetrical voltage transfer curve, Vth is set to VDD/2: If in a process |VTp| = VTn, the device aspect ratios for a symmetrical inverter are related by:

Kp Kn

p (W L ) p n (W L )n

K n VDD Vth VTp = Kp Vth VTn

Kn 1 2 VDD VTp = 1 K p 2 VDD VTn

(W L ) p n = (W L )n p

Since n / p 2.5, a minimum area CMOS inverter will have (W/L)n 1 and (W/L)p 2.5. In this case the voltage transfer function is completely symmetric.
Institute of Microelectronic Systems

5: CMOS Inverter

20

Summary

V IL 4.0V

So what did we accomplish until now? We know how a CMOS inverter works. VOL, VOH - do you still know it? We know how to set the W/L ratios of the transistors to get optimal noise margins. So we make every inverter the same, that is to say minimal -or?

vo
2.0V

3
VIH

0V 0V 1.0V 2.0V

4
3.0V

5
4.0V 5.0V

vI

5: CMOS Inverter

Institute of Microelectronic Systems

21

Dynamic Behavior of the CMOS Inverter High to Low Output Transition (I)
MN goes from Cutoff over Saturation into Nonsaturation region for the given input. The border between Saturation and Nonsaturation is reached at the time tx and the output voltage Vout = VOH - VTn v
I V DD = 5 V MP v I = 5V v O (0+) = 5V + 5V

0V 0 v VOH = 5V (Vin - VTn) VOL = 0 V

t
O

MN

MN saturated MN nonsaturated t

t1
Institute of Microelectronic Systems

tX

t2

5: CMOS Inverter

22

High to Low Output Transition (II)

In order to simplify the final expressions, the integrations on the right for computing tHL are done with the borders from VDD to V0 (V1 = 0,9 VDD, V0 = 0,1 VDD) Saturation:
t x t1 = COUT
VDD VTn

i=

dV dQ = COUT OUT dt dt dV dt = COUT iOUT

VDD

dVOUT Kn (VDD VTn )2 2

2CoutVTn 2 K n (VDD VTn )

Nonsaturation:
t 2 t x = COUT
V0

Kn 2 2(VDD VTn )VOUT VOUT 2 2(VDD VTn ) COUT ln = 1 K n (VDD VTn ) V0

VDD VTn

dVOUT

2C VOUT 1 ln = OUT K n 2(VDD VTn ) 2(VDD VTh ) VOUT

= VDD VTn

V0

5: CMOS Inverter

Institute of Microelectronic Systems

23

High to Low Output Transition (III)

We have used the following integral:

dx 1 xn x a + bx n = an ln a + bx n

In our case:

n = 1, b = 1

ax x

dx

1 x ln a ax

t HL = (t x t1 ) + (t 2 t x )
therefore:

2VTn 2(VDD VTn ) t HL = + ln 1 V V V 0 DD Tn

=
COUT K n (VDD VTn )

where

5: CMOS Inverter

Institute of Microelectronic Systems

24

Low to high output transition

From symmetry (VTn VTp; Kn Kp) follows for the high to low transition time: 2 VTp 2 VDD VTp COUT t LH = + ln 1 V0 K p VDD VTp VDD VTp

DD

=5V + 5V MP

V =0V
I

0V v M
N O

t 0 v
O

(0+) = 0V C + 5V

0V 0
Institute of Microelectronic Systems

5: CMOS Inverter

25

Dynamic Behavior of the CMOS Inverter (contd)

The choice of size of the NMOS and PMOS transistors can be dictated by the desired average propagation delay P For symmetrical inverter:

P =

t PHL + t PLH = t PHL = t PLH 2

' ' Kn 2.5 K p

tr = t f = 2 P

Example:
VDD= 5 V 5 1 v o
v
I

V DD =5V

V DD =5V 32.5 1 v v o
I

M v
I

20 1 v o

2 1

13 1 1 pF

8 1 2 pF

(a)

(b)

Symmetrical reference inverter | VTP | = VTN = 1V P = 6.4 ns C = 1 pF tr = tf = 12.8 ns

5: CMOS Inverter

Scaled inverters a) P = 1 ns

b) P = 3.2 ns
26

Institute of Microelectronic Systems

Power Dissipation
6.0V

Two kinds of power dissipation in digital electronics: static power dissipation (logic gate output is stable) dynamic power dissipation (during switching of logic gate) With CMOS nearly no static power dissipation!

Output Voltage 40uA 4.0V

20uA 2.0V Drain Current

0V

0A >> 0V 2.0V

vI

4.0V

6.0V

5: CMOS Inverter

Institute of Microelectronic Systems

27

Dynamic Power Dissipation (I)

R1 Switch closes at t = 0 Non-linear Resistor

Power dissipation due to charge and i(t) discharge of capacitances + The total energy ED delivered by the V DD source is given by

+
vc (t)

ED = P(t )dt
0

(a)

vc (0) = 0

The power P(t) = VDDi(t), and because VDD is a constant,

The current supplied by source VDD is also equal to the current in capacitor C, and so dv

ED = VDD i (t )dt = VDD i (t )dt

0 0

ED = VDD C
0

dt

dt

= CVDD
Institute of Microelectronic Systems

VC ( )

VC ( 0 )

dvC

5: CMOS Inverter

28

Dynamic Power Dissipation (II)

Integrating from t = 0 to t = , with VC(0) = 0 and VC () = VDD results in
2 ED = CVDD

The total energy ETD dissipated in the process of first charging and then discharging the capacitor is equal to
2 2 CVDD CVDD + = 2 2 Discharge Charge 2 = CVDD

We know that the energy Es stored in capacitor C is given by

2 CVDD ES = 2

ETD

and thus the energy EL lost in the resistive element must be

2 CVDD EL = ED ES = 2
Institute of Microelectronic Systems

5: CMOS Inverter

29

Dynamic Power Dissipation (III)

Thus, every time a logic gate goes through a complete switching cycle, the transistors within the gate dissipate an energy equal to ETD. Logic gates normally switch states at some relatively high frequency (switching events/second), and the dynamic power PD dissipated by the logic gate is then

2 PD = CVDD f

In effect, an average current equal to (CVDDf) is supplied from the source VDD.

5: CMOS Inverter

Institute of Microelectronic Systems

30

Dynamic Power Dissipation (IV)

Power dissipation due to the short circuit current (when both transistors are on during transition) The short circuit current reaches a peak for Vin = Vout = VDD/2
5.0 V

VDD = 5 V vO Vin = Vout = VDD/2 vI vout i DD R onn R onp

Voltage
0.0 V 30uA

Current
0 uA 0s

4ns

8ns

12ns

16ns

Time
5: CMOS Inverter Institute of Microelectronic Systems 31

Summary
Lets repeat:
6.0V 40uA 4.0V Output Voltage

20uA 2.0V Drain Current 0V 0A >> 0V

What is the dynamic behaviour of the inverter? What do we need it for? What kind of power dissipation is there? What kind of power dissipation is dominant with CMOS logic?

2.0V v I

4.0V

6.0V

2 PD = CVDD f
Institute of Microelectronic Systems

5: CMOS Inverter

32