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3.

The inverter - static properties

In this chapter the basic properties of the inverter will be considered. While not being a very exciting device per se, the inverter has some very basic properties to which the properties of any logic gate, or analog amplifier circuit for that matter, can be related. Both the static and the dynamic properties of the inverter will be considered. The static properties concern the logic function of the inverter, while the dynamic properties concerns the transient switching of the output from one logical state to the other as a result of a switching input.

V IN V OUT
V IN
V OUT

VIN

VOUT

 

0 1

 

1 0

Fig. 3.1. The inverter as a symbol for a Boolean truth table.

In essence, the inverter is a symbol representing a very simple Boolean truth table as illustrated in Fig. 3.1, where a logical zero input produces a logical one at the output and vice versa. In this model nothing is said about the propagation delay between the switching of the input and the switching of the input. To account for this dynamic property of the electronic implementation of an inverter, a delay model could be added as shown in Fig. 3.2. Delay models range from very simple models for hand calculations to rather complicated models for timing analysis using electronic design automation (EDA) tools. The most simple delay model only considers a constant delay, while a more complicated delay model considers both the size of the inverter and the output load as well as the input switching speed. One value for the propagation delay that is often referred to is the fanout- of-four delay, the FO4 delay, see Fig. 3.3 which shows the delay of an inverter loaded by four identical inverters

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V

IN










V

OUT

Fig. 3.2. An inverter with a delay model.

 
 
    FO4 ‐ V OUT   delay    
 

FO4

V

OUT

 
delay  

delay

 
delay  
 
    FO4 ‐ V OUT   delay    

V IN

Fig. 3.3. An inverter with a fanout-of- four (FO4) delay.

3.1 Static properties

The aim of this section is to describe the static properties of a CMOS inverter in rather simple terms. The simplest electronic implementation of an inverter requires an electronic switch such as the N-switch described in chapter 1, and a load resistor as shown in Fig. 3.4. Here, a logical one is represented by the supply voltage V DD , while a logical zero is represented by zero voltage V SS , or ground. For this inverter to be robust the voltage transfer characteristic (VTC) should be centered on V DD /2 so that the input voltage when the inverter flips between logical states is V DD /2. The low output voltage when the MOSFET is ON is given by resistive voltage division by

V

OL

R ON

R

ON

R

L

V

DD

.

(3.1)

For this output voltage to go low the MOSFET ON resistance should be much smaller than the load resistance, i.e. R ON << R L . In Fig. 3.4 a simplified voltage transfer characteristic is shown where the MOSFET switch is assumed to turn on at V IN =V DD /2 and to have a constant on-resistance R ON (solid line). The real voltage transfer characteristic when the MOSFET

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switch is turned on at its threshold voltage V TN and the on-resistance R ON is voltage dependent is indicated by the dashed line.

V IN

V DD

dependent is indicat ed by the dashed line. V IN V DD V SS OH V

V SS

OHis indicat ed by the dashed line. V IN V DD V SS V V DD

V

V DD

IH

V SS

R L

the dashed line. V IN V DD V SS OH V V DD IH V SS

R ON

V OL

V OUT V OH V DD V D D /2 V OL V SS V
V OUT
V
OH
V DD
V D D /2
V
OL
V SS
V D D /2
V DD

V IN

Fig. 3.4. The basic inverter function illustrated with an N-switch and a load resistance R L and its voltage transfer characteristic (VTC).

In CMOS technology the resistor could be implemented by using a pseudo- NMOS load in form of a p-channel MOSFET as shown in Fig. 3.5. When used as an amplifier in an analog design, the p-channel load device is usually biased through a current mirror designed so that current I B , or fractions of

this current, also flows through the inverter.

V B

v IN

V DD
V
DD

v

OUT

Fig. 3.5. The pseudo-NMOS-inverter.

V

DD

V DD   V DD
 
V DD
V
DD
   
    V B

V

B

   

v

I

B

I B     v IN  
   
v IN
v
IN
 

OUT

A more power-efficient implementation of an inverter uses two

complementary switches as shown in Fig. 3.6. For a high input V IH , the N-

switch turns ON and the P-switch turns OFF making the output go low, V OL . For a low input V IL the N-switch turns OFF and the P-switch turns ON making the output go high, V OH . Since one of the two switches is always

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OFF, there is no static power dissipation in any of the two logic states, a
OFF, there is no static power dissipation in any of the two logic states, a fact
that is the main advantage of the CMOS technology.
V
V
OUT
DD
V DD
V DD
V
OH
V
ON
OFF
DD
VTC
V
V IN
V OUT V IL
OH
V IH
V OL
V
D D /2
OFF
ON
V
V
SS
V SS
V SS
OL
V
V
IN
SS
V
D D /2
V
DD

Fig. 3.6. The CMOS-inverter function illustrated with switches and a simplified voltage transfer characteristic (VTC).

In this CMOS implementation of an inverter there is a full output voltage swing between the supply rails V DD and V SS , independent of the ON resistances of the switches. The switching voltage of the CMOS inverter is given by the input voltage for which both MOSFET devices deliver the same saturation current. For a robust design with a switching voltage equal to V DD /2 both MOSFETs should have the same driving capability. In more detail, the accepted output voltage range for a logical one is given by V OH,min <V OUT <V DD , while the accepted output voltage range for a logical zero is given by V SS <V OUT <V OL,max , see Fig. 3.7. If the input voltage resulting in V OH,min is denoted V IL,max , and the input voltage resulting in V OL,max is denoted V OL,min we can draw a simplified, piecewise linear, voltage transfer characteristics as shown in Fig. 3.7. In this VTC we can see that V OL,max <V IL,max , and V IH,min <V OH,min , facts that indicate good noise margins. These noise margins, NM H and NM L , are defined in Fig. 3.7. Another property of the CMOS inverter is its level-restoring properties. In Fig. 3.8 we can see that even if the input to a CMOS inverter is way outside the allowed voltage ranges, the output voltage of is fully restored already after two inverters. This is a consequence of the nonlinear voltage transfer characteristics.

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V

V

V

V

V OUT DD OH,min N MH N ML OL,max SS V SS V IL,max V
V OUT
DD
OH,min
N
MH
N
ML
OL,max
SS
V SS
V IL,max V IH,min V DD

V IN

V

V

V

V

DD

IH,min

IL,max

SS

Fig. 3.7. Definition of noise margins using a simplified piecewise-linear voltage transfer curve (VTC).

V

IN

 

V 1

V 2

 
 
 
curve (VTC). V IN   V 1 V 2   Fig. 3.8. Illustration of the level-restoring

Fig. 3.8. Illustration of the level-restoring properties of the inverter.

In summary, the basic properties of a CMOS inverter are

Full voltage swing from rail to rail

No static power dissipation

Robustness

Noise margins

Level-restoring.

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3.2

The voltage transfer curve (VTC) in detail

When calculating the inverter voltage transfer characteristic, we use a simple circuit model where the MOSFET is represented by its ON resistance in the linear region and by its saturation current I DSAT in the saturation region.

V IN

V DD

I D S A T in the saturation region. V IN V DD R L V

R L

I D S A T in the saturation region. V IN V DD R L V

V SS

V

V

DD
DD

R L

V

R ON

region. V IN V DD R L V SS V V DD R L V R

OUT

V SS

V

DD
DD

R L

V

OUT

V SS

OUT

I DSAT

SUBTHRESHOLD REGION
SUBTHRESHOLD REGION

Fig. 3.9. The basic inverter with a load resistance R L and its voltage transfer characteristic.

Exercise 3.1: Derive the equations describing the MOS-inverter voltage transfer characteristic in Fig. 3.9. Solution.
Exercise 3.1: Derive the equations describing the MOS-inverter voltage
transfer characteristic in Fig. 3.9.
Solution. The load line of the resistor is given by
V
V
DD
OUT
I 
.
(3.2)
R
L
The n-channel switch is either saturated or acting as a resistor: in the green
region where the MOSFET is saturated equal currents through the load
resistor and the MOSFET yield

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Solving for V OUT yields the following equation describing a parabola for the transfer characteristic in the green region

V

2

Using the same condition of current identity in the blue region where the MOSFET behaves like a nonlinear resistor, we obtain

1

kR

L

2  1  2 V DD VV     IN TN kR
2
1
2 V
DD
VV

IN
TN
kR
kR
L
L

When kR L →∞, this expression simplifies to

V OUT

V DD

R ON

which is nothing but plain simple voltage division between resistors R ON and R L .

I

DSAT

k

VV 

IN

TN

2

I DSAT  k  VV  IN TN  2 V DD  V OUT
I DSAT  k  VV  IN TN  2 V DD  V OUT
I DSAT  k  VV  IN TN  2 V DD  V OUT

V

DD

V

OUT

.

(3.3)

2

R

L

OUT

V

DD

kR

L

VV

IN

TN

OUT  V DD kR L  VV  IN TN  2 . (3.4)
OUT  V DD kR L  VV  IN TN  2 . (3.4)

2 .

(3.4)

V

OUT

VV



IN

TN

. (3.5)

kR

L

V

IN

V

TN

R

L

,

 

The basic parameter of this VTC is given by kR L ; the higher the value of this parameter, the better the inverter characteristic and the higher the voltage amplification in the switching region. Large values of kR L means that R L >> R ON , i. e. the MOSFET must be designed for high driving capability with respect to the load resistance. This is why this logic style is named ratioed logic. This VTC is again illustrated in the right-hand diagram of Fig. 3.10 while the left-hand diagram shows the resistor load line and MOSFET IV- characteristic for two different input gate voltages.

.1

The CMOS inverter

The voltage transfer characteristic of the CMOS inverter can be derived similarly. However, it is just a little bit more complicated since we must

keep track of the operation regions of both the nMOS transistor and the pMOS load transistor. As shown in Fig. 3.11, we have to keep track of the following regions and MOSFET bias conditions:

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Fig. 3.10. Load curves for the n-channel MOSFET for two different input voltages plotted together

Fig. 3.10. Load curves for the n-channel MOSFET for two different input voltages plotted together with the resistor load line (left), and the inverter voltage transfer characteristic (right).

V

V

DD

UT

V

V DD DD R ON,P V OUT I DSAT,N
V
DD
DD
R
ON,P
V
OUT
I
DSAT,N

V DD

V V DD UT V V DD DD R ON,P V OUT I DSAT,N V DD
I
I

I DSAT,P

V OUT

I DSAT,N

DSAT,P

V OUT

R ON,N

Region A, B

Region C

Region D, E

B: pMOS ‐ resistive Region C: Both MOSFETs saturated D: nMOS ‐ resistive A: n‐subthreshold
B: pMOS ‐ resistive
Region C:
Both MOSFETs
saturated
D: nMOS ‐ resistive
A: n‐subthreshold region
E: p‐subthreshold region

V

TN

V

IN

V

DD +V TP

V DD

Fig. 3.11. Regions of MOSFET operation for the CMOS inverter.

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both n-channel and p-channel MOSFETs are saturated (region C)

n-channel MOSFET is saturated (or OFF) and p-channel MOSFET is linear (regions A and B)

p-channel MOSFET is saturated (or OFF) and n-channel MOSFET is linear (regions C and D)

The circuit element representation of the MOSFETs in the CMOS inverter is shown at the top of Fig. 3.11. In Fig. 3.12 we can see the current/voltage characteristics of the two MOSFETs for three different input voltages (left) and the resulting bias points on the VTC on the right. Most easily recognized is the illustration of region C marked V IN =V SW . In the left-hand diagram we can see that for this input voltage both MOSFETs deliver the same saturation currents resulting in a region of infinite voltage amplification in the right- hand VTC. This is the input voltage V SW for which the inverter flips. It can be derived from the following equation of equal saturation currents:

k n

2

V GSTN

2

k

p

2

V

SGTP

2

where

V

GSTN

VV

IN

TN

and

V

SGTP

V

DD

VV

IN

TP

.

(3.6)

The resulting switching voltage is then given by

V

in

V

sw

V  V  xV DD TP TN 1  x
V
V
xV
DD
TP
TN
1 
x

, where x=k N / k P .

(3.7)

For V TN =-V TP and x=1 the switching voltage is V DD /2. For strong n-channel devices, x >1, V sw < V DD /2 and for strong p-channel devices, V sw > V DD /2,

for strong p-channel devices, V s w > V D D /2, Fig.3.12. Finding bias points
for strong p-channel devices, V s w > V D D /2, Fig.3.12. Finding bias points

Fig.3.12. Finding bias points on the CMOS inverter VTC.

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In region B, where the p-channel device is resistive, the VTC curve can be derived from the following equal current condition:

yielding

 V k n  V 2 DD OUT V  kV   
 V
k n
V
2
DD
OUT
V

kV
 
V
V
,
GSTN
p
SGTP
DD
OUT
2
2
2 k
2
N

VV
 V

VV
VV
.
V OUT
IN
TP
DD
IN
TP
IN
TN
k
P

(3.8)

(3.9)

Similarly for region D, where the n-channel device is resistive, we obtain the following equal
Similarly for region D, where the n-channel device is resistive, we obtain the
following equal current condition
V UT
k
V

V
V
kV

V
V
 2 ,
(3.10)
N
IN
TN
UT
P
DD
IN
TP
 
2
 
yielding
2 k
2
P

VV
VV
V

VV
.
(3.11)
V OUT
IN
TN
IN
TN
DD
IN
TP
k
N
3.3 Process corners

Due to process variations k n /k p varies across the wafer and between wafers. This results in a spread of inverter switching voltages as shown in Fig. 3.13. The process corners of the MOSFET driving capabilities are also illustrated.

of the MOSFET drivi ng capabilities are also illustrated. k P HI, LO HI, HI LO,
k P HI, LO HI, HI LO, LO LO, HI
k P
HI, LO
HI, HI
LO, LO
LO, HI

k N

Fig. 3.13. MOSFET driving capability process window (right) and resulting spread of inverter switching voltages (left).

54

3.4

The inverter as an analog amplifier

The inverter is of course a digital device, but the circuit implementation of the inverter also works as an amplifier of small analog signals. This is illustrated in Fig. 3.14. The figure shows how a MOSFET with a load resistor has been biased in the saturation region where the MOSFET acts as a voltage-controlled current source. A small sinusoidal input signal, on top of the bias voltage, results in an amplified sinusoidal at the output. The voltage amplification can be calculated from the small signal model, A v =-g m R L .

v IN

V DD

small signal model, A v =-g m R L . v IN V DD V SS

V SS

large‐ signal model small ‐signal model R R R L L L v v OUT
large‐ signal model small ‐signal model
R
R
R
L
L
L
v
v
OUT
OUT
v out =‐ g m R L v in
I
DSAT
g m v
in
V
V
SS
SS
SUBTHRESHOLD REGION
SUBTHRESHOLD REGION

Fig. 3.14. Basic amplifier circuit.

55

The design methodology assumed by the analog designer is to use nonlinear large-signal analysis for calculating the bias point and the linear region of operation of the amplifier, and to use linear small-signal analysis for calculating the voltage amplification. The output voltage range of the amplifier is limited by distortion due to the nonlinear transfer characteristic. The linearized small-signal transfer curve with slope A v is shown dashed (in red). The small-signal amplification is given by

A

v

v

OUT

v

IN

vi

OUT

OUT



i

OUT

v

IN



R

L

g

m

.

(3.12)

The nonlinearity of the transfer curve that is an advantage in digital designs, giving the inverter its level restoring properties, is a disadvantage in analog designs due to distortion and creation of overtones.

3.4.1 The pseudo-NMOS amplifier

The most common analog integrated circuit CMOS amplifier is the pseudo- NMOS-inverter amplifier shown in Fig. 3.15. In this design, the load resistor is implemented by use of a pMOS device since area-efficient resistors are not available in CMOS integrated circuit technology. The pMOS load transistor has a fixed bias voltage V B indirectly set by the current mirror M2- M3. The reference current I B , or multiples thereof, is mirrored from a reference stage to the amplifier stage. The same current will flow through M2 and M3 since they have the same gate to source voltage provided they are designed for equal driving capabilities. The amplifier large-signal and small-signal models are also shown in the figure.

V DD V B M 3 2 I B v IN M 1
V
DD
V
B
M
3
2
I
B
v IN
M
1

V

DD

M

I B

figure. V DD V B M 3 2 I B v IN M 1 V DD

v OUT

largesignal model small signal model

B v OUT large ‐ signal model small ‐ signal model I B I v OUT
B v OUT large ‐ signal model small ‐ signal model I B I v OUT
B v OUT large ‐ signal model small ‐ signal model I B I v OUT
I
I

B

I

v OUT

DSAT

signal model small ‐ signal model I B I v OUT DSAT g mn v IN
signal model small ‐ signal model I B I v OUT DSAT g mn v IN

g

mn

v

IN

v OUT

g

dp



g

dn

g

dp

g mn v in

g dn

Fig. 3.15. The pseudo-NMOS amplifier and its circuit models.

56

The designer determines the amplifier current level to provide the n-channel MOSFET with a certain transconductance at a certain gate bias,

g

mn

i

DSAT N

,

v

GS

I

B

V

GSTN

/ 2

,

(3.13)

where typically the gate bias V GSTN =V IN -V TN is in the 100-200 mV range. The nMOS-transistor is sized to sink the given current I B at this given bias voltage, i.e.

I

B

k

2

VV

IN

TN

2 .

(3.14)

The amplifier transfer curve is shown in Fig. 3.16. Its region of linear operation is determined by the saturation condition for the two MOSFETs

V

DD

VV

IN

TN

VV

 

B

TP

V

OUT

V

DD

V

OUT

V

OUT

VV



B

TP

nMOS .

pMOS

(3.15)

Hence, the region of operation is given by

V

IN

V V VV

TN

OUT

B

TP

,

(3.16)

as shown in Fig. 3.16. The smaller the gate voltage overdrive, the larger the region of linear amplifier operation. In essence, the gate voltage overdrives chosen determines how close to the rails the amplifier will work.

SUBTHRESHOLD REGION
SUBTHRESHOLD REGION

Fig. 3.16. The amplifier and its linear region of operation.

57

For this amplifier circuit, the small-signal model must be more detailed than before in that the MOSFET output conductance must be carefully considered. From the small-signal model of the amplifier circuit, the following small signal amplification can be derived

A

v

v

OUT

v

IN



g

mn

gg

dn

dp

.

(3.17)

Example 3.2 . Calculate the circuit voltage amplification at a current level of 200 A
Example 3.2 . Calculate the circuit voltage amplification at a current level of
200 A if the MOSFETs are biased with gate voltage overdrives of 200 mV.
The Early voltages of the devices are assumed to be 5 V.
Solution: The transconductance is given by
I
200 [μA]
B
g

 2 mA/V.
mn
/ 2
100 [mV]
V GSTN
The output conductance is approximately given by
g
d 
 40 μA/V.
V A 5 [V]
The voltage amplification is then
g
2
mn
A

 25.
v
g
g
0.04
0.04
dn
dp
It is interesting to note that, in the case of equal Early voltages, the voltage
amplification can be written
V
5
0,2
V GST

I

B

200 [μA]

A

v



A

25.

Example 3.3 . Is it reasonable to neglect velocity saturation for a MOSFET biased at
Example 3.3 . Is it reasonable to neglect velocity saturation for a MOSFET
biased at V GST =100 mV if the velocity saturation voltage is V C =2 V?
Solution: With V C =2 the drain current saturation voltage is given by
V
V
0.2
GST
C
V
 V
2.1
GST
C
The error is only 5%, resulting in a 5% error in the calculation of the
saturation current. However, for V GST =200 mV and V C =1 V, the error is 20%.
For calculating the maximum saturation current available at say V GST =0.9 V,
great care must be taken to use the saturation voltages. For the two cases of
V C =1 V and V C =2 V, the correct saturation voltages are 0.47 V and 0.31 V.

V DSAT

 0.095 V.

58

Using V DSAT =0.9 V, instead of the correct values, for calculating the saturation current would result in an overestimation of the saturation current by a factor of two and three, respectively.

3.4.2 The CMOS inverter as an amplifier

The same type of analysis can be applied to calculate the small-signal properties of the CMOS inverter. Its large-signal and small-signal equivalent circuits are shown in Fig. 3.17. The region of amplifier operation can be derived from large-signal analysis using the saturation conditions

V

DD

VV

IN

TN

V

OUT

VVV



IN

TP

DD

V

OUT

V

OUT

VV



IN

TP

nMOS .

pMOS

(3.18)

Hence, the region of amplifier operation is given by

V

BIAS

VV V V

TN

OUT

BIAS

TP

,

(3.19)

where V IN =V BIAS is the input bias voltage. The bias point and the (green) region of amplifier operation around the bias point are indicated in Fig. 3.18. The Norton and Thevenin equivalent circuits resulting from the inverter small-signal equivalent circuit in Fig. 3.17 is shown in Fig. 3.19. As indicated by the figure, the CMOS inverter can be equivalently regarded as a current source or a voltage source, both with an internal source resistance determined by the sum of the output conductances.

V IN

largesignal model

V V DD DD I DSAT,P V V OUT OUT I DSAT,N V SS
V
V
DD
DD
I
DSAT,P
V
V
OUT
OUT
I
DSAT,N
V
SS

small signal model

V V OUT OUT I DSAT,N V SS small ‐ signal model g g dp v

g

V V OUT OUT I DSAT,N V SS small ‐ signal model g g dp v

g

dp

v

mp v in

g

mn v in

g

dp

out

Fig. 3.17. The CMOS-inverter, its large- and small-signal equivalent circuits

59

n‐subthreshold region p‐subthreshold region
n‐subthreshold region
p‐subthreshold region

Fig. 3.18. The CMOS-inverter and its voltage transfer characteristic.

Obviously, the voltage amplification of the CMOS inverter as an amplifier is given by

A

v

v

OUT

v

IN



g

mn

g

mp

gg

dn

dp

.

(3.20-)

Due to several reasons the CMOS inverter amplifier is not commonly used. First, the input voltage range of the CMOS amplifier is often very narrow as is apparent from the figure; secondly, it also receives poor marks on other amplifier properties such as supply noise rejection [Rabaey et al., p 190].

Example 3.4: Compare the voltage amplification of the CMOS inverter to that of the pseudo-NMOS amplifier in Example 3.2. Solution : Provided g mp =g mn , the voltage amplification is given by

A

v



g

mn

g

mp

2

2

g

dn

g

dp

0.04

0.04

50.

Twice!

(g mn + g mp )v in

v out g dn +g dp Norton circuit
v out
g
dn +g dp
Norton circuit

mn + g mp )v in v out g dn +g dp Norton circuit  g

g mn

g

mp

g dn

g

dp

v

in

g dn +g dp v out + ‐ Thevenin circuit
g dn +g dp
v out
+
Thevenin circuit

Fig. 3.19. Norton and Thevenin equivalent circuits of the CMOS amplifier.

60

3.5

Summary

In this chapter we have investigated the functionality and the static properties of the CMOS inverter. First, the digital properties of the inverter were studied and its voltage transfer characteristic was derived and analyzed. Three different inverter implementations were analyzed; with resistive load, with pseudo nMOS load and with active pull-up pMOS load. The inverter switching voltage and its noise margins were defined. Variations across the wafer and between wafers due to process variations were mentioned. Finally, the small-signal properties of the inverter as an analog amplifier were discussed.

61