Main Memory

By

Prof. Dr. Shaiq A. Haq

Air University, E-9, Islamabad

Scheme of Presentation
Overview of Main Memory
SRAM, DRAM

64MB DRAM Logical Organization Improved Architectures of DRAM for Performance Enhancement
SDRAM (Synchronous DRAM) RDRAM (Rambus DRAM) DDR (Double Data Rate DRAM)

Memory Interfacing Cache Memory

Memory Hierarchy
Regs Instructions, Operands L1 Cache Inside CPU

Upper Level
Faster

Blocks L2 Cache Blocks Main Memory

Virtual Memory

Pages Disk Files Tape Larger Lower Level

Main Memory Background

Next level down in the hierarchy
satisfies the demands of caches + serves as the I/O interface

Performance of Main Memory:

Latency: Cache Miss Penalty
Access Time: time between when a read is requested and when the desired word arrives Cycle Time: minimum time between requests to memory

Bandwidth (the number of bytes read or written per unit time): I/O & Large Block Miss Penalty (L2)

Main Memory is DRAM: Dynamic Random Access Memory

Dynamic since needs to be refreshed periodically (8 ms, 1% time) Addresses divided into 2 halves (Memory as a 2D matrix):
RAS or Row Access Strobe + CAS or Column Access Strobe

Cache uses SRAM: Static Random Access Memory

No refresh (6 transistors/bit vs. 1 transistor)

Memory Background: Static RAM (SRAM) Six transistors in cross connected fashion
Provides regular AND inverted outputs Implemented in CMOS process

Single Port 6-T SRAM Cell

Memory Background: Dynamic RAM(DRAM)

SRAM cells exhibit high speed/poor density DRAM: simple transistor/capacitor pairs in high density form
Word Line

. . .

Bit Line

Sense Amp

Static RAM
Bits stored as on/off switches, uses digital flip-flops No charges to leak No refreshing needed when powered More complex construction Larger per bit More expensive Does not need refresh circuits Faster Cache

Dynamic RAM
Bits stored as charge in capacitors Essentially analogue
Level of charge determines value

Charges leak Need refreshing even when powered Simpler construction Smaller per bit Less expensive Need refresh circuits Slower Main memory

SRAM v DRAM
Both volatile
Power needed to preserve data

Dynamic cell
Simpler to build, smaller More dense Less expensive Needs refresh Larger memory units

Static
Faster Cache

Types of Read Only Memory (ROM)

Written once, during manufacture
Very expensive for small runs

Programmable (once)
PROM Needs special equipment to program

Read mostly
Erasable Programmable (EPROM)
Erased by UV

Electrically Erasable (EEPROM)

Takes much longer to write than read

Flash memory
Erase whole memory electrically

DRAM logical organization (64 Mbit)

Square root of bits per RAS/CAS

Typical 16 Mb DRAM (4M x 4)

Packaging

Memory Interfacing Circuit

Enhanced DRAM (EDRAM)

EDRAM includes a small amount of Static RAM inside a large amount of DRAM to act as cache memory for storing column address or row address. An older product from Enhanced Memory Systems, inc. EDRAM was also made by RAMTRON. It is also known as Cache DRAM. CDRAM was developed by Mitsubishi. Also known as Fast Page Mode DRAM.

Synchronous DRAM (SDRAM)

Access is synchronized with an external clock Address is presented to RAM RAM finds data (CPU waits in conventional DRAM) Since SDRAM moves data in time with system clock, CPU knows when data will be ready CPU does not have to wait, it can do something else Burst mode allows SDRAM to set up stream of data and fire it out in block DDR-SDRAM sends data twice per clock cycle (leading & trailing edge)

IBM 64Mb SDRAM

Improving Memory Performance in Standard DRAM Chips (contd)

Synchronous DRAM
add a clock signal to the DRAM interface

DDR Double Data Rate

transfer data on both the rising and falling edge of the clock signal

Improving Memory Performance via a New DRAM Interface: RAMBUS (contd)

RAMBUS provides a new interface memory chip now acts more like a system First generation: RDRAM
Protocol based RAM w/ narrow (16-bit) bus
High clock rate (400 Mhz), but long latency Pipelined operation

Multiple arrays w/ data transferred on both edges of clock

Second generation: direct RDRAM (DRDRAM) offers up to 1.6 GB/s

RAMBUS (contd)
Adopted by Intel for Pentium & Itanium Main competitor to SDRAM Vertical package all pins on one side Data exchange over 28 wires < cm long Bus addresses up to 320 RDRAM chips at 1.6Gbps Asynchronous block protocol
480ns access time Then 1.6 Gbps

Improving Memory Performance via a New DRAM Interface: RAMBUS

RDRAM Memory System

RAMBUS Bank

Summary of Memory Types

FPM DRAM; Fast page mode dynamic random access memory was the original form of DRAM. Uses a SRAM as Cache to store page or column address. EDO DRAM; Extended data-out dynamic random access memory does not wait for all of the processing of the first bit before continuing to the next one. As soon as the address of the first bit is located, EDO DRAM begins looking for the next bit. It is about five percent faster than FPM. Optimized for 66MHz Pentium. Maximum transfer rate to L2 cache is approximately 264 MBps. SDRAM; Synchronous dynamic random access memory takes advantage of the burst mode concept to greatly improve performance. It does this by staying on the row containing the requested bit and moving rapidly through the columns, reading each bit as it goes. The idea is that most of the time the data needed by the CPU will be in sequence. SDRAM is about five percent faster than EDO RAM and is the most common form in desktops today. Maximum transfer rate to L2 cache is approximately 528 MBps.

Summary of Memory Types (contd)

DDR SDRAM; Double data rate synchronous dynamic RAM is just like SDRAM except that is has higher bandwidth, meaning greater speed. Maximum transfer rate to L2 cache is approximately 1,064 MBps (for DDR SDRAM 133 MHZ). RDRAM; Rambus dynamic random access memory is a radical departure from the previous DRAM architecture. Designed by Rambus, RDRAM uses a Rambus in-line memory module (RIMM), which is similar in size and pin configuration to a standard DIMM. What makes RDRAM so different is its use of a special high-speed data bus called the Rambus channel. RDRAM memory chips work in parallel to achieve a data rate of 800 MHz, or 1,600 MBps. Since they operate at such high speeds, they generate much more heat than other types of chips. To help dissipate the excess heat Rambus chips are fitted with a heat spreader, which looks like a long thin wafer. Just like there are smaller versions of DIMMs, there are also SO-RIMMs, designed for notebook computers.

Summary of Memory Types (contd)

FLASH MEMORY; Flash memory is a solid-state, non-volatile, rewritable memory that functions like RAM and a hard disk drive combined. Flash memory stores bits of electronic data in memory cells, just like DRAM, but it also works like a hard-disk drive in that when the power is turned off, the data remains in memory. Flash memory is a type of EEPROM chip. Because of its high speed, durability, and low voltage requirements, flash memory is ideal for use in many applications - such as digital cameras, cell phones, printers, handheld computers, pagers, and audio recorders. Flash memory is avaliable in many different form factors, including: CompactFlash, Secure Digital, SmartMedia, MultiMedia and USB Memory.

SIMM is an acronym for Single Inline Memory Module DIMM is an acronym for Dual Inline Memory Module. RIMM is an acronym for Rambus Inline Memory Module

Levels of the Memory Hierarchy

CPU Registers
100s Bytes <1s ns

Capacity Access Time Cost

Registers

Staging Xfer Unit

Upper Level faster

Cache

Instr. Operands prog./compiler Cache Blocks Memory Pages Disk Files Tape
1-8 bytes

10s-100s K Bytes 1-10 ns $10/ MByte

Main Memory

cache cntl 8-128 bytes

M Bytes 100ns- 300ns $1/ MByte

Disk

OS 512-4K bytes

Tape

10s G Bytes, 10 ms (10,000,000 ns) $0.0031/ MByte

infinite sec-min $0.0014/ MByte

user/operator Mbytes

Larger

Lower Level

Processor-DRAM Speed Gap

1000

Processor: 2x/1.5 year

CPU

Performance

100

Processor-Memory Performance Gap grows 50% / year

10

Memory: 2x/10 years

DRAM

1 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000

Time

Why hierarchy works?

Principal of locality
Probability of reference Address space Rule of thumb: Programs spend 90% of their execution time in only 10% of code

Temporal locality: recently accessed items are likely to be accessed in the near future Keep them close to the processor Spatial locality: items whose addresses are near one another tend to be referenced close together in time Move blocks consisted of contiguous words to the upper level

Why Virtual Memory?

Today computers run multiple processes, each with its own address space Too expensive to dedicate a full-address-space worth of memory for each process Principle of Locality
allows caches to offer speed of cache memory with size of DRAM memory DRAM can act as a cache for secondary storage (disk) Virtual Memory

Virtual memory divides physical memory into blocks and allocate them to different processes

Virtual Memory Motivation

Historically virtual memory was invented when programs became too large for physical memory Allows OS to share memory and protect programs from each other (main reason today) Provides illusion of very large memory
sum of the memory of many jobs greater than physical memory allows each job to exceed the size of physical mem.

Allows available physical memory to be very well utilized Exploits memory hierarchy to keep average access time low

Mapping Virtual to Physical Memory

Program with 4 pages (A, B, C, D) Any chunk of Virtual Memory assigned to any chuck of Physical Memory (page)
Virtual Memory 0 A 4 KB B 8 KB C 12 KB D Disk D Physical Memory
0 4 KB 8 KB 12 KB 16 KB 20 KB 24 KB 28 KB

B A C