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This design tool is used for a PFC pre-regulated boost converter design using the FAN9612 Interleaved Dual BCM PFC Controller. It complements the Quick Setup Guide procedure in the FAN9612 datasheet and the design procedure described in AN-8086 the application note for FAN9612. This tool is meant to be used with both documents. The FAN9612 Design Tool consists of three steps. Each step is contained in a separate worksheet that can be accessed from the tabs at the bottom. Step 1: Enter their desired power supply performance specifications. The worksheet then calculates the ideal component values based on the input specifications. Step 2: Select real component values based on the ideal component values calculated in Step 1. The worksheet then calculates the real power supply performance specifications. Final Step: The third and final step provides an overview of the schematic and components selected. A loop gain Bode Plot is shown as well to conclude the design.
DISCLAIMER:
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT, CIRCUIT OR TOOL DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
Note: No macros or code was used in the Design Tool in an effort to provide simple, efficient and safe tools.
Project
Designer Date
2009 Fairchild Semiconductor Corporation. All rights reserved. Rev. 2.0.0 07/24/2009 Smith, Guo
www.fairchildsemi.com
From Power Supply Specification: Min. AC RMS Input (turn-on) Min. AC RMS Input (turn-off) Nominal AC RMS Input Max. AC RMS Input Min. Line Frequency Nominal DC Output Output Voltage Ripple (2 fLINE) Latching Output OVP Full Load Output Power Soft Start dVOUT/dt Desired Hold Up Time Pre-Calculated Parameters: Estimated Conversion Efficiency Turns Ratio (NBOOST / NAUX) Output Capacitance Boost Inductance per Channel Output Power per Channel Max. Output Power per Channel Max. On-Time per Channel Other Variables Used During the Calculations: Peak Inductor Current Max. DC Output Current (to load) Calculated Component Values: Zero Current Detect Resistor Bypass Capacitor for 5V Bias Maximum On-time Set Soft-Start Capacitor Compensation Capacitor Compensation Resistor Compensation Capacitor Feedback Divider Feedback Divider Over Voltage Sense Divider VLINE.ON VLINE.OFF VLINE.Norminal VLINE.MAX fLINE,MIN VOUT VOUT,RIPPLE VOUT,LATCH POUT dVOUT/dt tHOLD N COUT L POUT,CH PMAX,CH tON,MAX 73 V 70 V 110 V 265 V 50 Hz 400 V 8V 468 V 400 W 1.500 V/ms 20.00 ms 0.95 10 398 F 175 H 200 W 260 W 19.565 s Line OVP Voltage Min. Allowable Brown-Out Hysteresis VLINE,OVP Vline,Hyst 280 V 3.1 V Min. DC Output (end of tHOLD) Min. Switching Frequency Max. DC Bias (for FAN9612) Voltage Loop Crossover Frequency Feedback Pole Frequency Feedback Power Dissipation OVP Network Power Dissipation VIN Sense Power Dissipation Power Supply Over design VOUT,MIN fSW,MIN VDDMAX 330 V 50 kHz 15.00 V 6.0 Hz 150 Hz 0.150 W 0.100 W 0.070 W 1.30
fc
IL,PK IO,MAX RZCD1, RZCD2 C5VB RMOT CSS CCOMP,LF RCOMP CCOMP,HF RFB1 RFB2 ROV1
11.059 A 1.300 A 46.80 k 0.220 F 85.07 k 444 nF 336 nF 78.85 k 13.5 nF 1058.7 k 8.00 k 2173.9 k Over Voltage Sense Divider Input Voltage Sense Divider Input Voltage Sense Divider Brown-Out Hysteresis Set Input Voltage Sense Filter Capacitor Gate Drive Resistor Bypass Capacitor for VDD - HF Startup Energy Storage for VDD Current Sense Resistor Current Sense Resistor Power ROV2 RIN1 RIN2 RINHYST CINF RG1, RG2 CVDD1 CVDD2 RCS1, RCS2 PRCS1, PRCS2 16.38 k 2219.1 k 20.93 k 0.00 k 9.6 nF 15.00 2.2 F 22 F 0.0181 0.437 W
Note: Cells that have white text on a red background indicate that there is an error. Certain parts of the circuit will not operate properly if these items are not addressed.
Project
Designer Date
2009 Fairchild Semiconductor Corporation. All rights reserved. Rev. 2.0.0 07/24/2009 Smith, Guo
www.fairchildsemi.com
Note: Cells that have white text on a red background indicate that there is an error. Certain parts of the circuit will not operate properly if these items are not addressed. Cells with red text indicate that the parameter values calculated differ greatly from the desired value. Project Designer Date
www.fairchildsemi.com
2009 Fairchild Semiconductor Corporation. All rights reserved. Rev. 2.0.0 07/24/2009 Smith, Guo
VOU
CIN
D1
L1b RFB1
2 3 4
VBIAS
Q1
RFB2
RINHYST
RG1 RG2
Q2
ROV1
CVDD1 CINF
CVDD2
ROV2
Selected Component Values: Output Capacitance (total) Boost Inductance (per channel) Zero Current Detect Resistor Bypass Capacitor for 5V Bias Maximum On-time Set Soft-Start Capacitor Compensation Capacitor Compensation Resistor Compensation Capacitor Feedback Divider Feedback Divider COUT L1, L2 RZCD1, RZCD2 C5VB RMOT CSS CCOMP,LF RCOMP CCOMP,HF RFB1 RFB2 440 F 180 H 47.5 k 0.220 F 84.5 k 470 nF 390 nF 68.1 k 15.0 nF 1066 k 8.1 k Over Voltage Sense Divider Over Voltage Sense Divider Input Voltage Sense Divider Input Voltage Sense Divider Brown-Out Hysteresis Set Input Voltage Sense Filter Capacitor Gate Drive Resistor Bypass Capacitor for VDD - HF Startup Energy Storage for VDD Current Sense Resistor Current Sense Resistor Power ROV1 ROV2 RIN1 RIN2 RINHYST CINF RG1, RG2 CVDD1 CVDD2 RCS1, RCS2 PRCS1, PRCS2
Note: Cells that have white text on a red background indicate that there is an error and the component value cannot be displayed.
Project
Designer Date
2009 Fairchild Semiconductor Corporation. All rights reserved. Rev. 2.0.0 07/24/2009 Smith, Guo
www.fairchildsemi.c
mponents selected through Steps 1 and 2. e using the component values displayed below.
D1 COUT
FAN9612
CS1 16 CS2 15 VDD 14 DRV1 13 DRV2 12 PGND 11 VIN 10 OVP
9
L1b RFB1
VBIAS
Q1
RFB2
RG1 RG2
Q2
ROV1
RCS1
RCS2
CVDD1 CINF
CVDD2
ROV2
Selected Component Values: 2190 k 16.5 k 2226 k 21.0 k 0.0 k 10 nF 15.00 2.2 F 22 F 0.0200 0.395 W
www.fairchildsemi.com
Magnitude (dB)
0 -20
-40
-60 -80 -100 -120 0.1 1 10 100 Frequency (Hz) 1000 10000
80 70 Phase (deg) 60
50 40 30 20 10 0 0.1 1 10 100 Frequency (Hz)
6.31 Hz 59.67 deg
1000
10000
Note: This spreadsheet uses complex number, so Analysis ToolPak installation is required. Project
Designer Date
2009 Fairchild Semiconductor Corporation. All rights reserved. Rev. 2.0.0 07/24/2009 Smith, Guo
www.fairchildsemi.com