16-bit Binary Multiplication Using High Radix Analog Digits

Mitra Mirhassani and Majid Ahmadi

RCIM Lab Department of Electrical and Computer Engineering University of Windsor Windsor, ON, CANADA, N9B 3P4 Email: mirhass@uwindsor.ca

Graham A. Jullien
ATIPS Lab Department of Electrical and Computer Engineering University of Calgary Calgary, AB, CANADA, T2N 1N4

Abstract In this paper, a binary multiplier based on the Continuous Valued Number System (CVNS), and consisting of arrays of current mode modulo adders, is discussed. The Continuous Valued Number System uses analog current mode circuitry, with attendant very low system noise, to create arithmetic units with arbitrary equivalent digital precision. A series of analog digits, computing over arbitrary radix rings is used, in a forward correction mode, to achieve this comparable digital accuracy despite the fact that the implementation employs only relatively simple analog circuits. To reduce the area and power requirements in CVNS multipliers, columns of partial products are added in higher radices. In this paper, details of the design and implementation of a 16-bit binary multiplier in radix-4 CVNS are provided.

structure. The CVNS array multiplier consists of a regular arrangement of addition operations and exploits the CVNS redundancy. The term Array Multiplier is derived from the array structure of a collection of adders, where they are laid out on a two-dimensional plane. The basis of the array multiplication are integer residue scaling and residue addition. Such an approach is used in developing the digital multiplier discussed in this paper. The proposed multiplier is designed into the target 0.18m CMOS technology and favourably compared with standard binary multipliers in the same technology. II. CONTINUOUS DIGITS Any value within a boundary such as |P | M from a positional number system with radix B , can be mapped to a set of associated CVNS digits, i , in radix- . FCV N S : P
CV N S

I. I NTRODUCTION Efcient logic circuit design is a fundamental task in the design of high performance devices. For arithmetic implemented in System-on-Chip (SoC) technologies, there are increasing demands on higher speed, limiting area, and system and crosstalk noise. Most modern arithmetic processors are built with architectures that have been well-established in the literature, with many of the latest innovations devoted to special logic circuits and the use of advanced technologies. Specically, the design of multipliers is critical in digital signal processing applications, where a high number of multiplications is required. There are a wide variety of methods for multiplication with complexity order n and log (n) gate delay. Array multipliers offer regular layout, and are generated by a regular array of full adders and half adders [1][7]. In this paper the design and implementation of an array multiplier using the Continuous Valued Number System (CVNS) is explored. The CVNS [8] has a potential advantage to reduce the wiring complexity and the number of active devices required in arithmetic circuits. The number system can provide an alternative path in development of new types of arithmetic and signal processing units. Classical analog circuit blocks are used to construct the multiplier with arbitrary precision. Despite its analog nature, the CVNS theory in fact produces familiar arithmetic structures. While addition in the CVNS is digit wise, multiplication is based on the array multiplication

P FCV N S (P ) = i

(1)

The CVNS values, which are the ensemble of the CVNS digits can be written as a vector as follows: ( ,
1 , ..., 1 , 0 |1 , 2 , ..., )

(2)

where i ( i ) represents digits of the corresponding CVNS number. In order to simplify out notation, letters from the English alphabet to represent numbers in a weighted format and then you use its Greek letter to indicate that the number is now in CVNS format. The CVNS digits are obtained by a general expression applying the modulus operation: i =
p Li+1 M .B

0i<L

(3)

and digits with indices higher than L are obtained as follows: i1 0 i < 2 i>L = (4) (i1 )mod + < i 2

1424407850/06/$20.00

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+ + where |p| < M 2 and (p)mod = p + I. ; 0 (p)mod < . The CVNS digits with higher indices, have higher information density compared to the digits with lower indices. Therefore, the term Most Signicant Digit can not be applied in the same context as it is applied to conventional weighted magnitude number systems. Hence, we refer to the digits by the level of information that they contain; the digit with the highest index in the system is called the Most Informed Digit or MID in short. Some fundamentals of the CVNS addition and multiplication are given in the following section.

III. CVNS ADDITION The addition operation is performed independently on each of the CVNS digits [8]. The B-complement addition of two CVNS numbers, ( , 1 , ..., 1 , 0 |1 , 2 , ..., ) and ( , 1 , ..., 1 , 0 |1 , 2 , ..., ) is performed as follows: i = (i + i )mod+
L

In this paper, only the most informed CVNS digit is generated, and multiplied with the associated multiplicand digits. This way, the complexity of the multiplier is reduced, while the information redundancy is kept at its maximum. Therefore, general formula of CVNS multiplication is not used, instead the CVNS multiplier structure is generated considering the required partial products for binary multiplication at each row of a digital multiplication. The proposed method takes advantage of high performance CVNS adders, where CVNS digits can be represented in higher radices. The regular formula of the CVNS multiplication generates redundant terms that are needed to be removed by modulo operations for higher radices, hence becomes less efcient for radices > 2. Figure (1) shows the two multiplication scheme for a 4 4 binary multiplication. The second method is clearly more advantages in reducing the complexity. Moreover, this conguration can be implemented using similar analog units for the whole multiplier architecture, while the original CVNS multiplier block properties are not the same. Considering that the design platform is analog, this means that the second method design-time is dramatically reduced and it is more cost effective. V. P ROPOSED A RRAY M ULTIPLIER The Proposed CVNS array multiplier is structured considering the required binary partial products. In this form only the MID digit is generated, and its copies are multiplied with the multiplicand digits through ON or OFF switches. The CVNS adders use a radix-4 truncated addition method [9] with minor modication at the rst layer. In the rst layer of the CVNS multiplier, multiplicand digits act as activation signals of the CVNS adders. In the rst layer of an n n-bit multiplier, n/2 radix-4 n-bit CVNS adders are required, as shown in Figure (2). There are in total log2 (n) layers, where each layer reduces the partial products in half. For 16-bit multiplication, 4 layers are required. VI. A NALOG C IRCUITS The CVNS number representation is analog, therefore digits can take a continuous value. At the implementation level, CVNS designs can take advantage of some of the existing solutions in threshold logic. The central circuit of a CVNS adder is the modulus operation circuit, which is essentially a current comparator. In this design a differential current comparator is applied, which increases the noise immunity of the system. Generally, input to the one of the transistors of the input pair is the input current, while the other input transistor is always ON, and set to represent the threshold value. This method requires large transistors and increases the static power consumption. In our approach, the input current i is compared with its complement value i = (1 2 ) i, where = 4. This not only reduces the power requirements, but also decreases the area by eliminating the large transistors required at the input pair. Moreover, this conguration leads to better noise

=
i=0

(pi + ti )B i+2j L1

mod+

(5)

provided that the sum adheres to the condition | + | < M 2 . However, due to limitations imposed by the analog implementation medium, truncated addition is performed as follows:
L2j

=
i=z

(pi + ti )B i+3j L1 + CLj

mod+

(6)

where C j is the truncation signal which is used for removing the uncertainty form the MID digits, z = L 2j ( 1), and is a technology dependent parameter limited by the maximum reliable resolution of the implementation environment. IV. CVNS MULTIPLICATION Unlike addition, multiplication in the CVNS can not be performed digit wise. The CVNS multiplication is performed by summation of partial products. It has been shown that multiplying two values applying CVNS theory is as follows: oj = ( t)j = ti .j i
i

mod

(7)

where 0 < j L, is the representation of p in the CVNS format, and t is represented in a conventional positional number system. If the radix of the conventional number system is chosen as 2 (binary form), then t is represented in binary and each of its digits serve as an off-on switch for summing the CVNS partial products. There are, however, other methods for multiplying binary numbers using the CVNS theory. In particular regular arrays of binary partial products can be generated and reduced by series of high-radix CVNS adders.

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(a) CVNS multiplication by using Equation (7) Fig. 1.

(b) Proposed CVNS multiplication

Comparing the two CVNS multiplications method for a 4 4 multiplier

Fig. 2.

16 16 bit binary multiplication is performed by 4 layers of high radix CVNS adders.

margin and higher gate speed due to the fact that inputs have opposite transitions [10]. Moreover, to increase the symmetry of the differential pair and to reduce the mismatch effect, input signal to the differential pair is further more divided into two equal sets of signals. The input signal i is the result of adding a group of length -bit digit, which are a part of the MID digit, , and its scaled version, 2 . Originally the comparator needs to evaluate the term i = ti + 2ti1 2, to detect the existence of the carry information over a group of length

. In the new circuit, ti and (1 2 ) 2ti1 are compared using the same principal as before, however this time the differential pair has a more symmetrical structure, and each input transistor is connected to a more balanced conguration of parasitic capacitors. The maximum value of each of the signals and 2 is 2 , which means that no carry is generated within the groups, if either one of ti or ti1 signals are equal to zero. Therefore, the differential pair circuit operation becomes data dependent, with the enabling signal switch ti ti1 . The new MDAC style circuit shown

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in Figure (3), exhibits low gate delay, and its driving capability can be increased by adding high drive buffers at the output.

comparable to mature digital designs. The total area of the CVNS multiplier can be reduced even more, considering that the rst layer requires copies of the MID digit. This means that the continuous value of this digit has to be distributed in the chip area, which requires a more carefully drawn layout. In this design we generated the MID digit locally for each adder, that contributed to an overhead in area; however, the robustness of the design against noise has been increased.
TABLE I C OMPARING THE CVNS MULTIPLIER AND SEVERAL STANDARD DIGITAL MULTIPLIERS . Multiplier [11](0.25m) [1] (24-bit) [1] (24-bit) [7] [6] [2] [12] (0.13m) [3] [5] [4] CVNS Array Multiplier (0.18m) Delay (ns) 9.8 5.91 5.88 ns 4.39 4.34 3.4 4.42 3.97 3.8 3.52 3.2 Area (m2 ) 381, 238 44680 43217 126000 5980 N/A 14589 N/A N/A 36797 42137

Fig. 3. New MDAC style current comparator for detecting the carry information in a group of CVNS digit of length .

The modulo circuit, shown in Figure (4), can not take advantage of this conguration. Therefore, input current which is the equivalent analog value of the binary inputs, is compared with its complement value at the differential pair, through (M1-M7) transistors. The voltage in the secondary pair of the current comparator drops for values less than 2 and rises for values higher or equal to 2. This branch also turns ON or OFF transistor M10. Transistors M8-M14 are used for the binary output signal generation. The gate of transistor M10 is connected to the (i)mod2 branch, and biasing of M9 causes the gates of M11-M14 to go HIGH for a logic 1 and go LOW for a logic 0. Accordingly, if the (i)mod2 branch goes high, M10 is turned ON and causes a voltage drop.

VII. C ONCLUSION The CVNS number system is a novel continuous valued analog digit number representation, introduced recently for arithmetic and signal processing units. The CVNS multiplier is composed of regular array of high radix CVNS adders. The CVNS multiplier has high speed and shows relatively small layout area. The design will generate lower system noise than its CMOS logic counterparts, because of the smooth nature of the analog transitions. R EFERENCES
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Fig. 4.

Current mode modulo circuit

The CVNS multiplier is realized in the TSMC CMOS 0.18m technology, with a maximum delay of 3.2 ns, and a core area of 42137m2 . The example demonstrates that CVNS designs can yield fast, arithmetic circuits using low noise analog circuitry. For comparison purposes, performance of the analog CVNS multiplier is compared with various types of digital array multipliers, and results are shown in Table I). Comparisons between this example as the rst implemented CVNS multiplier showed that it can achieve performance

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[8] A. Saed, M. Ahmadi, and G. A. Jullien, A number system with continuous valued digits and modulo arithmetic, IEEE Trans. on Comp., vol. 51-11, pp. 12941304, NOv. 2002. [9] M. Mirhassani, M. Ahmadi, and G. A. Jullien, 16-bit radix-4 continuous valued digit adder, Proc. SPIE, Advanced Signal Processing Algorithms, Architectures, and Implementations XVI, vol. 6313-03, p. 12 pages, Aug. , 2006. [10] V. Beiu, Low-power differential conductance-based logic gate and method of operation thereof, U.S patent 6 580 296, June, 2003. [11] O. T. C. Chen, S. Wang, and Y.-W. Wu, Minimization of switching activities of partial products for designing low-power multipliers, IEEE Trans. on VLSI Systems, vol. 11, no. 3, pp. 418433, 2003. [12] J.-Y. Kang and J.-L. Gaudiot, A simple high-speed multiplier design, IEEE Trans. On Computers, vol. 55, no. 10, pp. 12531258, 2006.

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