Study of Place and Route and Back Annotation AIM : To study the place and route and back

annotation using Xilinx ISE 10.1 for a adder and subtractor circuits in verilog HDL. REQUIREMENTS: PC XILINX ISE 9.1 software

PROCEDURE: Step 1: Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Programs Xilinx ISE (9.1i). Step 2: Create a new project and Select File menu and then select New project. Step3: Specify the project name and location in pop up window and click NEXT. Step4: Select Device. Select the required family, device, package, speed grade, Synthesis tool Simulator from new project wizard pop up window. Click NEXT. Project summary will be displayed. Step 5: Click FINISH to start Project. Step6: To create new V file Right click on the device name and select NEW SOURCE Step 7: Select VERILOG MODULE in NEW SOURCE WIZARD and give suitable name for the Project. Click NEXT for the

DEFINE MODULE Window Assign required ports in this Window. Step 8: Write the Behavioral VERILOG Code in VERILOG Editor Sample code is given below for this experiment. Step 9: Check Syntax Run the Check syntax Process window synthesize check syntax , and remove errors if present Step 10: Synthesize the design using XST. Translate the design into gates and optimize it for the target architecture. This is the synthesis phase. Again for synthesizing your design, from the source window selects synthesis/Implementation from the dropdown menu. Highlight file in the Sources in Project window. To run synthesis, right-click on Synthesize, and the Run option, or double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and a. a green check !will appear next to Synthesize when it is successfully completed. b. a red cross "indicates an error was generated and c. a yellow exclamation ! mark indicates that a warning was generated. Check the synthesis report. If there are any errors correct it and rerun the synthesis. Step 11: After Synthesis, go to back annotate pin location in Implement Design and double click to start back annotation. In back annotation the tool translates and routes the logic in FPGA and generates the constraint file such that minimum delay paths are included. This helps to make the design faster. Once back annotation is completed, constraint file is generated.

Floor plan before Place and Route:

SIMULATION OUTPUT :

Floor plan after Place and Route

RESULT : Thus the place and route and back annotation was studied using adder and subtractor circuits program in verilog HDL and the timing report was analyzed.