VIT

UNIVERSITY

ECE 301 - VLSI System Design

(Fall 2011)

Verilog HDL Sequential Logic Modules - II

Prof.S.Sivanantham School of Electronics Engineering VIT University Vellore, Tamilnadu. India E-mail: ssivanantham@vit.ac.in

Objectives
After completing this lecture, you will be able to: Describe how to model counters (ripple/synchronous counters and modulo r counters) Describe how to model sequence generators Describe how to model timing generators

ECE301 VLSI System Design

FALL 2011

S.Sivanantham

Counters
Counter is a device that counts the input events such as input pulses l or clock l k pulses. l Types of counters: Asynchronous Synchronous Asynchronous y (ripple) ( pp ) counters: Binary counter (up/down counters) Synchronous counters: Binary counter (up/down counters) BCD counter (up/down counters) Gray counters (up/down counters)
ECE301 VLSI System Design FALL 2011 S.Sivanantham

Binary Ripple Counters

1 J clk qout[0] Q 1 J qout[1] 1 Q J qout[2] Q

CK K Q' 1

CK K Q' 2

CK K Q' 3

clk qout[0] qout[1] qout[2]

ECE301 VLSI System Design

FALL 2011

S.Sivanantham

Binary Ripple Counters

// a 3-bit 3 bit ripple counter module example module ripple_counter(clk, qout); input clk; output reg [2:0] qout; wire c0, c1; // the body of the 3-bit ripple counter assign c0 = qout[0], c1 = qout[1]; always @(negedge clk) qout[0] <= ~qout[0]; Try to synthesize it and see what always @(negedge c0) happens!! qout[1] <= ~qout[1]; The output cannot be observed from always l @(negedge @( d c1) 1) simulators due to lacking initial qout[2] <= ~qout[2]; values of qout. endmodule

ECE301 VLSI System Design

FALL 2011

S.Sivanantham

Binary Ripple Counters

// a 3-bit ripple counter with enable control module ripple_counter_enable(clk, pp _ _ ( enable, reset_n, _ q qout); ) input clk, enable, reset_n; output reg [2:0] qout; wire c0, c1; // the body of the 3-bit 3 bit ripple counter assign c0 = qout[0], c1 = qout[1]; always @(posedge clk or negedge reset_n) if (!reset_n) qout[0] <= 1'b0; else if (enable) qout[0] <= ~qout[0]; always @(posedge c0 or negedge reset_n) if (!reset_n) qout[1] <= 1'b0; else if (enable) qout[1] < <= ~qout[1]; qout[1]; always @(posedge c1 or negedge reset_n) if (!reset_n) qout[2] <= 1'b0; else if (enable) qout[2] <= ~qout[2]; endmodule d d l
ECE301 VLSI System Design FALL 2011 S.Sivanantham

A Binary Ripple Counter --- Using the generate Statement

// an N-bit ripple counter using generate blocks module d l ripple_counter_generate(clk, i l t t ( lk reset_n, t qout); t) parameter N = 4; // define the size of counter input clk, reset_n; output reg [N-1:0] qout; // the body of the N-bit ripple counter genvar i; generate for (i = 0; i < N; i = i + 1) begin: ripple_counter if (i == 0) // specify LSB always @(negedge clk or negedge reset_n) if (!reset_n) qout[0] <= 1'b0; else qout[0] <= ~qout[0]; else // specify the rest bits always @(negedge qout[i-1]or negedge reset_n) if (!reset_n) qout[i] <= 1'b0; else qout[i] <= ~qout[i]; end endgenerate endmodule

ECE301 VLSI System Design

FALL 2011

S.Sivanantham

A Binary Counter Example

// an n-bit binary counter with synchronous reset and enable control. module binary_counter(clk, binary counter(clk enable, enable reset, reset qout, qout cout); parameter N = 4; input clk, enable, reset; output reg [N-1:0] qout; output cout; // carry output // the body of the N-bit binary counter always y @(posedge @(p g clk) ) if (reset) qout <= {N{1b0}}; else if (enable) qout <= qout + 1; // generate carry output assign i #2 cout t = &qout; & t // Why Wh #2 is i required i d? endmodule

Q: What is the difference between using {cout, qout} <= qout + 1 and qout <= qout + 1 and assign cout = &qout?
ECE301 VLSI System Design FALL 2011 S.Sivanantham

Binary Up/Down Counters --- version 1

// an N-bit binary up/down counter with synchronous reset and enable control. module binary_up_down_counter_reset(clk, y_ p_ _ _ ( enable, reset, upcnt, p q qout, cout, bout); ) parameter N = 4; input clk, enable, reset, upcnt; output reg [N-1:0] qout; output cout, cout bout; // carry and borrow outputs // the body of N-bit up/down binary counter always @(posedge clk) if (reset) qout <= {N{1'b0}}; else if (enable) begin if (upcnt) qout <= qout + 1; else qout <= qout - 1; end // else qout < <= qout; // a redundant expression // Generate carry and borrow outputs assign #2 cout = &qout; // Why #2 is required ? assign #2 bout = |qout; endmodule d d l
ECE301 VLSI System Design FALL 2011 S.Sivanantham

Binary Up/Down Counters --- version 2

// an N-bit up/down binary counter with synchronous reset and enable control. module up_dn_bin_counter(clk, up dn bin counter(clk reset, reset eup, eup edn, edn qout, qout cout, cout bout); Parameter N = 4; // Enable up count (eup) and enable down count (edn) // cannot be set to one simultaneously. i input clk, lk reset, eup, edn; d output reg [N-1:0] qout; output cout, bout; // the body y of the N-bit binary y counter always @(posedge clk) if (reset) qout <= {N{1'b0}}; // synchronous reset else if (eup) qout <= qout + 1; else l if (edn) ( d ) qout t <= < qout t - 1; 1 assign #1 cout = (&qout)& eup; // generate carry out assign #1 bout = (~|qout)& edn; // generate borrow out endmodule

ECE301 VLSI System Design

FALL 2011

S.Sivanantham

Binary Up/Down Counters --- version 2

// an example p to illustrating g the cascade of two up/down p counters. module up_dn_bin_counter_cascaded(clk, reset,eup, edn, qout, cout, bout); parameter N = 4; input clk, reset, eup, edn; o tp t [2*N-1:0] output [2*N 1:0] qo qout; t; output cout, bout; // declare internal nets for cascading both counters wire cout1, bout1; // The body of the cascaded up/down counter up dn bin counter #(4) up_dn_cnt1 up_dn_bin_counter up dn cnt1 (clk, (clk reset,eup, reset eup edn edn, qout[3:0], qout[3:0] cout1, cout1 bout1); up_dn_bin_counter #(4) up_dn_cnt2 (clk, reset,cout1, bout1, qout[7:4], cout, bout); endmodule

ECE301 VLSI System Design

FALL 2011

S.Sivanantham

A Modulo r Binary Counter

// the body y of modulo r binary y counter with synchronous y reset and enable control. module modulo_r_counter(clk, enable, reset, qout, cout); parameter N = 4; parameter R= 10; // BCD counter inp t clk, input clk enable, enable reset; output reg [N-1:0] qout; output cout; // carry output // the body of modulo r binary counter. assign cout = (qout == R - 1); always @(posedge clk) if (reset) qout <= {N{1'b0}}; else begin if (enable) if (cout) qout <= 0; else qout <= qout + 1; end endmodule
ECE301 VLSI System Design FALL 2011 S.Sivanantham

Sequence Generators
In this lecture, we focus on the following three circuits: PR (pseudo random)-sequence generator Ring counter Johnson J h counter t
f Qn-1 D Q D Q CK Q' n-1 clk CK Q' n-2 Combinational Circuit Qn-2

Dn-1

Q1 D Q D Q CK Q' 1 CK Q' 0

Q0 z

The general paradigm of sequence generator

ECE301 VLSI System Design FALL 2011 S.Sivanantham

Primitive Polynomials
n 1, 2, 3, 4, 6, 7, 15, 22, 60 5, 11, 21, 29 10 17 10, 17, 20 20, 25 25, 28, 31, 41, 52 9 23, 47 18 8 12 13 14, 16 19, 27 f( x ) 1+x+xn 1+x2+xn 1+x3+xn 1+x4+xn 1+x5+xn 1+x7+xn 1+x2+x3+x4+xn 1+x+x4+x6+xn 1+x+x3+x4+xn 1 1+x3+x4+x5+xn 1+x+x2+x5+xn
n

n 24 26 30 32 33 34 35 36 37 38 39 40 42

f( x ) 1+x+x2+x7+xn 1+x+x2+x6+xn 1+x+x2+x23+xn 1+x+x2+x22+xn 1+x13+xn 1+x+x14+x15+xn 1+x2+xn 1+x11+xn 1+x2+x10+x12+xn 1+x+x5+x6+xn 1+x4+xn 1 1+x2+x19+x21+xn 1+x+x22+x23+xn

n 43 44, 50 45 46 48 49 51, 53 54 55 56,59 57 58

f( x ) 1+x+x5+x6+xn 1+x+x26+x27+xn 1+x+x3+x4+xn 1+x+x20+x21+xn 1+x+x27+x28+xn 1+x9+xn 1+x+x15+x16+xn 1+x+x36+x37+xn 1+x24+xn 1+x+x21+x22+xn 1+x7+xn 1 1+x19+xn

f ( x) = ai x i = a0 + a1 x + a2 x 2 + K + an x n
i =0 ECE301 VLSI System Design FALL 2011 S.Sivanantham

Maximal Length Sequence Generators

D an clk Q an-1 D Q an-2 D Q a1 D Q a0

CK n-1 Q'

CK n-2 Q'

CK 1 Q'

CK 0 Q'

(a) Standard format

D a0 clk

Q a1

Q a2

Q an-1

Q an

CK n-1 Q'

CK n-2 Q'

CK 1 Q'

CK 0 Q'

(b) Modular format

ECE301 VLSI System Design

FALL 2011

S.Sivanantham

A PR-Sequence PR Sequence Generator Example

An example of 4-bit pr-sequence generator: primitive polynomial: 1 + x + x4
qout[3] qout[2] qout[1] qout[0]

d[3]

d[2] D Q CK Q' preset D Q CK Q' clear

d[1] D Q CK Q' clear

d[0] D Q CK Q' clear

clk start

Using start to set the initial to 1000, the circuit will start from state 4b1000 after reset signal is applied.

ECE301 VLSI System Design

FALL 2011

S.Sivanantham

A PR-Sequence PR Sequence Generator Example

// an N-bit pr_sequence generator module --- in standard form module d l pr_sequence_generate t (clk, ( lk qout); t) parameter N = 4; // define the default size parameter [N:0] tap = 5'b10011; = 4b0100 for simulation only. Without input clk; th initial the i iti l value, l simulators i l t cannot t output reg [N-1:0] qout = 4b0100; calculate qout and hence we could not wire d; observe the qout values. // pseudo-random pseudo random sequence generator body assign d = ^(tap[N-1:0] & qout[N-1:0]); always @(posedge clk) qout <= {d, qout[N-1:1]}; endmodule

Q: Write an N N-bit bit pr pr_sequence sequence generator in modular form. form

ECE301 VLSI System Design FALL 2011 S.Sivanantham

A PR-Sequence PR Sequence Generator Example

// an N-bit pr_sequence generator module --- in standard form module pr_sequence_generate (clk, start, qout); parameter N = 4; 4 // define d fi the h default d f l size i parameter [N:0] tap = 5'b10011; input clk, start; output p reg g[ [N-1:0] ]q qout; ; wire d; // pseudo-random sequence generator body assign d = ^(tap[N-1:0] & qout[N-1:0]); always l @(posedge @( d clk lk or posedge d start) t t) if (start) qout <= {1'b1, {N-1{1'b0}}}; else qout <= {d, qout[N-1:1]}; endmodule

Using start to set the initial value to 4b1000, hence simulators can calculate qout and hence we could observe the qout q q values. Of course, the circuit will start from state 4b1000 after reset signal is applied.
ECE301 VLSI System Design FALL 2011 S.Sivanantham

Ring Counters
qout[0] qout[1] qout[2] qout[3] d[0] D Q CK Q' preset clk start d[1] D Q CK Q' clear d[2] D Q CK Q' clear d[3] D Q CK Q' clear

// a ring counter with initial value module ring_counter(clk, ring counter(clk start, start qout); parameter N = 4; input clk, start; output reg [0:N-1] qout; // the body of ring counter always @(posedge clk or posedge start) if (start) qout <= {1'b1,{N-1{1'b0}}}; else qout <= {qout[N {qout[N-1], 1], qout[0:N-2]}; qout[0:N 2]}; endmodule
ECE301 VLSI System Design FALL 2011 S.Sivanantham

Johnson Counters
qout[0] qout[1] qout[2] qout[3] d[0] d[1] d[2] D Q CK Q' clear d[3]

D Q CK Q' clear

D Q CK Q' clear

D Q CK Q' clear

clk start

// Johnson counter with initial value module ring_counter(clk, ring counter(clk start, start qout); parameter N = 4; // define the default size input clk, start; output reg [0:N-1] qout; // the body of Johnson counter always @(posedge clk or posedge start) if (start) qout <= {N{1'b0}}; else qout <= { {~qout[N-1], qout[N 1], qout[0:N-2]}; qout[0:N 2]}; endmodule
ECE301 VLSI System Design FALL 2011 S.Sivanantham

Timing Generators
A timing generator is a device that generates timings required i d for f specific ifi application. li i Multiphase clock signals: Ring counter Binary counter with decoder Digital g monostable circuits: Retriggerable Nonretriggerable

ECE301 VLSI System Design

FALL 2011

S.Sivanantham

A Multiphase Clock Signal

clk T0 T1 T2 T3 T4 T5 T6 T7
ECE301 VLSI System Design FALL 2011 S.Sivanantham

Multiphase Clock Generators

T0 T1 T2 T3 T4 T5 T6 T7

(a) Ring counter approach

clk D 0 CK 1 2 3 4 5 6 7

// a ring counter with initial value serve as a timing generator module ring_counter_timing_generator(clk, ring counter timing generator(clk, reset, qout); parameter n = 4; // define the counter size input clk, reset; output reg [0:n-1] qout; // the th body b d of f ring i counter t always @(posedge clk or posedge reset) if (reset) qout <= {1'b1,{n-1{1'b0}}}; qout <= {q q {qout[n-1], [ ], q qout[0:n-2]}; [ ]}; else endmodule
ECE301 VLSI System Design FALL 2011 S.Sivanantham

Multiphase Clock Generators

Binary counter with decoder approach
T7 T6 T5 T4 T3 T2 T1 T0

3-to-8 decoder A2 A1 A0

Synthesized output from SynplifyPro with n = 4 and m =2. (Program is listed on the next page.)
clk
[1:0]

CP

CK

Q2

Q1

Q0

Binary counter

enable reset

[1:0]

[1:0]

D[1:0] R

Q[1:0]

[1:0] [1:0]

decode
D[1:0] EQ[3:0]

[3:0] [3:0]

qout[3:0]

b t bcnt_out_5[1:0] t 5[1 0]

qout[3:0] bcnt_out[1:0]

ECE301 VLSI System Design

FALL 2011

S.Sivanantham

Multiphase Clock Generators

// a binary counter with decoder serve as a timing generator module d l binary_counter_timing_generator(clk, bi t ti i t ( lk reset, t enable, bl qout); t) parameter N = 8; // define the number of phases parameter M = 3; // define the bit number of binary counter input clk, reset, enable; output reg [N-1:0] qout; reg [M-1:0] bcnt_out; // the body of binary counter always @(posedge clk or posedge reset) if (reset) bcnt_out <= {M{1'b0}}; else if (enable) bcnt_out <= bcnt_out + 1; // decode the output of the binary counter always @(bcnt_out) qout = {N-1{1'b0},1'b1} << bcnt_out; endmodule

ECE301 VLSI System Design

FALL 2011

S.Sivanantham