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Simplified Reverse-Active Region Model

EE 332

DEVICES AND CIRCUITS II


Lecture 5 Bipolar Junction Transistors (3)

In reverse-active region, basecollector diode is forward-biased and base-emitter diode is reversebiased. Simplified equations are:
v I i = S exp BC C V T R v i = I exp BC E V T v I i = S exp BC B V T R
S

i i

= i RC = i E R B E

Simplified Reverse-Active Region Model


Problem: Find Q-point Given data: F = 50, R = 1 VBE =VB - VE = -9 V. Combination of R and the voltage source forward biases base-collector junction. Assumptions: Reverse-active region of operation, VBC = 0.7 V Analysis:
0.7V - (-9V) I = = 1.01mA C 8200 I 1 .01mA I = C = = 0 .505 mA B +1 2 R I = I = 0 .505 mA E B

Simplified Saturation Region Model


In saturation region, both junctions are forward-biased and transistor operates with small voltage between collector and emitter. vCESAT is saturation voltage for npn BJT.

i = I exp C S

v BE V T

S exp R 1

v BC V T i ( R i

S exp F

v BE V T i

S exp R

v BC V T

CESAT

=V

ln

1+

C + 1) i

C i F B

for i B > C

No simplified expressions exist for terminal currents other than iC + iB = iE.

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Early Effect and Early Voltage


As reverse-bias across collector-base junction increases, width of collectorbase depletion layer increases and width of base decreases (base-width modulation). In practical BJT, output characteristics have a positive slope in forwardactive region, collector current in not independent of vCE. Early effect: When output characteristics are extrapolated back to point of zero iC, curves intersect at common point vCE = -VA (Early voltage) which lies between 15 V and 150 V. v 1 + CE Simplified equations (including Early effect): =
F FO

Biasing for BJT


Goal of biasing is to establish known Q-point which in turn establishes initial operating region of transistor. In BJT, Q-point is represented by (IC, VCE) for npn transistor or (IC, VEC) for pnp transistor. Q-point controls values of diffusion capacitance, transconductance, input and output resistances. In general, during circuit analysis, we use simplified mathematical relationships derived for specified operation region and Early voltage is assumed to be infinite. The practical biasing circuits used for BJT are: Four-Resistor Bias network Two-Resistor Bias network

v i =I exp BE C S V T

v 1 + CE V A

v exp BE V T FO I S

Four-Resistor Bias Network for BJT


R R R 1 R = 1 2 CC R + R EQ R + R 1 2 1 2 V =R I +V +R I BE E E EQ EQ B V EQ =V

Four-Resistor Bias Network for BJT (contd.)


All calculated currents > 0, VBC = VBE - VCE = 0.7 - 4.32 = - 3.62 V Hence, base-collector junction is reverse-biased, assumption of forwardactive region operation is correct. R Load-line for the circuit is: V =V + F I = 12 38 , 200 I R CE CC C C C

4 = 12 ,000 I + 0 .7 + 16,000 ( + 1) I B B F 4 V - 0 .7 V I = = 2 .68A I = I = 201A B F B C 1 .23 10 6 I = ( + 1) I = 204 A E F B


V I R I E E C C R =V R + F I = 4 . 32 V CC C C F CE CC

=V

The two points needed to plot the load line are (0, 12 V) and (314 A, 0).Resulting load line is plotted on common-emitter output characteristics. IB= 2.7 A, intersection of corresponding characteristic with load line gives Qpoint.

Q-point is (250 A, 4.17 V)

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Four-Resistor Bias Network for BJT: Design Objectives

Four-Resistor Bias Network for BJT: Design Guidelines


Choose Thevenin equivalent base voltage V CC V
4 EQ V CC 2

We know that
V V I V V R BE BE for R EQ B EQ I << (V V ) = EQ BE EQ B EQ E R R E E

Select R1 to set I1 = 9IB.

This implies that IB << I2. So that I1 = I2. So base current doesnt disturb voltage divider action. Thus, Q-point is independent of base current as well as current gain. Also, VEQ is designed to be large enough that small variations in VBE assumed value of wont affect IE. Current in base voltage divider network is limited by choosing I I / 5 2 C This ensures that power dissipation in bias resistors is < 17 % of total quiescent power consumed by circuit and I2 >> IB for >50.

V R = EQ 1 9I B V V Select R2 to set I2 = 10IB. EQ R = CC 2 10 I B

RE is determined by VEQ and desired IC.

EQ I

V C

BE

RC is determined by desired VCE.

V V CE R CC E I C

Four-Resistor Bias Network for BJT: Example


Problem: Design 4-resistor bias circuit with given parameters. Given data: IC =750 A, F = 100, VCC = 15 V, VCE = 5 V Assumptions: Forward-active operation region, VBE = 0.7 V Analysis: Divide (VCC - VCE) equally between RE and RC.Thus, VE =5 V and VC =10 V
R C
E B

Two-Resistor Bias Network for BJT: Example


Problem: Find Q-point for pnp transistor in 2-resistor bias circuit with given parameters. Given data: F = 50, VCC = 9 V Assumptions: Forward-active operation region, VEB = 0.7 V Analysis: + 18 ,000 I + 1000 ( I + I ) 9 =V
B EB B C 9 =V + 18 ,000 I + 1000 ( 51 ) I EB B B I 9 V 0 .7 V = = 120 A B 69 ,000 I = 50 I = 6 . 01 mA B C EC EC = 9 1000 ( I = 2 . 18 V C +I B ) = 2 . 88 V

= CC I
= V I

V C

C = 6 . 67 k

I = 10 I = 75 A B 2 I = 9 I = 67 .5 A B 1
R = B = 84 . 4 k 1 9I B V V B = 124 k CC R = 2 10 I B V

R V

E = 6 . 60 k E +V BE = 5 .7 V

=V

V V

I = C = 7 . 5 A B F

Q-point is : (6.01 mA, 2.88 V)

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BJT Current Mirror


Collector terminal of a BJT in forwardactive region mimics behavior of a current source. Output current is independent of VCC as long as VCC > 0. Thus, BJT is in forwardactive region, since VBC =- VCC. Q1 and Q2 are assumed to be matched (with identical IS, F, R, VA,)
I REF V V BE = I + I + I = BB C 1 B1 B 2 R I =I

BJT Current Mirror (contd.)


V I V S exp BE 1 + CE 1 + 2 REF V V FO A T V 1 + CE 2 V V V A 1 + CE 2 = I =I exp BE I REF C2 S V V V 2 BE + + 1 T A V V A FO 1 + CE 2 I V O = A MR = V I 2 BE 1+ + REF V A FO

V exp BE S V T

With infinite FO and VA, mirror ratio is unity. Finite current gain and Early voltage introduce mismatch in output and reference current of mirror

BJT Current Mirror: Example


Problem: Find output current for given current mirror Given data: FO = 75, VA = 50 V Assumptions: Forward-active operation region, VBE = 0.7 V Analysis:
V V BE = 12 V 0 .7 V = 202 A = BB REF 56 k R 1 + 12 75 = 223 A = ( 202 A) I = MR. I REF O 1 + 0.7 + 2 75 50 I

BJT Current Mirror: Altering Mirror Ratio


I S =I A SO E A

where ISO is saturation current of BJT with one unit of emitter area: AE =1(A). Actual dimensions of A are technology-dependent.

Mirror ratio of BJT current mirror can be changed by changing relative sizes of emitters in the transistors. For ideal case, mirror ratio is determined only by ratio of the two emitter areas.
V 1 + CE 2 V A I = n.I REF O V 2 1 + BE + V A FO
n= A E2 A E1

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BJT Current Mirror: Output Resistance


Current source using BJT doesnt have an output current that is completely independent of terminal voltage across it, due to finite early voltage. Current source seems to have resistive component with it.
v 1+ o 1 + CE 2 V V A A io = i =I =I REF REF C2 V V 2 2 1 + BE + 1 + BE + V V A A FO FO
Ro =

Tolerances-Worst-Case Analysis: Example


Problem: Find worst-case values of IC and VCE. Given data: FO = 75 with 50% tolerance, VA = 50 V, 5 % tolerance on VCC, 10% tolerance for each resistor. V V BE Analysis: I I = EQ
C E R

To maximize IC , VEQ should be maximized, RE should be minimized and opposite for minimizing IC. Extremes of RE are: 14.4 k and 17.6 k.
V EQ =V R 1 CC R + R 1 2

vo

io

Q pt

1 =

Io V A

+V

V A I O

Ro is the small signal output resistance of the current mirror.

To maximize VEQ, VCC and R1 should be maximized, R2 should be minimized and opposite for minimizing VEQ.

Tolerances-Worst-Case Analysis: Example (contd.)


Extremes of VEQ are: 4.78 V and 3.31 V. Using these values, extremes for IC are: 283 A and 148 A.
V V V BE R I R I V R I EQ E E CE CC C C CC C C R E V V R I V +V BE CE CC C C EQ =V
RE

Tolerances-Monte Carlo Analysis


In real circuits, it is unlikely that various components will reach their extremes at the same time, instead they will have some statistical distribution. Hence worst-case analysis overestimates extremes of circuit behavior. Monte Carlo analysis, values of each circuit parameter are randomly selected from possible distributions of parameters and used to analyze the circuit. Several random parameter sets are generated, the statistical behavior of circuit is built up from analysis of many test cases.

To maximize VCE, IC and RC should be minimized, and opposite for minimizing VEQ. Extremes of VCE are: 7.06 V (forward-active region) and 0.471 V (saturated, hence calculated values for VCE and IC actually not correct).

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Tolerances-Monte Carlo Analysis: Example

End of Lecture 5

Full results of Monte Carlo analysis of 500 cases of the 4-resistor bias circuit yields mean values of 207 A and 4.06 V for IC and VCE respectively which are close to values originally estimated from nominal circuit elements. Standard deviations are 19.6 A and 0.64 V respectively.

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