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EE 332
In reverse-active region, basecollector diode is forward-biased and base-emitter diode is reversebiased. Simplified equations are:
v I i = S exp BC C V T R v i = I exp BC E V T v I i = S exp BC B V T R
S
i i
= i RC = i E R B E
i = I exp C S
v BE V T
S exp R 1
v BC V T i ( R i
S exp F
v BE V T i
S exp R
v BC V T
CESAT
=V
ln
1+
C + 1) i
C i F B
for i B > C
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v i =I exp BE C S V T
v 1 + CE V A
v exp BE V T FO I S
=V
The two points needed to plot the load line are (0, 12 V) and (314 A, 0).Resulting load line is plotted on common-emitter output characteristics. IB= 2.7 A, intersection of corresponding characteristic with load line gives Qpoint.
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We know that
V V I V V R BE BE for R EQ B EQ I << (V V ) = EQ BE EQ B EQ E R R E E
This implies that IB << I2. So that I1 = I2. So base current doesnt disturb voltage divider action. Thus, Q-point is independent of base current as well as current gain. Also, VEQ is designed to be large enough that small variations in VBE assumed value of wont affect IE. Current in base voltage divider network is limited by choosing I I / 5 2 C This ensures that power dissipation in bias resistors is < 17 % of total quiescent power consumed by circuit and I2 >> IB for >50.
EQ I
V C
BE
V V CE R CC E I C
= CC I
= V I
V C
C = 6 . 67 k
I = 10 I = 75 A B 2 I = 9 I = 67 .5 A B 1
R = B = 84 . 4 k 1 9I B V V B = 124 k CC R = 2 10 I B V
R V
E = 6 . 60 k E +V BE = 5 .7 V
=V
V V
I = C = 7 . 5 A B F
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V exp BE S V T
With infinite FO and VA, mirror ratio is unity. Finite current gain and Early voltage introduce mismatch in output and reference current of mirror
where ISO is saturation current of BJT with one unit of emitter area: AE =1(A). Actual dimensions of A are technology-dependent.
Mirror ratio of BJT current mirror can be changed by changing relative sizes of emitters in the transistors. For ideal case, mirror ratio is determined only by ratio of the two emitter areas.
V 1 + CE 2 V A I = n.I REF O V 2 1 + BE + V A FO
n= A E2 A E1
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To maximize IC , VEQ should be maximized, RE should be minimized and opposite for minimizing IC. Extremes of RE are: 14.4 k and 17.6 k.
V EQ =V R 1 CC R + R 1 2
vo
io
Q pt
1 =
Io V A
+V
V A I O
To maximize VEQ, VCC and R1 should be maximized, R2 should be minimized and opposite for minimizing VEQ.
To maximize VCE, IC and RC should be minimized, and opposite for minimizing VEQ. Extremes of VCE are: 7.06 V (forward-active region) and 0.471 V (saturated, hence calculated values for VCE and IC actually not correct).
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End of Lecture 5
Full results of Monte Carlo analysis of 500 cases of the 4-resistor bias circuit yields mean values of 207 A and 4.06 V for IC and VCE respectively which are close to values originally estimated from nominal circuit elements. Standard deviations are 19.6 A and 0.64 V respectively.
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