SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS

SCLS121B DECEMBER 1982 REVISED MAY 1997

D D D D D

Single Down/Up Count-Control Line Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Asynchronously Presettable With Load Control Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

SN54HC191 . . . J OR W PACKAGE SN74HC191 . . . D OR N PACKAGE (TOP VIEW)

B QB QA CTEN D/U QC QD GND

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

VCC A CLK RCO MAX/MIN LOAD C D

description
The HC191 are 4-bit synchronous, reversible, up/down binary counters. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (rippleclock) counters. The outputs of the four flip-flops are triggered on a low-to-high-level transition of the clock (CLK) input if the count-enable (CTEN) input is low. A high at CTEN inhibits counting. The direction of the count is determined by the level of the down/up (D/U) input. When D/U is low, the counter counts up, and when D/U is high, it counts down.

SN54HC191 . . . FK PACKAGE (TOP VIEW)

QB B NC VCC A QA CTEN NC D/U QC

4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13

CLK RCO NC MAX/MIN LOAD

NC No internal connection

These counters feature a fully independent clock circuit. Change at the control (CTEN and D/U) inputs that modifies the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter is dictated solely by the condition meeting the stable setup and hold times. These counters are fully programmable; that is, each of the outputs can be preset to either level by placing a low on the load (LOAD) input and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the level of CLK. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. Two outputs are available to perform the cascading function: ripple clock (RCO) and maximum/minimum (MAX/MIN) count. MAX/MIN produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock while the count is zero (all outputs low) counting down, or maximum (9 or 15) counting up. RCO produces a low-level output pulse under those same conditions, but only while CLK is low. The counters can be easily cascaded by feeding RCO to CTEN of the succeeding counter if parallel clocking is used, or to CLK if parallel enabling is used. MAX/MIN can be used to accomplish look ahead for high-speed operation. The SN54HC191 is characterized for operation over the full military temperature range of 55C to 125C. The SN74HC191 is characterized for operation from 40C to 85C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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QD GND NC D C

SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS

SCLS121B DECEMBER 1982 REVISED MAY 1997

logic symbol
CTEN D/U 14 11 15 1 10 9 4 5 G1 M3 [UP] CLK LOAD A B C D 1,2/1,3+ G4 C5 5D [1] [2] [4] [8] 3 2 6 7 QA QB QC QD 6,1,4 CTRDIV16 2(CT=0) Z6 3(CT=15) Z6 13 RCO 12 MAX/MIN

M2 [DOWN]

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, N, and W packages.

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SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS

SCLS121B DECEMBER 1982 REVISED MAY 1997

logic diagram (positive logic)

12 4 13 D/U CLK LOAD A 5 14 11 15 S C1 1D R 1 2 3 RCO

MAX/MIN

CTEN

QA

S C1 1D R

QB

10 6

S C1 1D R

QC

9 7

S C1 1D R

QD

Pin numbers shown are for the D, J, N, and W packages.

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SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS

SCLS121B DECEMBER 1982 REVISED MAY 1997

typical load, count, and inhibit sequence

The following sequence is illustrated below: 1. Load (preset) to binary 13 2. Count up to 14, 15 (maximum), 0, 1, and 2 3. Inhibit 4. Count down to 1, 0 (minimum), 15, 14, and 13
LOAD A B C D

Data Inputs

CLK D/U CTEN QA QB QC QD MAX/MIN RCO 13 14 15 0 1 2 2 2 1 0 15 14 13

Data Outputs

Count Up Inhibit Load

Count Down

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SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS

SCLS121B DECEMBER 1982 REVISED MAY 1997

absolute maximum ratings over operating free-air temperature range

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero.

recommended operating conditions

SN54HC191 MIN VCC VIH Supply voltage High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO tt Low-level input voltage Input voltage Output voltage Input transition (rise and fall) time VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 4.5 V VCC = 6 V 2 1.5 3.15 4.2 0 0 0 0 0 0 0 0 0.5 1.35 1.8 VCC VCC 1000 500 400 NOM 5 MAX 6 SN74HC191 MIN 2 1.5 3.15 4.2 0 0 0 0 0 0 0 0 0.5 1.35 1.8 VCC VCC 1000 500 400 ns V V V V NOM 5 MAX 6 UNIT V

TA Operating free-air temperature 55 125 40 85 C If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes.

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SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS

SCLS121B DECEMBER 1982 REVISED MAY 1997

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC 2V IOH = 20 A VOH VI = VIH or VIL IOH = 4 mA IOH = 5.2 mA IOL = 20 A VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II ICC Ci VI = VCC or 0 VI = VCC or 0, IO = 0 4.5 V 6V 4.5 V 6V 2V 4.5 V 6V 4.5 V 6V 6V 6V 2 V to 6 V 3 MIN 1.9 4.4 5.9 3.98 5.48 TA = 25C TYP MAX 1.998 4.499 5.999 4.3 5.8 0.002 0.001 0.001 0.17 0.15 0.1 0.1 0.1 0.1 0.26 0.26 100 8 10 SN54HC191 MIN 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1000 160 10 MAX SN74HC191 MIN 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1000 80 10 nA A pF V V MAX UNIT

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SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS

SCLS121B DECEMBER 1982 REVISED MAY 1997

timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC 2V fclock Clock frequency 4.5 V 6V 2V LOAD low tw Pulse duration CLK high or low 4.5 V 6V 2V 4.5 V 6V 2V Data before LOAD 4.5 V 6V 2V CTEN before CLK tsu Setup time D/U before CLK 4.5 V 6V 2V 4.5 V 6V 2V LOAD inactive before CLK 4.5 V 6V 2V Data after LOAD 4.5 V 6V 2V th Hold time CTEN after CLK 4.5 V 6V 2V D/U after CLK 4.5 V 6V TA = 25C MIN MAX 0 0 0 120 24 21 120 24 21 150 30 25 205 41 35 205 41 35 150 30 25 5 5 5 5 5 5 5 5 5 4.2 21 24 SN54HC191 MIN 0 0 0 180 36 31 180 36 31 230 46 38 306 61 53 306 61 53 225 45 38 5 5 5 5 5 5 5 5 5 MAX 2.8 14 16 SN74HC191 MIN 0 0 0 150 30 26 150 30 26 188 38 32 255 51 44 255 51 44 190 38 32 5 5 5 5 5 5 5 5 5 ns ns ns MAX 3.3 17 19 MHz UNIT

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SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS

SCLS121B DECEMBER 1982 REVISED MAY 1997

switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V fmax 4.5 V 6V 2V LOAD Any Q 4.5 V 6V 2V A, B, C, or D QA, QB, QC, or QD 4.5 V 6V 2V RCO 4.5 V 6V 2V CLK tpd d MAX/MIN Any Q 4.5 V 6V 2V 4.5 V 6V 2V RCO D/U MAX/MIN 4.5 V 6V 2V 4.5 V 6V 2V CTEN RCO 4.5 V 6V 2V tt Any 4.5 V 6V MIN 4.2 21 24 TA = 25C TYP MAX 8 42 48 130 40 33 135 36 30 58 17 14 107 31 26 123 39 32 102 29 24 86 24 20 50 15 13 38 8 6 264 53 45 240 48 41 120 24 21 192 38 32 252 50 43 228 46 38 192 38 32 132 26 23 75 15 13 SN54HC191 MIN 2.8 14 16 396 79 67 360 72 61 180 36 31 288 58 49 378 76 65 342 68 59 288 58 49 198 40 34 110 22 19 MAX SN74HC191 MIN 3.3 17 19 330 66 56 300 60 51 150 30 26 240 48 41 315 63 54 285 57 49 240 48 41 165 33 28 95 19 16 ns ns MHz MAX UNIT

operating characteristics, TA = 25C

PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS No load TYP 50 UNIT pF

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SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS

SCLS121B DECEMBER 1982 REVISED MAY 1997

PARAMETER MEASUREMENT INFORMATION

High-Level Pulse VCC 50% tw Low-Level Pulse VCC 50% 50% 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS VCC 50% tPLH Reference Input tsu Data Input 50% 10% 90% 50% th 90% VCC 50% 10% 0 V tf Out-of-Phase Output VCC 0V In-Phase Output 50% 10% tPHL 90% 50% 10% tf 90% tr tPLH 50% 10% 90% tr 50% 0V tPHL 90% VOH 50% 10% VOL tf VOH VOL 50% 0V

From Output Under Test

Test Point CL = 50 pF (see Note A)

Input

tr

VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES

VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms

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