ECE

171 Winter 2011 Homework 6 Solutions 1. [10] In the communications scheme below three data bits are transmitted along with a parity bit from the source to the destination. The data should have even parity. Design both the parity generator and parity checker functions. The parity checker should output a 1 if there is a parity error. Use the fewest gates possible. You may use inverters and 2-input AND, OR, XOR, XNOR gates.

5 points for XOR for PGB function 5 points for XOR for PCB function Partial credit if correct functions but not using XOR 2. [10] Design a 16-to-1 mux using only 4-to-1 multiplexers. 10 points for correct schematic with input labels, proper select input bits ganged together, etc.

3. [10] Design a circuit to multiply two unsigned 2-bit numbers using only 2-input AND gates and single-bit half adders.

4. [10] What function is performed by the following ALU circuit when {M,P} = {01}?

F = A + B + CI

5. [15] Analyze the following synchronous state machine to determine its functionality by obtaining the next-state equations, the PS/NS table, and the state diagram. Does the state machine have any illegal states? What is the name of the counting sequence?

Next state equations: Y1+ = D1 = Y2 Y2+ = D2 = ~Y1 PS/NS table: Y1 Y2 | Y1+ Y2+ ---------|-----------0 0 | 0 1 0 1 | 1 1 1 0 | 0 0 1 1 | 1 0

5 points for next state equations 5 points for PS/NS table 5 points for Gray code

There are no illegal states. This is Gray code. 6. [25] Assuming the flip flops in the circuit below are initialized to zeros, show the output sequence it generates.

0000 1000 1100 1110 1111 0111 0011 0001 0000 This is a Johnson counter. A Johnson counter is a type of shift or ring counter. A shift counter uses little combinational logic to create the count logic and therefore can operate at high speed.