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CHAPTER 1: PROCESSOR ARCHITECTURE Introduction: Computer technology has made incredible improvement in the past half century.

In the early part of computer evolution, there were no stored-program computer, the computational power was less and on the top of it the size of the computer was a very huge one. Today, a personal computer has more computational power, more main memory, more disk storage, smaller in size and it is available in affordable cost. This rapid rate of improvement has come both from advances in the technology used to build computers and from innovation in computer design. In this course we will mainly deal with the innovation in computer design. The task that the computer designer handles is a complex one: Determine what attributes are important for a new machine, then design a machine to maximize performance while staying within cost constraints. This task has many aspects, including instruction set design, functional organization, logic design, and implementation. Computer Architecture and Computer Organization are used to define two levels of abstractions that are used for designing or understanding a computer system. The term Computer Architecture refers to those aspects of a computer system that are visible to a programmer or those parameters that have a direct impact on the logical execution of a program. Examples of architectural attributes include the instruction set, the specification of the data, the number of bits used to represent different data types, Input/Output mechanisms, and the mechanisms used for addressing memory. The term Computer Organization refers to the functional units of a computer, their interconnection and interaction processes so as to realize the architectural specifications. Examples of organizational attributes include those hardware details that are apparent to the programmer, such as the functional units like the arithmetic and logical units, control signals, interfaces between the computer and peripherals, the instruction execution processes, clock frequency, size of physical memory etc. This course deals with the architectural elements of computers as well as the aspects of computer organization and discusses how a computer, the bare machine, is built. There is a concept of levels in computer architecture. The basic idea is that there are many levels at which a computer can be considered, from the highest level, where the user is running programs, to the lowest level, consisting of transistors and wires. Basic Computer Model A computer consists of four basic modules: o o o o Central Processing Unit(CPU) Input Unit Output Unit Memory Unit

(The von Neumann model consists of five major components:(1) i/p unit; (2) o/p unit; (3) ALU; (4)MU; (5) DCU)

A. Central Processing Unit (CPU): The job of the Central Processing Unit or the Processor is to control the operation of all the functional units of the computer to execute a program. It consists of two basic modules: The Decoder and Control Unit (DCU) that interprets the instructions of a program and emits control signals to the different functional units within the CPU and also the rest of the computer for execution of the individual instructions. The Arithmetic and Logic Unit (ALU) that performs the arithmetic and logical operations required for execution of the instructions. In addition, the CPU generally has a set of registers for temporary storage of data and to maintain the state information of the computer and the data paths that interconnect the different components of the processor. B. Input Unit: Through the Input Unit data and instructions can be fed to memory unit of the computer under the control of the CPU.Examples of input devices: Keyboard, Mouse, Track ball, Joystick, Scanner, Digitizer, hard disk, floppy disk, etc. C. Output Unit: Through the Output Unit results of the computation are provided to the user from the memory unit under the control of the CPU. Examples of output devices: Printer, CRT/LCD monitor, Plotter, hard disk, floppy disk, etc. D. Memory Unit: is used to store the data and the program fed through the input unit. The CPU processes the data as per the instructions in the program. The results produced are stored back in the memory unit to be finally transferred to the output unit. The memory can be categorized into two types: Primary / Main Memory and Secondary Memory/ Storage. The main memory unit is referred to as the Primary Memory which can be volatile (RAM) or non-volatile (ROM,PROM,EEPROM) There is another kind of storage device, apart from primary or main memory, which is known as secondary memory. Secondary memories are non volatile memory and it is used for permanent storage of data and program. Example of secondary memories: Hard Disk, Floppy Disk, Magnetic Tape ------ These are magnetic devices,CD-ROM ------ is optical device Thumb drive (or pen drive) ------ is semiconductor memory. Primary Memory Organization: The Primary Memory can be thought to be an array of data slots each capable of holding a byte of data. These slots are called memory locations. Each of these memory locations is identified by a number. This identifying number is called its address. Address 0 1 2 3 4 5 . . . N-2 N-1 . . . Memory Locations

To access any of the memory locations one has to specify the address and the operation (i.e. read or write) to be performed. There are address lines through which the address is specified. Through the command lines the operation is specified. Data lines are provided to input/output the data. In case of a write operation the data to be written is fed through the data lines. On completion of the operation the memory unit emits Memory Function Complete (MFC) signal for information of the operation initiator.

Primary Memory Unit Decoder 0 1 2 3 . . N-1 Memory Locations

Address

Data

Command MFC

The System Bus Model A refinement of the von Neumann model, the system bus model has a CPU (ALU and control), memory, and an input/output unit. Communication among components is handled by a shared pathway called the system bus, which is made up of the data bus, the address bus, and the control bus. There is also a power bus, and some architectures may also have a separate I/O bus.

Working Principle of a Computer: Before going into the details of working principle of a computer, we will analyse how computer works with the help of a small hypothetical computer. In this small computer, we do not consider about Input and Output unit. We will consider only CPU and memory module. Assume that somehow we have stored the program and data into main memory. We will see how CPU can perform the job depending on the program stored in main memory. Consider an ALU which can perform four arithmetic operations and four logical operations To distinguish between arithmetic and logical operation, we may use a signal line, 0 - in that signal, represents an arithmetic operation and 1 - in that signal, represents a logical operation.

In the similar manner, we need another 2 signal lines to distinguish between 4 arithmetic operations. The different operations and their binary code are as follows: 000 ADD 001 SUB 010 MULT 011 DIV 100 OR 101 AND 110 NAND 111 NOR Consider the CPU whose task is to generate the appropriate control signal at the right moment.There is an instruction decoder in the CPU which decodes this information in such a way that computer can perform the desired task. The simple model for the decoder may be considered as having three input lines as input to the decoder which generates eight output lines. Depending on input combination only one of the output signals will be generated and it is used to indicate the corresponding operation of ALU. In our simple model, we use 3 storage units (registers) in CPU, 2 for storing the operand & 1 for storing the results. In an computer huge memory storage is required. Some of them are inside the CPU called the registers. Other bigger junk of storage space is known as primary memory or main memory. The CPU can work with the information available in main memory only. To access the data from memory, we need two special registers one is known as Memory Data Register (MDR) and the second one is Memory Address Register (MAR). Data and program is stored in main memory. While executing a program, CPU brings instruction and data from main memory, performs the tasks as per the instruction fetch from the memory. After completion of operation, CPU stores the result back into the memory. Main Memory Organization for our hypothetical computer: A memory module of capacity 16 X 4 indicates that, there are 16 locations in the memory module each location capable of storing 4 bits of information. We need two operation to work with memory. READ Operation: This operation is to retrieve the data from memory and bring it to CPU register. WRITE Operation: This operation is to store the data to a memory location from CPU register. With the help of one signal line, we can differentiate between these two operations. If the content of this signal line is 0, we say that we will do a READ operation; and if it is 1, then it is a WRITE operation. To transfer the data from CPU to memory module and vice-versa, we need some connection. This is termed as DATA BUS. The size of the data bus indicates how many bits we can transfer at a time. Size of data bus is mainly specified by the data storage capacity of each location of memory module. To specify a particular memory location where we want to store our data or from where we want to retrieve the data we need to use the memory address. Each location can be specified with the help of a binary address. If we use 4 signal lines, we have 16 different combinations in these four lines, provided we use two signal values only (say 0 and 1).These signal lines used to identify a memory location is termed as ADDRESS BUS. Size of address bus depends on the memory size. For a memory module of capacity of 2n location, we need n address lines, that is, an address bus of size n. We use a address decoder to decode the address that are present in address bus. As for example, consider a memory module of 16 locations and each location can store 4 bit of information. The size of address bus is 4 bit and the size of the data bus is 4 bit .The size of address decoder is 4 X 16. There is a control signal named R/W. If R/W = 0, we perform a READ operation and if R/W = 1, we perform a WRITE operation If the contents of address bus is 0101 and contents of data bus is 1100 and R/W = 1, then 1100 will be written in location 5. If the contents of address bus is 1011 and R/W=0, then the contents of location 1011 will be placed in data bus. Memory Instruction: We need some more instruction to work with the computer. Apart from the instruction needed to perform tasks inside CPU, we need some more instructions for data transfer from main memory to CPU and vice versa. In our hypothetical machine, we use three signal lines to identify a particular instruction. If we want to include more instruction, we need additional signal lines.

Instruction 1000 1001 1010 1011 1100 1101 1110 1111

Code LDAI imm LDAA addr LDBI imm LDBA addr STC addr HALT NOP NOP

Meaning Load register A with data that is given in the program Load register A with data from memory location addr Load register B with data Load register B with data from memory location addr Store the value of register C in memory location addr Stop the execution No operation No operation

With an additional signal line, we can go upto 16 instructions. When the signal of this new line is 0, it will indicate the ALU operation. For signal value equal to 1, it will indicate 8 new instructions. So, we can design 8 new memory access instructions. We have added 6 new instructions. Still two codes are unused, which can be used for other purposes. We show it as NOP meaning No Operation. We have seen that for ALU operation, instruction decoder generated the signal for appropriate ALU operation. Apart from that we need many more signals for proper functioning of the computer. Therefore, we need a module, which is known as control unit, and it is a part of CPU. The control unit is responsible to generate the appropriate signal. As for example, for LDAI instruction, control unit must generate a signal which enables the register A to store data into register A. Consider a simple problem to add two numbers and store the result in memory, say we want to add 7 to 5.To solve this problem in computer, we have to write a computer program. The program is machine specific, and is related to the instruction set of the machine. For our hypothetical machine, the program is as follows: Instruction Binary HEX Memory Location LDAI 5 1000 0101 85 (0, 1) LDBI 7 1010 0111 A7 (2, 3) ADD 0000 0 (4) STC 15 1100 1111 CF (5, 6) HALT 1101 D (7)

Take another example: Say the 1st number is stored in memory location 13 and the 2nd data is stored in memory location 14. Write a program to Add the contents of memory location 13 and 14 and Store the result in memory location 15. Instruction LDAA 13 LDBA 14 Binary 1000 0101 1010 0111 HEX 85 A7 Memory Location (0, 1) (2, 3)

ADD STC 15 HALT

0000 1100 1111 1101

0 CF D

(4) (5, 6) (7)

One question still remain unanswered: How to store the program or data to main memory. Once we put the program and data in main memory, then only CPU can execute the program. We need some instructions to perform the input/output tasks. For example instructions are needed to take input from keyboard or to send the result to printer. We have seen that number of instructions that can be provided in a computer depends on the signal lines that are used to provide the instruction, which is basically the size of the storage devices of the computer. For uniformity, we use same size for all storage space, which are known as register. If we work with a 16-bit m/c, total instructions that can be implemented is 2^16.The model that we have described here is known as Von Neumann Stored Program Concept. First we have to store all the instruction of a program in main memory as CPU can work with the contents that are stored in main memory. Instructions are executed one after another. Working Principle of a Computer A computer understands a set of instructions. Any task that needs to be performed by the computer is specified in terms of the instructions within this set. This specification of the task therefore takes the form of an ordered set of instructions that is called a Computer Program or just a Program. The information to be processed and the variable parameters of the task are specified in terms of Data. The present day digital computers are based on stored-program concept introduced by Von Neumann. In this stored-program concept, programs and data are stored in separate storage unit called memories. This is the model we are going to discuss. This model (Von Neumann Stored Program Computer)was developed by Von Neumann in 1946 while building a computer at the Institute of Advanced Studies (IAS) at Princeton University. In this model of a computer the program under execution and its data are stored in the primary memory of the computer. The instructions in the program are stored in the memory unit in the order in which they are to be executed. The essential components in a processor areA register called the Program Counter (PC) or Instruction Pointer (IP) that maintains the address of the next instruction to be executed. A register called the Instruction Register (IR) that holds the instruction currently under execution. A register called the Memory Address Register (MAR) that holds the address of the memory location that is to be accessed next or currently being accessed. A register called the Memory Data Register (MDR) or Memory Buffer Register (MBR) that holds the data to be transferred to the memory unit through a memory write operation or transferred from the memory unit through a memory read operation. A Decoder and Control Unit(DCU) that decodes the instruction in the IR and emits the necessary signals to the various units within the processor as well as the memory and the input and output units for execution of the instruction at hand. An Arithmetic and Logic Unit (ALU) that performs arithmetic and logical operations on data as instructed by the DCU. A set of General purpose Registers (GPR) that are used for holding temporary data and addresses during the execution of a program. A Status Register (SR) that maintenance certain information on the current status of the program under execution as well as the processor. A register called the Stack Pointer (SP) that points to the location of operation in a data structure that works with the Last-In-First-Out (LIFO) discipline.

For execution of a program the Program Counter (PC) is loaded with the address of the first instruction of the program. The processor then follows the steps below: (i) Transfer the address in the PC to the MAR. ( MAR PC ) (ii) Increment PC to point to the next instruction in memory. (PC++) (iii) Initiate a read operation in the memory. As a result the memory transfers the content of the location specified in the MAR to the MDR . Read (iv) Transfer the content of MDR to the IR. ( IR MDR )

(v)

(vi)

The DCU decodes the instruction in the IR and accordingly issues controls signals to the various units within the processor as well as the memory, input and output units to perform the desired operation. (Execute IR) Repeat the steps 1 to 5 until a Halt instruction is encountered.

In a Register Transfer Language (RTL) the above process can be described asRepeat MAR PC PC++ Read IR MDR Execute Until IR = Halt The first four steps in the process above constitute the Instruction Fetch Cycle while the fifth step constitutes the Instruction Execution Cycle. The instruction execution cycle can be further divided into following sub cycles(i) Operand Fetch Cycle: During this the operands of the instruction are fetched into the processor from the memory unit. (ii) Execution Cycle: Perform the desired operation. (iii) Operand Store Cycle: During this cycle transfer the result(s) of the instruction to desired location. Activities during these sub cycles vary from instruction to instruction while the Instruction Fetch Cycle remains the same for every instruction. Instruction Set Architecture The operation of a CPU is determined by the instruction it executes, referred to as machine instructions or computer instructions. The collection of different instructions is referred as the instruction set of the CPU. (A) Instruction Types: (a) Data Manipulation Instructions: (i) Arithmetic: For arithmetic operations such as- Add, Subtract, Multiply, Divide etc. (ii) Logical: Logical operations such as- AND, OR, NOT, etc. (iii) Bit Manipulation: Binary operations such as- Shift, Rotate, Set, Clear etc. (iv) Compare & Test: Performing operations such as- Compare, Test etc. (b) Data Transfer Instructions: To perform frequently required data transfers from one location to another such as(i) Transfer between registers: Move etc. (ii) Transfer between memory locations: Move etc. (iii) Transfer between register and memory locations: Load, Store etc. (iv) Transfer between registers/ memory locations and Input/ Output devices: Input, Output etc. (c) Program Control Instructions: To enable implementation of non-sequential execution of instructions such as program loops, if-then-else conditional execution, subroutine/ function execution, etc. These are of two categories(i) Branch or Jump Instructions: - Unconditional Branch: Branch, Jump etc. - Conditional Branch: Branch if Equal, Branch if Greater Than etc. (ii) Subroutine Instructions: Call Subroutine, Return from Subroutine etc. B. Instruction Format: Representation of instructions as a string of bits. (a) Components of an Instruction (i) Operation - Operation Code (Opcode) (ii) Operand(s)- Addresses (iii) Next Instruction Address Opcode Opr1 Opr2 Opr3 Next Address

(b) Addressing Format Number of Operand Addresses Specified in the Instruction i. Three Address: General Purpose Register (GPR) Based Machine(m/c) - Two addresses specify the two input operands and the third address specifies the location for the result to be stored. Three GPRs can be used for this purpose.

ii. Two Address: General Purpose Register (GPR) Based m/c - Two addresses specify the two input operands. One of these addresses is also used as the location for the result to be stored. In this case one of the source operands gets overwritten. Two GPRs can be used for the two operand locations. iii. One/ Single Address: Accumulator Based m/c - Only one address is provided to specify one of the operands. The second operand location has to be implied. A special purpose register called Accumulator is used for the purpose. The accumulator is also used to store the result. GPRs GPRs

ALU

ALU

Accumulator

GPRS Based m/c iv. Zero/ No Address: Stack Based m/c

Accumulator Based m/c

- In this format the instruction does not specify any of the operand addresses. Therefore all the addresses have to be implied. The top of a stack is assumed to hold the source operands and the result is placed at the top of the stack.

Stack

ALU

Stack Based m/c Example Evaluation of Arithmetic Expressions for Different Addressing Formats: Let the expression to evaluate be: R=(A+B)*C/D-E Three address format: T1 A+B; T2 T1*C; T3 T2/D; R T3-E;

Two address format: T1 A; T1 T1+B; T1 T1*C; T1 T1/D; T1 T1-E; R T1;

Single address format: Acc A; Acc Acc+B; Acc Acc*C; Acc Acc/D; Acc Acc-E; R Acc; Zero address format: Push(A), Push(B), add, Push(C), mult, push(D), div, Push(E), sub, pop(R)

:: S A, S B, S pop()+pop(), S C, S pop()*pop(), S D, S pop()/pop(), S E, S pop()-pop(), R pop()

:: S A,S B,S S1+S2,S C,S S1*S2,S D,S S2/S1, S E,S S2-S1,R S1

(c ) Addressing Modes: how the address of an operand specified, and how the bits of an instruction organized to define the operand addresses and operation of that instruction. All computer architectures provide more than one of these addressing modes. The question arises as to how the control unit can determine which addressing mode is being used in a particular instruction. Several approaches are used. Often, different opcodes will use different addressing modes. Also, one or more bits in the instruction format can be used as a mode field. The value of the mode field determines which addressing mode is to be used. i. Immediate: The operand is specified as part of the instruction Instruction Opcode Operand

ii.

Absolute or Direct: The address of the operand in memory is specified as a part of the instruction. Instruction Opcode Address Memory

Operand

iii. Register: A register holds the operand. The register is specified in the instruction.

Instruction Opcode Register No.

GPRS

Operand

iv. Register Indirect: The operand is placed in a memory location. Its address is stored in a
register. This register is specified in the instruction. Instruction Opcode Register No. Memory

GPRs

Address

Operand

iv.

Displacement A displacement relative to the location

-Relative: The operand is placed in a memory location. of the instruction specifies in the location of the operand.

Instruction Opcode Displacement


Memory

Instruction

PC

Displacement

Operand

- Indexed: The operand is placed in a memory location. A displacement w.r.t an address given in an index register specifies the location of the operand. Instruction Opcode Index Register Displacement Memory

GPRS

Address

Operand

- Base Register: The operand is placed in a memory location. The sum of the contents of an index register and a base register gives the location of the operand.

Instruction Opcode Index Register Base Register Memory

GPRS

Base Address

+
Operand Index

Program Control Instructions: a. Branch/ Jump Instructions: i. Unconditional Branch: Branch, Jump etc. ii. Conditional Branch: Branch if Equal (BEQ), Branch if Not Equal (BNE) Branch if Greater Than (BGT) etc.

The format of a typical branch instruction isBranch Code Branch Address

In case of an unconditional branch on execution of the instruction the control of the processor is transferred to the instruction located at the branch address. This is achieved by simply modifying the PC content to the branch address, i.e. by performing the operation PC Branch Address. In case of a conditional branch instruction it is also necessary to evaluate the condition and based on its result the branch may or may not be taken. For example, say the branch instruction is required to implement an if statementif (x==y) then Statement Block1 else Statement Block2 To achieve this, the processor uses a set of Flags maintained in a Status Register (SR). Some of these flags are- Negative(N), Zero(Z), Overflow(V), Carry(C). The processor sets or resets these flags based on the result of an operation involving the ALU. If the result of an ALU operation is negative, the N bit is set, otherwise it is reset. Similarly, if the result is zero, the Z bit is set, otherwise reset. The setting or resetting of the V and C bits depend upon whether an overflow or carry occurs as a result of an ALU operation. The conditional branching is achieved through two m/c instructions. First, instruction for evaluation of the condition and setting or resetting the flag bits. Second, the conditional branch instruction for which the processor checks the relevant flag bit(s) and decides on whether to modify or not to modify the PC. The case above may be implemented as-

com x, y

; Compare x and y.

bne branch_address ; Branch if not equal to. For the com x, y instruction the processor performs a subtraction operation and sets or resets the N and Z bits as follows: x and y are equal x is greater than y x is less than y : N=0, Z=1; : N=0, Z=0; : N=1, Z=0;

Following this instruction when the bne instruction is executed, the processor checks the Z bit. If it finds the Z bit set to 1, it modifies the PC content with the branch_address, otherwise it leaves the PC unchanged. The other conditional branch instructions are executed in a similar manner. b. Subroutine: Call Subroutine, Return from Subroutine etc. The formats of a typical subroutine call and return instruction are Subroutine Call Code Subroutine Address

Return Code The return instruction does not specify any return address. This address is remembered by the processor by saving it in the processor stack while executing the subroutine call instruction. The use of the stack for saving the return address allows deep nesting of subroutines as the stack is a Last-In-First-Out (LIFO) structure.The Call Subroutine instruction performs a Push(PC) operation to save the current PC in the Stack and then modify the PC to point to the called subroutine.The Return instruction placed at the end of a subroutine performs a Pop operation to restore the last PC saved in the Stack.The resulting effect in case of a set of nested subroutines is as depicted in figure below: Main ------------------------------Call Sub1 P1 --------------------P2 ----------------------------------------Return ----------Return ----------Return ----------Return

Sub1
------------------------------Call Sub2 ----------P3

Sub2
------------------------------Call Sub3 ----------P4

Sub3
------------------------------Call Sub4 -----------

Sub4
--------------------------------------------------

Nested of Subroutines

P4 P3 P2 P1 At Main At Sub1 P1 At Sub2 P2 P1 At Sub3 P3 P2 P1 At Sub4

Content of the Stack at different stages of nesting of the Subroutines above. In practice, the processor also saves the Status Register (SR) content along with the PC on execution of a Call Subroutine instruction and restores it while executing the Return instruction. This is done to ensure that the status of the processor within a program segment is not affected by the execution of a Subroutine. Instruction Set Design One of the most interesting, and most analyzed, aspects of computer design is instruction set design. The instruction set defines the functions performed by the CPU. The instruction set is the programmer's means of controlling the CPU. Thus programmer requirements must be considered in designing the instruction set. Most important and fundamental design issues: a. Operation repertoire : How many and which operations to provide,& how complex operations should be. b. Data Types : The various type of data upon which operations are performed. c. Instruction format : Instruction length (in bits), number of addresses, size of various fields and so on. d. Registers : Number of CPU registers that can be referenced by instructions and their use. e. Addressing : The mode or modes by which the address of an operand is specified. ***Study the PDP-11 Instruction Set (on your own)*** PDP-11 instruction set The instruction set of the PDP-11 was designed towards a clean, general, symmetric instruction set. It can be used as a register-based, stack-based, or memory-based machine, depending on the programmer's preferences. Word length is 16 bits with the leftmost, most significant bit (MSB) being bit 15. There are eight general registers of 16 bits each. Register 7 is the program counter (PC) and Register 6 is the stack pointer (SP). There is also a Processor Status Register/Word (PSW) which indicates the 4 condition code bits (N, Z, V, C), the Trace Trap bit, processor interrupt priority, and 4 bits for current and previous operating modes. Addressing on the PDP-11 is linear from memory address 0 through 177777(octal). Memory management allows access to physical memory with addresses of up to 22 bits (17777777). All I/O devices, registers etc are addressed as if they were part of memory. These are in the 4KW of reserved memory space at the top of the address space. All word memory addresses are even. In byte operations, an even address specifies the least-significant byte and an odd address specifies the most-significant byte. Specifying an odd byte in a word operation will return an odd address trap. Memory addresses from 0 to 400 octal are reserved for various exception traps such as timeouts, reserved instructions, parity, etc., and device interrupts. Addressing for the Single Operand, Double Operand and Jump instructions is achieved via six bits: ______ |m|m|m|r|r|r| |Mode |Reg |where the modes are as follows: (Reg = Register, Def = Deferred)

Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7

Reg Rn Direct addressing register contains the operand Reg Def (Rn) Content of Reg is the address of the operand AutoIncr (Rn)+ Content of Reg is the address, then Reg incremented AutoIncrDef @(Rn)+ Content of Reg is addr of addr, then Reg Incremented AutoDecr -(Rn) Reg is decremented then content is used as address AutoDecrDef @-(Rn) Reg is decremented then content is used as addr of addr Index X(Rn) Content of Reg + Following word is address IndexDef @X(Rn) Content of Reg + Following word is addr of addr

Note that the right-most bit of the mode is an indirection bit. Although not special cases, when dealing with R7 (the PC), some of these modes are called different things: ______ |m|m|m|1|1|1| |Mode | R7 | Mode 2 Mode 3 Mode 6 Mode 7 Immediate Operand follows the instruction Absolute Address of Operand follows the instruction Relative Instr address+4+Next word is Address RelativeDef Instr address+4+Next word is Address of address

Mainstream instructions are broken into Single operand and Double operand instructions, which in turn can be word or byte instructions. Double Operand Instructions ________________ |b i i i|s s s|s s s|d d d|d d d| | Op | Source | Dest | Bit 15, b, generally selects between word-sized (b=0) and byte-sized (b=1) operands. In the table below, the mnemonics and names are given in the order b=0/b=1. The double operand instructions are: b 000 ssssss dddddd Non-double-operand instructions. b 001 ssssss dddddd -- MOV/MOVB Move Word/Byte Moves a value from source to destination. b 010 ssssss dddddd -- CMP/CMPB Compare Word/Byte Compares values by subtracting the destination from the source, setting the condition codes, and then discarding the result of the subtraction. b 011 ssssss dddddd -- BIT/BITB Bit Test Word/Byte Performs a bit-wise AND of the source and the destination, sets the condition codes, and then discards the result of the AND. b 100 ssssss dddddd -- BIC/BICB Bit Clear Word/Byte

For each bit set in the source, that bit is cleared in the destination. This is accomplished by taking the onescomplement of the source and ANDing it with the destination. The result of the AND is stored in the destination. b 101 ssssss dddddd -- BIS/BISB Bit Set Word/Byte For each bit set in the source, that bit is set in the destination. This is accomplished by ORing the source and destination, and storing the result in the destination. b 110 ssssss dddddd -- ADD/SUB Add/Subtract Word Adds the source and destination, storing the results in the destination. Subtracts the source from the destination, storing the results in the destination. Note that this is a special case for b=1, in that it does not indicate that byte-wide operands are used. b 111 xxxxxx xxxxxx Arithmetic functions not supported by all implementations of the PDP-11 architecture. Single Operand Instructions ________________ |b|0 0 0|i i i i i |d d d d d d| |Instruction| Dest | | | Bit 15, b, generally selects between word-sized (b=0) and byte-sized (b=1) operands. In the table below, the mnemonics and names are given in the order b=0/b=1. Unless otherwise stated, the operand is read for the data to operate on, and the result is then written over that data. The single operand instructions are: b 000 000 011 dddddd -- SWAB/BPL Swap Bytes/Branch Plus Swap bytes exchanges the two bytes found in the destination, writing the result back to it.

The branch (b=1) is described in the section on branches, below. Note that SWAB is actually a bit pattern from the range reserved for branches. This particular pattern is otherwise unused, as it would be a modification of BR, Branch Always, which has no obvious semantics. b 000 101 000 dddddd -- CLR/CLRB Clear Word/Byte Sets all the bits in destination to zero. b 000 101 001 dddddd -- COM/COMB Complement Word/Byte Calculates the ones-complement of the operand, and stores it. The ones-complement is formed by inverting each bit (0->1, 1->0) independently. b 000 010 010 dddddd -- INC/INCB Increment Word/Byte Adds one to the destination. b 000 101 011 dddddd -- DEC/DECB Decrement Word/Byte

Subtracts one from the destination. b 000 101 100 dddddd -- NEG/NEGB Negate Word/Byte Calculates the twos-complement of the operand, and stores it. The twos-complement is formed by adding one to the ones-complement. The effect is the same as subtracting the operand from zero. b 000 101 101 dddddd -- ADC/ADCB Add Carry Word/Byte Adds the current value of the carry flag to the destination. This is useful for implementing arithmetic subroutines with more than word-sized operands. b 000 101 110 dddddd -- SBC/SBCB Subtract Carry Word/Byte Subtracts the current value of the carry flag from the destination. This is useful for implementing arithmetic subroutines with more than word-sized operands. b 000 101 111 dddddd -- TST/TSTB Test Word/Byte Sets the N (negative) and Z (zero) condition codes based on the value of the operand. b 000 110 000 dddddd -- ROR/RORB Rotate Right Word/Byte Rotates the bits of the operand one position to the right. The right-most bit is placed in the carry flag, and the carry flag is copied to the left-most bit (bit 15) of the operand. b 000 110 001 dddddd -- ROL/ROLB Rotate Left Word/Byte Rotates the bits of the operand one position to the left. The left-most bit is placed in the carry flag, and the carry flag is copied to the right-most bit (bit 0) of the operand. b 000 110 010 dddddd -- ASR/ASRB Arithmetic Shift Right Word/Byte Shifts the bits of the operand one position to the right. The left-most bit is duplicated. The effect is to perform a signed division by 2. b 000 110 011 dddddd -- ASL/ASLB Arithmetic Shift Left Word/Byte Shifts the bits of the operand one position to the left. The right-most bit is set to zero. The effect is to perform a signed multiplication by 2. b 000 110 100 dddddd -- MARK/MTPS Mark/Move To Processor Status Mark is used as part of one of the subroutine call/ return sequences. The operand is the number of parameters. MTPS is only on LSI-11s, and is used to move a byte to the processor status word. This is needed because the LSI-11 does not support accessing registers via memory addresses. b 000 110 101 dddddd -- MFPI/MFPD Move From Prev. Instruction/Data Pushes a word onto the current R6 stack from the operand address in the previous address space, as indicated in the PSW. On PDP-11s that do not support separate instruction and data spaces, MFPD is treated the same as MFPI. b 000 110 110 dddddd -- MTPI/MTPD Move To Previous Instruction/Data

Pops a word from the current stack as indicated in the PSW to the operand address in the previous address space, as indicated in the PSW. On PDP-11s that do not support separate instruction and data spaces, MTPD is treated the same as MTPI. b 000 110 111 dddddd -- SXT/MFPS Sign Extend/Move From Processor Status SXT sets the destination to zero if the N (negative) flag is clear, or to all ones if N is set. This is useful for implementing arithmetic subroutines with more than word-sized operands. MFPS copies the processor status byte to the indicated register. This only exists on LSI-11s, and is needed there because those systems don't support accessing registers via memory addresses. Branches _______________ |b|0|0|0|b|b|b|b|d|d|d|d|d|d|d|d| |Branch Code | Destination| The destination of a branch is +127 to -128 words from the word following the branch instruction itself. This seems slightly odd, until you realize the sequence of events: the branch instruction is read from memory and the PC incremented. If the branch is to be taken, the offset is then added to the current value of the PC. Since the PC has already been incremented, the offset is thus relative to the following word. Note that all branch instructions are one word long. The various branches test the values of specific condition codes, and if the tests succeed, the branch is taken. The condition codes are N (negative), Z (zero), C (carry), and V (overflow). In the table below, the branch tests are shown as boolean expressions. `x' stands for exclusive-OR. `v' stands for inclusive-OR. 0 000 000 1dd dddddd BR: Branch Always 0 000 001 0dd dddddd BNE: Branch if Not Equal (Z==0) 0 000 001 1dd dddddd BEQ: Branch if EQual (Z==1) 0 000 010 0dd dddddd BGE: Branch if Greater or Equal (NxV == 0) 0 000 010 1dd dddddd BLT: Branch if Less Than (NxV == 1) 0 000 011 0dd dddddd BGT: Branch if Greater Than (Zv(NxV) == 0) 0 000 011 1dd dddddd BLE: Branch if Less or Equal (Zv(NxV) == 1) 1 000 000 0dd dddddd BPL: Branch if PLus (N == 0)

1 000 000 1dd dddddd BMI: Branch if MInus (N == 1) 1 000 001 0dd dddddd BHI: Branch if HIgher (C==0 and Z==0) 1 000 001 1dd dddddd BLOS: Branch if Lower Or Same (CvZ == 1) 1 000 010 0dd dddddd BVC: Branch if oVerflow Clear (V == 0) 1 000 010 1dd dddddd BVS: Branch if oVerflow set (V == 1) 1 000 011 0dd dddddd BCC: Branch if Carry Clear (C == 0) also known as BHIS: Branch if Higher Or Same 1 000 011 1dd dddddd BCS: Branch if Carry Set (C == 1) also known as BLO: Branch if Lower Condition Code Operations ________________ |0|0|0|0|0|0|0|0|1|0|1| s |N|Z|V|C| | Opcode | | Mask | General opcode 000240x. Set/Clear corresponding bits depending on sense of bit 04 (set=1, clear=0). Codes 240 and 260 set/clear no bits and are, thus, used as NOP. Although specific mnemonic are provided for each flag and all flags, any combination may actually be set or cleared at a time. General mnemonics are: CLx SEx CCC SCC Clear x, where x is N, Z, V, or C Set x, where x is N, Z, V, or C Clear all condition codes Set all condition codes

0 000 000 010 1s0 000 NOP/NOP: No Operation 0 000 000 010 1s0 001 SEC/CLC: Set/Clear Carry

0 000 000 010 1s0 010 SEV/CLV: Set/Clear Overflow 0 000 000 010 1s0 100 SEZ/CLZ: Set/Clear Zero 0 000 000 010 1s1 000 SEN/CLN: Set/Clear Negative 0 000 000 010 1s1 111 SCC/CCC: Set/Clear All Condition Codes Other, Miscellaneous ________________ |0|0|0|0|1|0|0|L|L|L| d|d|d|d|d|d | | Opcode |Link_|Destination|

0 000 100 sss dddddd -- JSR Jump to Subroutine The actual sequence of steps taken is: MOV <Link>,-(R6) MOV PC,<Link> JMP <destination> Thus, it loads the calling address into the specified link register (after saving the original contents). It then jumps to the destination. The fun part is (as usual with the PDP-11) that the PC is a general register, and the description above is the result when the PC is used as the source. ________________ |0|0|0|0|0|0|0|0|1|0|0|0|0|L|L|L| Opcode |Link_| |

0 000 000 010 000 sss -- RTS ReTurn from Subroutine Undoes the effects of a JSR. For predictable results, it is suggested that the same register should be used as was named in the corresponding JSR instruction. The actual operations involved are: MOV <Link>,PC MOV (R6)+,<Link> This is the reverse of JSR. Obviously, the finesse here too is that you can use the PC, to get what people normally consider a CALL/RETURN function. Why is it done like this then? Well, consider this example: ... JSR R0,FOO .WORD A .WORD B

MOV R1,C ... FOO: MOV @(R0)+,R1 ADD @(R0)+,R1 RTS R0

This type of parameter passing is used extensively in the PDP-8 and PDP-10), for example. Also, the FORTRAN runtime system on the PDP-11 do it this way. (It is fairly easy to write a compiler that generates such a calling sequence, and then have a library of functions which expect this calling convention.) ________________ |0|0|0|0|0|0|0|0|0|1| d| d|d|d|d|d | Opcode |Destination| |

0 000 000 001 ddd ddd -- JMP JuMP Loads the destination address into the PC, thus effecting an unconditional jump. Note that a trap will occur on some systems if an odd address is specified. On others, the destination is silently rounded down to the next-lower even address (i.e., the right-most bit is ignored). ________________ | 0|0|0|0|0|0|0|0|0|0|0|0|0 | i| i| i| | | | | | | Op |

0 000 000 000 000 000 -- HALT Halts the machine Ceases I/O, and gives control to the console. Operator intervention is required to continue or restart the system. 0 000 000 000 000 001 -- WAIT WAIT for interrupt 0 000 000 000 000 010 -- RTI ReTurn from Interrupt 0 000 000 000 000 100 -- BPT BreakPoint Trap 0 000 000 000 000 101 -- RESET Initializes the system The following opcode ranges are all unused: 00 00 07 .. 00 00 77 00 02 10 .. 00 02 27 00 70 00 .. 00 77 77 07 50 40 .. 07 67 77 10 64 00 .. 10 64 77 10 67 00 .. 10 77 77 Other arithmetic and floating point instructions were added to the basic set over the years, but those listed above form the core PDP-11 instruction set.