T

Simplifying Sequential Circuit Test Generation

MENG-LIEH SHEU SEQUENTIAL TEST generation

poses a difficult problem for circuits implemented from finite-state machines. The flip-flopsin sequential circuitssynthesizedfrom FSMs generally have intricate cyclic structures that complicate sequential test generation. We have developed a parity checker design-fortestabilityscheme that significantly enhances circuit testability, thus simplifying the testability problem. Years ago, Hennie proposed a checking experiment to test FSMs by deriving distinguish sequences that can differentiate good machines from faulty ones. The very long test sequence involved, plus the near impossibility o f deriving the distinguish sequence sometimes makes this approach impractical. To shorten the derived checking sequence, Fujiwara et aL2 proposed making machines output-observableby adding a number o f extra outputs. This method reduces the length of the checking sequence for the modified machine nearly to a minimum. For practical circuit designs, manufacturers commonly use scan designs3 to facilitatesequential circuit testing.To
28

CHUNG LEN LEE National Chiao Tung University

the large hardware overhead and shorten the test sequence, several factors argue against their use.

. . .
J
enhance circuit controllability and observability, full scan designs chain all the storage elements into a shift register. Such designs, though, involve relatively large hardware overhead and long test sequences. Partial scan designs, by contrast, select only a subset o f flip-flopsfor scanning. Though they significantlyreduce
0740-7475/94/$04.000 1994 IEEE

Sequential test generation is inevitable for the nonscanned flip-flops. All scan designs may degrade performancedue to the extra delay introduced in the scan path. Additional input/output pins are necessary for the scan data I/O and scan clock control. The scan mode cannot operate at the speed o f the circuit during normal operation.

Researchers have developed many efficient sequential test generation algorithms to generate test sequences for FSM circuits based on the stuck-at-faultmodel. Due to the heavy computation involved, these can generate test sequences only for moderately large circuits. Recently, Cheng et aL4proposed a functional test generation method for FSMs based on their single-statetransition fault model. The derived functional
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Useful definitions
Design for testability Distinguish sequence Distinguish table FSM Finite state machine FTG Functional test generation PCDFT Parity checker DFT SPDS Statepair distinguishing sequence SSPDS Shortest SPDS SST Singlestate transition
__

DFT DS DT

test sequences have high stuck-at fault coverages, demonstrating the effective ness o f this functional fault model. One solution for this testing problem is to design (orsynthesize) the circuit of an FSM in a testable way. For example, Devadas et a1.5proposed a procedure to synthesize highly testable FSMs that eliminates sequential redundancies o f an FSM. Agrawal et aL6devised a general architecture of testable design for FSMs in which the FSM function merges with a test function during circuit synthesization. The same group also developed a state assignment procedure for synthesizing testable designs that produces highly testable designs by r e ducing the cyclic structure of the flip flops. Saucier et a1.8developed a method to synthesize concurrently checked controllers. It employs an embedded signature monitoring approach and signature justification method to verify signatures o f the paths of a selfchecking FSM. Recently, Fujiwara et a1.9proposed a parity scan design to shorten the test application time. In their approach,the circuit is fully scanned and treated as a combinational circuit during testing. To eliminate the scan-out sequence of paritytestable faults, an added parity checker checks all flipflops. Our new parity checker DIT scheme for F S M s O uses a parity checker to monitor state changes after FSMs have made
FALL 19911

state transitions to detect state transition faults. For the circuit, which still works as a sequential circuit duringtesting,the of A and B parity checker directlyobserves the fault effect appearing at the state lines. This (3) eliminates any propagation or scan-out sequence. Our approach significantly Even Odd Even Odd Even enhances circuit testability, making the testing problem much simpler. Before proceeding to the parity checkof A and B er DFTscheme for FSMs, readers should acquaint themselves with several definitions of distinguishabilityand theorems for distinguishable machines that we ad- Figure 1. Three cases that can cause the dress in the accompanying box on the fault effect to disappear (a),and ways to next page. eliminate fault-effectdisappearance lbj.

Parity checker DFT scheme For an FSM to detect an SST fault, we need an input sequence that will prop agate the fault effect of the faulty state pair to primary outputs. During the fault effect propagation, three possible cases can cause the fault effect to disappear such that the primaly outputs cannot observe the fault effect:

The fauliy state pairs are equivalent (case I j, partially equivalent (case 2), and form U loop (case 3).

Flip

1. The faulty state pair is equivalent. 2. The faulty state pair is partially checker equivalent. 3. The faulty state pair forms a loop, Figure 2. The parity checker DFJ scheme as shown in Figure la, where A, B eliminates the propagation or scan-out are two states of a faulty state pair. sequence required by other schemes.

In Figure la, for the first case,statesA and B transit to the same next states,giv- be fully or partially equivalent.The case ing the same outputs under any input. having more states in such a loop preThey are equivalent.This is the equiva- sents the same situation as the third lent sequential redundancy reported by case. We propose a new D R scheme to Devada, Ma, and Newton. For the second case, statesA and B further eliminate the propagation or transit to the same next state Cwith the scan-out sequence that other schemes same output 0 under certain input I. require. In our scheme, as shown in They are partially equivalent. In this Figure 2, we attach a parity checker to case, if the input I is accidentally c h e the state lines to monitor the fault efsen as the propagation sequence, the fects appearingat the flip-flops. fault effect will disappear. Basically, we assign the states of the f a particular parity. For the third case, states A, B, and C FSM with codes o transit to each other to form a loop with The parity checker checks the parity of the same output 0 under the same in- the flipflops that code the states of the put I. In this case,statesA, B, and Cmay machine. Whenever an SST fault oc29

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Figure 3. The parity checker DFT scheme

with concurrent error detection. Adding one flip-flop and its associated logic t o preserve the parity of the states will extend our approach to a concurrent error detection design.
30

curs, a faulty state pair arises, and the faulty state demonstrates an opposite parity that the parity-checker detects. Hence, by assigning different parities to states of the state pair as shown in Figure 1b, our Dm scheme can avoid all three cases of state undistinguishness just described. For case 1 of Figure 1b, we assign different parity to states A and B, as they have the largest undistinguishability. The parity checker will directly detect the fault effect of the equivalent faulty state pair, thus rendering the propagation or scan-out sequence unnecessaly. The same exercise can also apply to state pairs of cases 2 and 3. After as-

signing different parities,the equivalent, partially equivalent or loop states become totally distinguishable.The parity checker can immediately detect all fault effects propagated to the state lines, making the test sequence to detect faults shorter and removing some sequentialredundant faults. Test generation for circuitssynthesized according to this scheme becomes very simple. With one more flip-flop and its associated logic for preserving the parity of the states (see the shaded portion of Figure 3), this scheme not only helps detect the faults of an FSM during testing. It can also serve as a scheme for the
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Definitions and theorems continued

faulty transition for the fault and generate tota a faultystate pair. Since the machine is ic A distinguishable, the propagation se- l y quence of any faulty state pair is no Ion than K. The maximum length fort

o f SST faults is M(N-I mum length for the in

comes 2NM(N-l).
Definition 6. If the two stat

r what applied input se are a totally distinguishable

I

nition 7. A state S,,, of an uishable state if

fault-tolerantdesign of an F S M for concurrent error detection.In such a case, the output of the parity checker (labeled TO) serves as an error indicator o f transient faults appearing at flip-flops during normal operation. To reflect the testability o f an FSM, we use the value icand the number o fP distinguishable states as parameters. For a Pdistinguishable F S M described by a state transition graph, we can also derive the number xas well as the number o f the K-distinguishablestates. The larger the value o f xand the number o f Kdistinguishablestates,the longer a test sequence must be to test this machine. Also, the more difficult this test seFALL 1994

quence will be to generate. We want, therefore, to design a machine having only totally distinguishable states. Such a machine makes test generation very easy and greatly shortens the obtained test sequence. The value K and the number o f Kdistinguishable states are generally greater than one for an FSM. To reduce ic-to make a machine totally distinguishable-our scheme uses a parity checker to design the F S M and makes all SST faults having a lower level o f testability to be observed immediately at the output o f the parity checker by assigningdifferentstate parity to the SST faults.

Sate parity assignment The testability feature o f our approach rests on the fact that different parities on the states o f the FSM will occur as the machine becomes faulty. By checking the parity, our scheme can differentiate the faulty state pair. However, for an FSM, seldom will all states or state pairs be totally distinguishable. In our proposed DFTscheme,we have developed a state assignment procedure that assignsstate pairs o f the F S M to maximize the number o f totally distinguishablestates. To better understand the state parity assignment procedure, lets look at the example of F S M M2.4 Figure 4 (next page) shows the state transition table
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0/1

UnDisty(M2) = 2.8

D,$$Fi 7-l vrl

E 3

A UnDisty(S)= 2.4

B 2.8

C 3.4

D 2.6

E 2.6

F 3

Figure 4. A sample FSM M 2 : state transition table (a),state transition graph

(b).

[B,Cl; [E,Fl; [A,Dl; [ A A , [C,Dl, [D,El; ...

(4
Figure 5. The distinguish table constructed from the state transition table o f M 2 : the
distinguish table (a),undistinguishability table (b), and the order list (c).

and the associated state transition graph of M2.At first, we construct a distinguish table (DT), as shown in Figure 5a, from the state transition table.The distinguish table compilesthe distinguishabilityof each state. For this E M , states B and E are totally distinguishable because they transit to different states with different outputs under any input. Also, states C and E are totally distinguishable. Hence, in the distinguish table, we mark the table entries of state pairs [B,E] and [C,E] with an X. States B and C transit to the same next state D with

same output 1 under input 1, but transit to statesA and E with output 0 under input 0. States B and C thus are partially equivalent, or may be equivalent if statesA and E are equivalent.We mark the table entry of state pair [ B , q with an asterisk and an [A,E]. StatesA and B transit to different next states and have different outputs under input 0 but the same output,that is 1, under input 1. We also mark the table entry of state pair [A&] with [D,E], which are the next

states of states A and B under input 1. The accompanying Procedure for Building a distinguish table box shows the procedure we derive to construct the distinguish table from the state transition table for an FSM. In constructingthe distinguish table, the procedure also calculatesundistinguishability to reflect the distinguishability. For an F S M F with Nstates and each state with L outgoing edges, we define the undistinguishabilityof a state pair and a state as follows: For a state pair [S,,S,], its undistinguishability is UnDisty( [S,S,]) = Number of next state pair in [S,,S,] entry + number of [SJ,] in distinguish table + K, where K =pN, if SIand S, have p partially equivalent transitions,where 1 I p 5 L; K = 0,othenvise. For a state SI,its undistinguishability is UnDisty(S,)=

( N - 1 ) /=l,/t1
With the above definitions,we construct an undistinguishabilitytable of state pairs for the example F S M as shown in Figure 5b. For example, UnDisty([A,D]) = 2+1+1 = 4, because there are two next state pairs in the [AD] entry,and [A,D] appears once as the next state pair in the [B,D] and
32
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D E F
A B C D E

Figure 6 .The modified distinguish table of example M2. A//state pairs are tota//y
distinguishable except [A,C], and this machine becomes a I -distinguishable machines, with an undistinguishability that approaches 0.

[ C,D] entries. Since there is one * in the [ B , q entry, UnDisty([B,C])= 6+1+1+1 = 9. Figure 5b also shows the undistinguishability of every state. For state C, UnDisty(Q = (2+9+3+1+2)/5 =3.4.Here, we can define the undistinguishability o f an FSM as

UnDisty(F) = -cUnDisty(S,) N l=l. The undistinguishability o f an FSM can serve as a testabilitymeasure for the machine. The larger the undistinguishability for a machine,the harder the test generation will be. For the example FSM shown in Figures 4 and 5, this value is UnDisty(M2) = (2.4+2.8+3.4+2.6 +2.6+3)/6= 2.8. With the undistinguishability value computed foreach state pair, we derive an order list o f state pairs for the state parity assignment. Figure 5c shows such a
FALL 1994

l n

stateSA, C, and Fare assigned even parity codes;statesB, D, and E are assigned odd parity codes. Since A and B have different parity, the machine can differentiate them at the next clock. An X marked on the [A,B] entry indicates that it is a totally distinguishable state , [A,E], pair. Also, the state pairs [A,D] [B,C], ... are totally distinguishable. The state pair [A,F]has two next state pairs, [B,c] and [C,E],that are both tolist derived from Figure 5b. In the list,the tally distinguishable. State pair [A,F] state pair [B,C]should get assigned to a then is totally distinguishable after one different parity first because it has the clock. Hence, in the figure, all state highest undistinguishability value. Pair pairs are totally distinguishable except [E,F] should come next, and so forth. [A,C]. This machine becomes a 1For parity assignment, as an even or distinguishable machine,with an undisodd parity is assigned to one state o f a tinguishability approaching 0. The state pair, the scheme assigns the op- machine can record state pair [A,C] for posite parity to the otherstate o f the pair. the later test generation. With this assignment made, the states o f this state pair-originally having high Test generation undistinguishability-become totally Adding the parity checker and adoptdistinguishable. Those state pairs that ing the state parity assignment greatly are not totally distinguishable will also simplifies test generation o f FSMs. We become much less k-distinguishable. have developed two methods for genGenerally,we can easily generate the erating test sequences with 100%fault test sequence o f those k-distinguishable coverage for different fault models. A state pairs. The State parity assignment functionaltest generation method apbox describes the procedure used to plied before synthesis o f FSMs works for assign state parity for an FSM. the singlestate transition fault model. A Figure 6 shows the new distinguish deterministic test generation method table after completion o f the parity as- applied after the circuit implementation signment for the example. In the figure, works for the single stuck-atfault model.
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sitions o f states A and C is a constraint during test generation. Since [D,E] is totally distinguishable Table I. after one additional clock, making any additional transition after the conM2a M2b strained transitions will remove the conTest straints. Since the state transition graph is a n eulerian, one stroke will generate 7 0 28 the test sequence, as Figure 7 shows. 29 Figure 7. Functional test generation of 0 44 Here, the reset state is A. After traversing 42 example M2. 0 57 the states, the derived test sequence is 0 49 63 0000110101110 and the final state is C. 1 49 70 For comparison, we performed two 1 60 Table 1. Two state assignments for M2. 76 implementations of different state as80 68 0 M2 a Parity b signments with the M2 machine we 85 80 1 have used as an example. Table 1 p r e 85 0 90 92 85 sents the results. For the M2a impleA 000 Even 000 1 mentation, we adopted the stateparity 1 B 010 Odd 96 85 010 assignment, and for the M2b impleC 110 Even 001 98 87 1 mentation, we assigned the states 91 99 D 100 Odd 100 0 without considering parity. We then E 001 Odd 011 synthesized these two assignments into F 101 Even 101 For the state transition graph, direct- logic circuits with the aid o f MisII.I2We ed edges (state transitions) are like one- then applied the test sequence generway streets, and the vertices (states) are ated in Figure 7 to these two logic cirFunctional test generation. As we like crossingstreets, with the constraint cuits to detect stuck-at faults. From theorem 2, for the M2a implediscussed earlier, after state parities are that some edges must be consecutiveassigned, the machine becomes a min- ly traversed at least once. For a totally mentation, the SST fault coverage is imal Kdistinguishable device. For a K- distinguishable machine, the constraint guaranteed to be 100%.Table 2 shows distinguishable FSM to detect all SST disappears. In this special case, the the fault coverage o f stuck-at fault verfaults, the test generation problem ba- functional test generation resembles the sus the test sequence applied for these sically is a postman traveling problemI7 checking experiments Fujiwara and two implementations. Clearly, the fault with a constraint that the postman must Kinoshita present.* If the state transition coverage rises much faster, reaching consecutively pass some specified graph is an eulerian, the problem sim- 99% for the M2a implementation than streets. Starting from the postaffice (re- plifies to a onestroke one, and the test with M2b. Fault coverage reaches only set state), the postman, however, length becomes the minimum test 91% under the applied test sequence for should traverse all streets at least once, length-the number o f transitions plus the M2b implementation. while passing the minimal number of one. (An eularian graph is one that lets streets. (In the postman traveling prob- us walk all edges once and only once: Deterministic test generation. In lem, a postman picks up mail at the post that is, a eulerian graph can be drawn in general, FSMs are not completelyspecoffice and delivers it to each block in one stroke, with no edge repeated.) ified for their state transition tables. the territory. The postman wishes to The information obtained in the state Unspecified states, state transitions, and choose a route that minimizes the dis- assignment procedure can assist during dontcare terms remain for the tables. tance traveled. The vertices and edges functional test generation. For the dis- During functional test generation, calo f a graph G modeling this situation cor- tinguish table o f example M2 shown in culation of the undistinguishability respond to the street corners and con- Figure 6, the machine is now a 1- does not reflect these unspecified necting blocks of the postmans distinguishable machine after state terms. Also, for the traversing sequences territory. The solution, then, to the post- parity assignment. One remaining 1- containing dont care terms, we ranman traveling problem is a closed walk distinguishable state pair, [A,c ] , has an domly assign logic 0 or 1 to form the ino f minimum length G that uses every undistinguishable next state pair [D,E] put sequence. These reduce the edge at least once.) under input 1. So the input 1 state tran- effectiveness o f the derived functional
Table 2. The fault coverage percentages of the two implementations shown in

r / O )

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faults o f the implemented circuits. For example, in the M2a implementation just discussed, the derived functional test sequence reach only a 99%stuckat fault coverage. To reach 100%stuck-at fault coverage, we use a deterministic test generation method to generate test for a circuit synthesized employing the parity checker DFTscheme as follows:

~~

PCDFT-FTG CPU Test

F S M
name
bbsra bbsse

speed
(sec.)

length (patterns)

SST fault coveraae With Without PCDFT PCDFT (%) (%I

SA fault coverage With Without

PCDFT

PCDFT

(%I
100 98.2 100 100 99.6 100 100 100 100 100 100 99.3 98.6 100 99.6 100 99.8 98.7 99.8 100 100
8

(%I
77.2 87.7 72.6 83.5 96.5 97.6 97.2 99.5 96.4 86.3 93.1 67.3 53.9 94.2 91.2 97.8 94.5 85.9 91.6 95.4 98.2 88.5

bbtas
beecount

1. Find a sequence that traverses all cse states at least once as an initial test dk14 sequence. dk15 2. Run sequential fault simulation for dk16 the test sequence; drop the dedk17 tected faults and stop if no fault redk27 mains; and record the last reached dk512 state as the current state. ex3 3. Select a target fault. ex7 4. Run the combinational test generlion ation procedure for the target fault. lion9 The fault effect may appear in priopus mary outputs, or appear in odd sand number of flip-flops. Record the sse state that detects the fault as the styr target state and the input that train4 detects the fault as the activation train1 1 pattern. Average 5. Find a sequence that justifies the '99.69524 current state to the target state as the new test sequence,add the activation pattern into the test se- form logic optimization and circuit requence, and go to step 2. alization for the combinational logic system then automaticallyadds the flip Experiments flops and parity checker to make a seWe built an automatic synthesis sys- quential circuit. Finally, a single state tem on a Sun workstation to synthesize transition fault simulator SSTFS and a and generate functional test sequences stuck-at fault simulator SEESIMI4evalufor FSMs by incorporating our DFT ate the fault coverage. scheme. Upon receiving the transition As Tables 3 and 4 show, the system table o f an FSM,the system builds the has synthesized a number o f MCNC distinguish table, calculates the undis- (Microelectronic Center at North Carotinguishability, and suggests a parity lina) benchmark FSMs.I5In Table 3, the state group partition, as well as deriving second and third columns are the test a set of functional test sequences.With generation times and the test lengths o f the suggested state group partition, it the functional test sequences generatuses MUSTANG,13 a state-assignment ed during synthesis.The fourth column tool developed at UC Berkeley,to make is the SST fault coverage for the FSMs the state assignments and MisII to per- designed with the parity checker DFT
FALL 1994

0.02 0.03 0.02 0.02 0.05 0.02 0.02 0.1 3 0.02 0.02 0.03 0.02 0.02 0.02 0.02 0.02 0.20 0.03 0.1 8 0.02 0.02 0.04

92 150 36 53 212 83 43 195 65 22 56 93 101 14 33 82 334 169 389 14 42 108

100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100

90.7 83.6 94.2 82.4 75.4 91.7 85.4 98.7 91.5 91.7 96.0 55.6 38.3 87.9 80.1 92.8 99.3 84.2 89.4 81.0 80.8 84.3

scheme (PCDFT).All the SST fault coverage are 100%for these FSMs. The fifth column is the SST fault coverage for the FSMs with a parity checker added to FSMs to help detect the transition fault, but without applying the state parity assignment. For this case, the SST fault coverage averages 15%lower. The last two columns are the single stuck-at (SA) fault coverage o f each implemented logic circuit with and without employing the PCDFT scheme. Table 3 shows that the stuck-at fault coverages under the derived test sequence for the circuits employing the PCDFT scheme are generally over 99%, while the average SA fault coverage for the circuits without employing the
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T a b 4. Comparison of F T G and our KDR-FTG.

able 5 . Results of our deterministictest

meration PCDFJ-Det T G .
PCDFT-FIG Test Fault length coverage (patterns)

F S M
name

CPU' speed

FTG Test length

(patterns)

Fault coverage

CPU'

(sec.)
1.0 0.2 10.0 0.4 0.5 2.0 0.2 204.0 2.0 45.0 202.0
42.5 235

0
100.0 100.0 100.0 100.0 100.0 99.3 98.5 97.2 00.0 97.9 97.7
99.1

speed (sec.)
0.02 0.02 0.13 0.02 0.03 0.02 0.02 0.18 0.02 0.05 0.20 0.06 1. 0 0

w r

dk14 dkl5 dk16 dkl7 dk512 ex7 opus

styr

bbara
CSe

sand
Average Normalize-

228 146 406 86 89 158 96 964 241 880 809

373

83 43 195 65 56 101 82 389 92 212 334

150

100.0 100.0 100.0 100.0 100.0 98.6 00.0 99.8 00.0 99.6 99.8
99.8

SA fault PCDFT-DetTG CoveraQe CPU Test With Withou F S M speed length PCDFT PCDFT name (sec.) (patterns) 1%) ("4 51 1.1 2.3 104 16 bbtas 0.4 42 beecount 0.3 cse 5.9 158 61 dk14 2.3 29 dk15 1.0 dk16 9.1 172 45 dk17 0.8 19 dk27 0.2 58 dk512 1.0 36 ex3 1.1 44 ex7 1.5 11 lion 0.1 21 lion9 0.1 54 opus 1.1 sand 24.5 214 90 sse 2.4 styr 23.4 287 14 train4 0.1 38 train1 1 0.7 74 Average 3.8 bbara
bbsse

'CPU seconds: F T G on Sun 4/260 (I 0 MIPS), KDF-FTG on Sun Sparc 2 (28 MIPS).

Table 6 .Comparisonof STG3 and PCDFJ-DetTG.

STG3
CPU'

F S M name

speed

(=.I
12 4 7,176 9 92 314 25 20,613 36 9,657 9,106
4,277 218

Test Fault length coverage (patterns)

w r

PCDFT-DetTG Test Fault speed length coverage (=.I (patterns) (%I

CPU'

100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100
100

81.2 96.4 58.3 93.8 84.1 100 99.2 93.4 96.8 91.8 94.7 90.3 88.1 88.9 92.2 94.4 80.0 97.8 81.6 90.2 89.3
89.6

dk14 dkl5 dk16 dk17 dk512 ex7 opus

styr

bbara
CSe

sand
'
~

90 44 322 66 85 58 80 515 133 344 376

192

100.0 100.0 97.6 100.0 100.0 99.2 100.0 94.3 100.0 97.8 97.6
98.8

2.3 1.0 9.1 0.8 1.0 1.5 1.1 23.4 1.1 5.9 24.5
6.5 1.o

Average Normalized

61 29 172 45 58 44 54 287 51 158 214 107

100 100 100 100 100 100 100 100 100 100 100
100

'CPU seconds: FTG on Sun 4/260

(IOMIPS), PCDF-FTGon Sun Sparc 2 (28 MIPS).

PCDFT scheme is only 88.5%.For the PCDFT circuits whose SA fault coverage are not loo%, the undetected faults
36

mainly come from the unspecified term o f the FSMs. All these non-fully-testabl circuits have very low connectivity, ir

icating that functional test sequences rill not effectivelydetect SA faults when le machines have many unspecified 3rms. The test generation times are allost negligible for most circuits. Table 4 compares the test generation mes of Table 3 with those found in :heng and Jou.4 Here, the test generao n times for our PCDFT scheme ciruits represent the CPU times o f a Sun parc 2 workstation, a 28 MIPS machine, ihile those o f the functional test genertion (FTG) circuits4 represent CPU f a Sun 4/260 workstation, a 10 mes o !IPS machine. After normalizing CPU mes, the test generation times for 'CDIT circuits are 235 times shorter ian those o f FTG circuits. The table also
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lists the test length and fault coverage o f Table 7. Comparison of our DFT scheme (KDFT) with other approaches. eachsequence.Our PCDlTscheme cirHardware Extra Performance Test Test cuits have higher fault coverages, nearly 100%on average, and shorter test Approach overhead I/O pins degradation generation length capability CED lengths than those o f FTG circuits. Yes Simple Short Table 5 shows the results for the test Low 1 No PCDFT Yes Easy Long 23 Yes sequences generated by the determinParity-~can'~ High High 23 Yes istic test generation method for the imFull scan No Long Easy No Harder Short plemented PCDFT circuits. In the table, Low 23 Yes Partial scan the second and the third columns are I the test generation times and lengths o f Acknowledgments the test sequencesgenerated by the d e The authors wish to express their gratiterministic test generator (PCDFTtude for helpful comments from the reDetTG). The fourth column is the viewers. The National Science Council, stuck-at fault coverages for the test s e Taiwan, Republic of China, supported this quences for the PCDFT circuits,which work under contracts NSC-814404-EO09136 are all 100%.The fifth column shows the and NSC-82-0404-E009-183. fault coverages for the nonPCDIT circuits if they are applied to the same test sequences.The average fault coverage References is only 90%for this case. Also, note that 1. F.C. Hennie, "Fault-Detecting Experiments forSequential Circuits,"h c . FiHh for the deterministic test sequences, Ann. Symp. Switching Circuit Theoryand their test lengths are shorter than those o f the functional test sequences of hgicalDesign, Princeton, N.J., 1964, pp. 95110. Table 3. 2. H. Fujiwara and K. Kinoshita, "Design of To show the efficiency o f this test Diagnosable Sequential Machines Utigeneration, Table 6 compares our relizing Extra Outputs," IEEE Trans. Comsults with those o f STG3.* Our test lengths are shorter than those o f STG3; puters, Vol. 232,1974, pp. 138145. 3. M. Abramovici, M.A. Breuer, and A.D. we achieve 100%fault coverage for all circuits with much less test generation Friedman, Digital Systems Testing and time. We gain all this effectiveness from Testable Design, Computer Science Press, Oxford, England, 1990. the small penalty o f the parity checker. 4. K.T. Cheng and J.Y. Jou, "FunctionalTest Generation for Finite State Machines," &. Int'l Test Conference,C 5 Press, 1990, pp. 162-168. 5. S. Devadas and K. Keutzer, "A Unified Approach to the Synthesis o f Fully Testable Sequential Machines," IEEE Trans. Computer-AidedDesign, Vol. 10, 1991,pp.3 950. THE EXTRA OVERHEADon logic gates 6. V.D. Agrawal and K.T.Cheng, "TestFunction Specification in Synthesis," Roc. added in this scheme is very small, r e quiring only log,(number o f states)-1 27th &sign Automation C o d , CS Press, numbers of XOR gates. This figure is 1990,pp. 235240. less than the general extra overhead in 7. K.T. Cheng and V.D. Agrawal, "State As the conventional scan designs. Table 7 signment for Testable Design," Int'l J. compares the scan designs, the parityComputer-Aided V U I Design, Vol. 3, scan d e ~ i g nand , ~ our parity checker March 1991,pp. 291-308. DFT. 8. R. Leveugle and G. Saucier, "Optimized
~

FILL 1994

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JO AT KCAD

Synthesisof Concurrently CheckedControllers,IEEE Trans. Computevs,Vol. 39, 1990,pp. 419425. 9. H. Fujiwara and A. Yamamoto, ParityScan Design to Reduce the Cost of Test Application,h o c . Intl Test C o d , CS Press, 1992,pp. 283-292,. 10. M.L. Sheu and C.L. Lee, A Parity Checker Design for Testability Scheme for Finite State Machines,Roc. Asia-Pacific Cod CircuitsandSystems, IEEE Circuits and Systems Society, Piscataway, N.J., 1992,pp. 53-58. 11. S. Devadas, H.K. Ma, and A.R. Newton, Redundancies and Dont Cares in S e quential Logic Synthesis, J. Electronic Testing: Theory and Applications, Jan. 1990,pp.1530. 12. R. Brayton et al., MIS:Multiple-LevelInteractive Logic Optimization Systems, IEEE Trans. Computer-AidedDesign,Vol. 6, 1987,pp. 1062-1081. 13. S. Devadas et al., MUSTANG: State Assignment of Finite State Machines Targeting Multilevel Logic Implementations, IEEE Trans. Computer-Aided Design, Vo1.7, 1988, pp. 129@1300. 14. C.P. Wu, C.L. Lee, and W.Z. Shen, SEES IM-A Fast SynchronousSequentialCircuit Fault Simulator with Single Event Equivalence,h c . European Design Automation Cod,C S Press,1992,pp.446-449. 15. B. Lisanke, LogicSynthesisand Optimization Benchmarks,tech. report,MCNC, Research Triangle Park, N.C., Dec. 1988.

B S and M S degrees in electronics engineering. His research interests include V U 1 testing, logic arid high-level synthesis, and computer-aided design. He is a student member of the IEEE Computer Society,Circuits and Systems Society, and Communications Society.

Chung Len Lee currently is a professor in the Department of Electronics Engineering, National Chiao Tung University, where his teaching and research interests focus on integrated circuits and testing. He has supervised more than 90 M S and PhD candidates, and has published more than 140 papers in technical journals. He received his B S from the National Taiwan University and M S and PhD degrees from Carnegie Mellon University. Presently,he serves on the editorial board of the Journal of Electronic Testing: Theory and Applications,and is a member of the IEEE Asian Test Technology Committee. He is a senior member of the IEEE Circuits and Systems Society and the IEEE Computer Society.

Meng-Lieh Sheu is currently working toward his PhD in the Department of Electronics Engineering at the National Chiao Tung University, where he earlier received
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Direct questions concerning this article to Cheng Len Lee, Department of Electronics Engineering, National Chiao Tung University, 30050, Hsin-Chu, Taiwan: cllee@cc.nctu.edu.tw.
IEEE DESIGN & TEST OF COMPUTERS

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