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2013-1192 (Reexamination Nos. 95/000,166 & 95/001,122)

IN THE

UNITED STATES COURT OF APPEALS

FOR THE FEDERAL CIRCUIT

RAMBUS, INC., Appellant, v. MICRON TECHNOLOGY, INC., Appellee. Appeal from the United States Patent and Trademark Office, Patent Trial and Appeal Board. REPLY BRIEF FOR RAMBUS INC. J. Michael Jakes James R. Barney Molly R. Silfen Aidan C. Skoyles FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER, LLP 901 New York Avenue, NW Washington, DC 20001 (202) 408-4000 August 26, 2013 Attorneys for Appellant Rambus Inc.

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TABLE OF CONTENTS I. II. INTRODUCTION ...........................................................................................1 REPLY TO MICRONS ARGUMENTS ........................................................5 A. Micron Has Failed to Show by Substantial Evidence That Any Single Embodiment of Bennett Stores a Value That Is Representative of the Amount of Time to Transpire Between a Memory Read Request and Data Delivery ..........................5 1. Micron Misstates the Proper Weight to Be Given to the Examiners Factual Findings in an Inter Partes Reexamination ............................................................................5 Microns Alternative Construction of Representative Is Incorrect ......................................................6 Microns Alternative Construction of in Response to the First Operation Code and After the Amount of Time Transpires Is Erroneous .................................................11 The Configurations Shown in Figures 25a and 25b of Bennett Do Not Anticipate Claims 26 and 28 ..........................13 The Presence or Absence of One Extra Clock Cycle Does Not Satisfy Claim 26s Requirement of a Stored Value That Is Representative of the Request-to-Data Delay Time ....................................................21 Bennett Does Not Disclose Interleaved Transactions That Depend on Predetermined, Stored Delay Times ..............................................................................23

2. 3.

4. 5.

6.

B. III.

Microns Alternative Ground for Invalidity Based on JEDEC and Park Contradicts this Courts Prior Decisions.................25

Conclusion .....................................................................................................30

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TABLE OF AUTHORITIES FEDERAL CASES PAGE(S)

ArcelorMittal France v. AK Steel Corp., 700 F.3d 1314 (Fed. Cir. 2012) ..........................................................................16 Ariad Pharms., Inc. v. Eli Lilly & Co., 598 F.3d 1336 (Fed. Cir. 2010) ..........................................................................27 Association of Data Processing Service Organizations, Inc. v. Board of Governors of the Federal Reserve System, 745 F.2d 677 (D.C. Cir. 1984) .............................................................................. 5 Brand v. Miller, 487 F.3d 862 (Fed. Cir. 2007) .............................................................................. 6 Ex Parte Frye, 94 USPQ2d 1072 (BPAI 2010) ............................................................................ 5 Ex Parte Horito and Brown, 2012 WL 4842863 (BPAI 2012) .......................................................................... 6 ICU Medical, Inc. v. Alaris Medical Systems, Inc., 558 F.3d 1368 (Fed. Cir. 2009) ....................................................................27, 29 In re Caveney, 761 F.2d 671 (Fed. Cir. 1985) ..............................................................................6 In re Gartside, 203 F.3d 1305 (Fed. Cir. 2000) ............................................................................5 Hynix Semiconductor Inc. v. Rambus Inc., 645 F.3d 1336 (Fed. Cir. 2011) ....................................................................26, 27 LizardTech, Inc. v. Earth Resource Mapping, Inc., 424 F.3d 1336 (Fed. Cir. 2005) ..........................................................................27 Rambus Inc. v. Infineon Technologies AG, 318 F.3d 1081 (Fed. Cir. 2003) ....................................................................26, 28

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Rambus, Inc. v. Micron Technology, Inc., No. 2013-1224 (Fed. Cir.) ..................................................................................25 Rambus, Inc. v. Micron Technology, Inc., No. 2013-1228 (Fed. Cir.) ..................................................................................25 Sage Products, Inc. v. Devon Industries, Inc., 126 F.3d 1420 (Fed. Cir. 1997) ............................................................................ 6 Talbert Fuel Systems Patents Co. v. Unocal Corp., 275 F.3d 1371 (Fed. Cir. 2002), vacated and remanded on other grounds, 537 U.S. 802 (2002) ............................................................................................10 Tehrani v. Hamilton Medical, Inc., 331 F.3d 1355 (Fed. Cir. 2003) ...................................................................passim Vitronics Corp. v. Conceptronic, Inc., 90 F.3d 1576 (Fed. Cir. 1996) ............................................................................11 In re Zurko, 258 F.3d 1379 (Fed. Cir. 2001) ............................................................................ 6 FEDERAL STATUTES 35 U.S.C. 315 (2002) ............................................................................................26 35 U.S.C. 317 (2002) ............................................................................................26

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I.

INTRODUCTION Micron concedes that Bennetts configuration parameter VI can, at most, be

configured to include or not an extra clock cycle of delay before the transmission of data. (Micron Br. 10 (emphasis added); see also id. at 38 ([A] setting of 1 in parameter VI for Figures 25b and 36 represents one extra clock cycle delay.).) Thus, Microns argument is premised on the inclusion (or not) of an extra clock cycle of delay based on a configuration setting that fails in every embodiment to represent the rest of the overall delay, i.e., the indeterminate period of time between receipt of a read request in Bennett and the delivery of data. As the examiner correctly found, this one extra clock cycle is not representative of an amount of time to transpire after which the memory device outputs the first amount of data because there are other factors, such as arbitration and retry conditions, that can also affect this delay period. Most of Microns brief is spent trying to overcome this glaring problem with the Boards decision. First, Micron points to Figures 25a and 25b of Bennett as allegedly showing a configuration in which each action takes only one clock cycle (Micron Br. 9), which, according to Micron, means that the total time to data delivery depends only on the wait-line setting. Yet this is simply false. Figures 25a and 25b do not illustrate actual memory read transactions but, instead, merely generic transactions in which real-world factors such as arbitration losses 1

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and retry conditions have been ignored (i.e., the arbitration and wait functions in these bus configurations are assumed to take but one cycle) in order to simplify presentation of timing concepts. (A1362[85:17-19].) Thus, the most that can be gleaned from these figures is that changing configuration parameter VI from 3 to 1 will result in one extra clock cycle of delay. Nothing in these figures shows what the total delay period will be in an actual memory read transaction across those bus configurations once real-world factors such as arbitration losses and retry conditions are considered. Next, Micron complains that Rambus is seeking to require that every single configuration of Bennett must read on the claim under every circumstance in order to anticipate. (Micron Br. 3.) Yet that is not Rambuss argument at all. 1 The problem with the Boards decision is that there is no embodiment in Bennett that discloses storing a value that is representative of the time between receipt of a read request and the corresponding delivery of data. Figures 25a and 25b do not disclose this because they purposely do not illustrate arbitration losses and retry conditions, which, in an actual memory read transaction across those same bus

Indeed, it is Micron who is misconstruing the anticipation requirement by focusing myopically on the hypothetical transactions of Figures 25a and 25b and just one particular configuration setting (which has nothing to do with overall transaction timing), while ignoring the full teaching of Bennett and the many other configuration settings and bus conditions that can affect the timing of a memory read transaction, as more fully illustrated in Figure 35. 2

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configurations, would render the total delay time indeterminate. As for the figures of Bennett that do show real-world memory transactions, such as Figure 35, Micron all but concedes they do not anticipate. (Micron Br. 18, 39.) Micron also argues that the Boards rejection relied on embodiments of Bennett that either did not use an arbitration protocol or won the arbitration on the first attempt. (Micron Br. 4.) To begin with, there is no such thing as an embodiment in Bennett that always wins arbitration on the first attempt. Instead, whether arbitration is won on the first attempt depends entirely on the nature of each individual transaction and the instantaneous conditions on the bus. Second, even when arbitration is won by the memory device on the first attempt, there is still an indeterminate amount of time that transpires before that arbitration attempt, as indicated by the first set of vertical ellipses in Figure 35. Micron fails to address this undisputed fact, even though it was discussed extensively in Rambuss opening brief (see Rambus Br. 8, 25-26, 31, 52). Finally, Micron fails to point to any embodiment in Bennett that includes a wait line and executes memory read transactions without arbitration. In fact, the only memory read transactions that include wait information in Bennett are the type illustrated in Figure 35, which clearly requires arbitration. As a fallback, Micron argues that the delay-time limitation only requires a minimum amount of time to transpire before the memory device outputs data, but 3

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does not preclude additional delay caused by other circumstances such as arbitration. (Micron Br. 4-5.) Of course, this is clearly wrong. Aside from the claim language itself, which makes clear that the delay time is measured from receipt of an operation code to the delivery of data, the whole point of the accesstime register in the 916 patent is to allow the memory controller to interleave transactions by knowing in advance what the actual time will be between a memory request and the corresponding delivery or sampling of data. Microns alternative construction would eviscerate the delay-time limitation and read out the preferred embodiment of the invention. Finally, as an alternative ground for affirmance, Micron argues that the Board should have found that the 916 patent was not entitled to its priority date and that JEDEC and Park render claim 26 and 28 invalid. (Micron Br. 43.) As an initial matter, Micron is not entitled to raise this argument because it was not part of its reexamination request. Beyond that, the examiner and the Board properly found that the 916 patent is entitled to its priority date and that JEDEC and Park are not prior art. For the reasons explained below, this Court should reverse the Boards obviousness ruling and reinstate the examiners correct decision affirming claims 26 and 28 over Bennett.

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II.

REPLY TO MICRONS ARGUMENTS A. Micron Has Failed to Show by Substantial Evidence That Any Single Embodiment of Bennett Stores a Value That Is Representative of the Amount of Time to Transpire Between a Memory Read Request and Data Delivery 1. Micron Misstates the Proper Weight to Be Given to the Examiners Factual Findings in an Inter Partes Reexamination

The examiners factual findings form part of the record, and contrary to Microns assertions (Micron Br. 35-37) the Board may not simply disregard them when they prove inconvenient. See In re Gartside, 203 F.3d 1305, 1312-14 (Fed. Cir. 2000) (Court must examine the record as a whole, taking into account evidence that both justifies and detracts from the Boards decision) (emphases added). In asserting otherwise, Micron relies on a Board decision that itself refers to its review of the examiners findings and conclusions. (Micron Br. 36 (quoting Ex Parte Frye, 94 USPQ2d 1072, 1077 (BPAI 2010)).) Thus, regardless of the standard of review the Board uses when reviewing the examiner, the Boards decision must be supported by substantial evidence in the closed record, which includes the evidence presented by the parties and the examiners findings. Gartside, 203 F.3d at 1315 ([S]ubstantial evidence [must] be found within the record of closed-record proceedings to which it exclusively applies. (quoting Assn of Data Processing Serv. Orgs., Inc. v. Bd. of Governors of the Fed. Reserve Sys., 745 F.2d 677, 684 (D.C. Cir. 1984)). 5

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Micron contends, incorrectly, that the Board gives no deference to an examiners factual findings. (Micron Br. 36-37, citing Frye, 94 USPQ2d at 1077 and a USPTO blog entry). To the contrary, [t]he Board reviews facts found by the Examiner to determine whether those facts are supported by a preponderance of the evidence. Ex Parte Horito and Brown, 2012 WL 4842863, at *2 (BPAI Sept. 27, 2012) (citing In re Caveney, 761 F.2d 671, 674 (Fed. Cir. 1985)). A preponderance-of-the-evidence review is not the same as a de novo review. Regardless, the Boards review cannot simply dismiss the examiners findings, as Micron erroneously asserts. Sage Prods., Inc. v. Devon Indus., Inc., 126 F.3d 1420, 1426 (Fed. Cir. 1997) (No matter how independent an appellate courts review of an issue may be, it is still no more than thata review.); see also In re Zurko, 258 F.3d 1379, 1385-86 (Fed. Cir. 2001) (explaining that, with respect to core factual findings, Board cannot simply reach conclusions based on its own understanding or experience); Brand v. Miller, 487 F.3d 862, 869 (Fed. Cir. 2007) ([I]n the context of a contested case, it is impermissible for the Board to base its factual findings on its expertise, rather than on evidence in the record, although the Boards expertise appropriately plays a role in interpreting record evidence.). 2. Microns Alternative Construction of Representative Is Incorrect

With respect to the proper construction of representative, Micron appears to be of two minds. First, it appears to agree with this Courts holding in Tehrani 6

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v. Hamilton Med., Inc., 331 F.3d 1355, 1361 (Fed. Cir. 2003) that, to be representative, a value must be directly related to and stand for, or be a reasonable proxy for, the latter item. Specifically, Micron contends that the Board found Bennetts parameter values represent, dictate, symbolize, or stand for a value of time, which is consistent with the meaning of representative in Tehrani. (Micron Br. 26.) Micron further contends that the finding that Bennett anticipates under the construction argued for by Rambus should be reviewed for substantial evidence. (Id. at 30.) Certainly, Micron would not be advocating that this Court review the Boards decision under an incorrect construction; thus, it can only be assumed that Micron agrees with the construction advocated by Rambus, which (as Micron concedes) is consistent with the meaning of representative in Tehrani. (Id. at 26.) But Micron then hedges it bet by suggesting that, [t]o the extent the Board relied on a broader construction of representative, such construction was based on the usage of representative in the 916 Patent. (Id. at 30 (emphasis added).) Microns use of the qualifier to the extent that reveals its own uncertainty as to whether the Board actually articulated any such broader construction of representative. Moreover, Micron fails to justify any such construction. Microns only purported evidence of an alleged broader usage of representative in the 916 patent is a single passage at column 11, lines 44-64. 7

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(See Micron Br. 30.) But nowhere does that passage use representative any differently than its ordinary meaning. Instead, that passage explains an encoding scheme in which four bits (i.e., BlockSize[0:3]) are used to represent various block sizes from 0 to 1024 bytes. (A154[11:45-67].) Each four-bit combination uniquely describes (and therefore represents) a different block size. 2 This is fully consistent with the ordinary meaning of representative as explained in Tehrani. Micron also attempts to defend the Boards rationale that claim 26, as a device claim, only requires the stored access-time value to have the capability of representing the time period between receipt of a read request and the delivery of data, even if it does so only sporadically and unpredictably. (A19.) According to Micron, the Boards use of the term capability was in reference to anticipatory disclosure of the prior art and not with reference to the construction of the term representative. (Micron Br. 32.) Micron contends that the Board was merely clarifying that claim 26 is broad enough to encompass a prior art memory device that discloses the capability of winning arbitration on the first attempt. (Id.) Micron contends that the 3-bit pattern of 011 can represent[] either a value of 3 or 64 depending on what encoding scheme is selected by a separate parameter. (Micron Br. 30.) This is highly misleading, however, because BlockSize[0:3] is a 4-bit pattern, not a 3-bit pattern. Thus, only 0011 would represent a value of 3, and only 1011 would represent 64. (See A154[11:55-65] (1011 in binary corresponds to 11 in decimal form, which corresponds to a block size of 64 bytes).) Thus, each 4-bit pattern represents only one value. 8
2

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Microns attempt to recast the Boards capability rationale as pertaining to anticipation rather than claim construction does not cure the defect in that rationale. As Micron appears to concede, the ordinary meaning of representative requires a value that consistently represents (i.e., stands for) another value. This relationship cannot merely depend on happenstance. This is why the Boards capability rationale is illogical. According to the Boards rationale, even if the wait-line value in a particular bus configuration of Bennett fails to correlate to the actual request-to-data-delivery delay period in 99.99% of all memory transactions on that bus, if it correlates occasionallyi.e., even if purely by happenstance in 0.01% of transactionsthen the delay-time limitation is satisfied. This rationale cannot be correct, however, because it would eviscerate the ordinary meaning of representative, i.e., a value that must be directly related to and stand for, or be a reasonable proxy for, the latter item, Tehrani, 331 F.3d at 1361, and it would render the claimed invention inoperable. As explained in Rambuss opening brief, the purpose of storing values in access-time register 173 in the 916 patent is to allow a controller to know at the time of the request and with precision when a particular device will respond to a given read or write request, to allow interleaved scheduling. (A156[16:1-13].) If the access-time values were only sometimes accurate, and only under unpredictable circumstances (as the Boards rationale would allow), the system 9

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would not work properly because the controller would not be able to depend on the correct data consistently being on the bus at the selected time. (See A156[16:6-7].) As a matter of law, a construction which inhibits the operation of the claimed invention should be viewed with extreme skepticism. Talbert Fuel Sys. Patents Co. v. Unocal Corp., 275 F.3d 1371, 1376 (Fed. Cir. 2002) (citation omitted), vacated and remanded on other grounds, 537 U.S. 802 (2002). Micron next argues (for the first time on appeal) that, [w]hen viewed in light of the specification, it is clear that outputting data exactly when the access time transpires is only a preference and not a requirement. (Micron Br. 16.) Micron cites certain passages in the 916 patent that use preferential language, e.g., a slave should preferably respond to a request in a specified time, sufficient to allow the slave to begin or possibly complete a device-internal phase including any internal actions that must precede the subsequent bus access phase. (Id. at 15-16, citing A152[8:55-58] (emphasis Microns).) problems with this newly minted argument, however. First, regardless of whether the exact-timing feature was described as a preferred embodiment in the specification, it is the claimed embodiment. Claim 26 specifically requires that the output drivers output the amount of data in response to the first operation code and after the [specified] amount of time transpires. (A162[27:1-3] (emphasis added).) Patentees are certainly entitled to claim their 10 There are at least two

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preferred embodiments, and it is the claims that define the scope of the invention, not the specification. Vitronics Corp. v. Conceptronic, Inc., 90 F.3d 1576, 1582 (Fed. Cir. 1996). Second, the passages Micron cites do not even support its newly raised theory that the access time is at best a minimum time needed for the memory device to perform a transaction. (Micron Br. 16.) In fact, precisely the opposite is true; the stored access-time value represents the maximum time a memory device might need before it can respond to a memory request. As the 916 patent clearly explains: The configuration master should choose and set an access time in each access-time register 173 in each slave to a period sufficiently long to allow the slave to perform an actual, desired memory access. For example, for a normal DRAM access, this time must be longer than the row address strobe (RAS) access time. (A156[16:1-6] (emphases added).) Thus, Microns new minimum theory is plainly wrong and cannot justify the Boards anticipation ruling. 3. Microns Alternative Construction of in Response to the First Operation Code and After the Amount of Time Transpires Is Erroneous

Micron attempts to defend the Boards fallback claim-construction argument that claim 26 does not specify any particular signal to trigger the time delay. (A20.) According to Micron, the delay time in claim 26 need not be measured starting immediately after receipt of the read request but, instead, can be 11

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measured from any arbitrary point after receipt of the read request. (Micron Br. 33.) This claim construction is unsupportable. The final limitation of claim 26 specifically requires that the output drivers output the [specified] amount of data in response to the first operation code and after the [specified] amount of time transpires. (A162[27:1-3] (emphasis added).) Micron attempts to dismiss this claim language on the ground that the phrase in response to the first operation code is directed to the amount of data and not to the amount of time transpires. (Micron Br. 34.) Yet Micron conveniently overlooks the word and that joins those two clauses. In other words, the claim clearly requires that the output drivers respon[d] to the first operation code by output[ting] the [specified] amount of data . . . after the [specified] amount of time transpires. There is simply no other logical way to read this claim language. The amount of time to transpire after which the memory device outputs the first amount of data therefore begins immediately after receipt of the first operation code. The 916 specification confirms this common-sense reading of the claim language. For instance, the specification explains in the context of the preferred embodiment: To reduce the complexity of the slaves, a slave should preferably respond to a request in a specified time, sufficient to allow the slave to begin or possibly complete a device-internal phase including any internal actions that 12

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must precede the subsequent bus access phase. The time for this bus access phase is known to all devices on the buseach master being responsible for making sure that the bus will be free when the bus access begins. Thus the slaves never worry about arbitrating for the bus. (A152[8:54-62].) Thus, a slave (i.e., memory device) responds to a request in a specified time. This means the delay time runs from the receipt of the request (i.e., operation code) to the point where the memory device responds by returning the requested data, precisely as recited in claim 26. 4. The Configurations Shown in Figures 25a and 25b of Bennett Do Not Anticipate Claims 26 and 28

Micronlike the Boardrelies almost exclusively on Figures 25a and 25b of Bennett for its anticipation argument. The reason Micron relies on those

simplified figures is that the other figures of Bennett, such as Figure 35 (which shows an actual memory read transaction), clearly do not anticipate the asserted claims. Micron incorrectly states that Rambus has argued that the same outcome must occur in every single one of Bennetts 30,000+ configurations in order to show anticipation. (Micron Br. 42-43.) But Rambus has argued no such thing. Instead, it is Rambuss position (and the examiners below) that no embodiment of Bennett, including the bus configurations corresponding to Figures 25a and 25b, discloses a predetermined, stored value that is representative of the amount of time to transpire after which the memory device outputs the first amount of data.

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To begin with, Micron concedes that the wait-line parameter in Bennett can, at most, be configured to include or not an extra clock cycle of delay before the transmission of data. (Micron Br. 10 (emphasis added)); see also A1565.) As Rambus has explained and Micron does not contest, this one extra clock cycle can be completely obscured by other factors such as arbitration losses and retry conditions, which are ignored in the transactions illustrated in Figures 25a and 25b (because arbitration and wait are assumed to be but one cycle) but which could occur in a real-world memory transaction like that shown in Figure 35. This renders the one extra clock cycle nonrepresentative of the overall transaction time. (See Rambus Br. at 29-31.) Micron incorrectly contends, however, that Figures 25a and 25b of Bennett allegedly show an embodiment where there are no other factors, such as arbitration losses and retry conditions, affecting the time period between receipt of a transaction request and the delivery of data, such that the only factor affecting timing is the value of the wait-line parameter. (Micron Br. 9-10, 35, 41-42.) But Micron ignores several glaring problems with this argument. First, contrary to Microns suggestion, because the bus configurations corresponding to Figures 25a and 25b of Bennett do, in fact, include arbitration and wait information placeholders, any transactions occurring across those bus configurations can be affected by arbitration losses and retry conditions, even 14

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though those events are not specifically illustrated in those figures. Specifically, the configuration for Figure 25a is 122121XX, with arbitration, slave ID/function, wait, and data all multiplexed on X shared lines. (A1362[85:50-57, 86:9-14].) The configuration for Figure 25b is 122123XX, with one dedicated wait line and arbitration, slave ID/function, and data all multiplexed on X shared lines. (A1362[86:31-37].) Both figures clearly show an arbitration time slot and a wait time slot, either of which could result in an unknown change in data timing for any given transaction due to arbitration losses and/or a wait signal that necessitates a retry. That Figures 25a and 25b do not specifically illustrate these events is immaterial since one skilled in the art would understand the usage of those functions by Bennett and how they would affect the 122121XX and 122123XX embodiments in a real-world memory read transaction, such as that shown in Figure 35. Moreover, a person skilled in the art would understand that other configuration settings, besides the wait-line setting, can affect memory transaction timing. Moreover, Figures 25a and 25b of Bennett are clearly not intended to illustrate actual memory read transactions as required by claims 26 and 28. Instead, as Bennett explains, to simplify presentation of timing concepts [in Figures 25a-h,] all . . . activities are assumed to be but one cycle. (A1362[85:1719] (emphasis added).) This means the illustrated transactions in Figures 25a and 15

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25b are merely hypothetical, i.e., all other factors affecting timing have been stripped away in order to show just the isolated effect of varying the degree of multiplexing on the timing of a generic informational transaction. (A1362[85:1317] (The progression of cases is from timing on the fully pin multiplexed Versatile Bus as shown in FIG 25a through six intermediate cases to timing on the fully pipelined Versatile Bus as shown in FIG. 25h.).) Thus, Figures 25a and 25b do not illustrate the multiple possible ways in which an actual given memory transaction might proceed on a Versatile Bus configured in accordance with one of those figures. 3 Taking Figure 35 as an example of an actual memory read transaction in Bennett, the annotated illustration below shows what would have to be assumed in order to result in the artificially simplified timing of Figure 25b:

Indeed, Figures 25a and 25b do not specifically disclose memory transactions at all. For instance, they fail to show any address information being sent across the bus, as would be required for a memory transaction. And contrary to Microns assertion that the Board found these figures represent transactions of a memory device, (Micron Br. 42), what the Board actually found was that Figures 25a-h represent generic slave devices and hence encompass memory devices. (A16.) Encompassing a memory device is not the same as disclosing a memory device, just as the term vehicle encompasses but does not disclose a unicycle. See ArcelorMittal France v. AK Steel Corp., 700 F.3d 1314, 1323 (Fed. Cir. 2012) (holding that a generic reference to coating did not anticipate a claim specifically requiring an aluminum coating). 16

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no retry due to wait must assume zero delay before arbitration memory must win arbitration on first try no retry due to wait

(A1088[Fig. 35] (annotations added).) As shown above, in order for an actual memory read transaction in Bennett to correlate to the hypothetical conditions shown in Figure 25b (i.e., where all activities are assumed to be but one cycle), one would have to assume that: (1) the memory device is immediately available to absorb the transmitted address (i.e., no retry due to wait); (2) there is no delay before memory arbitration begins (i.e., the first set of vertical ellipses equals zero clock cycles); (3) the memory wins arbitration on the first attempt (i.e., the second set of vertical ellipses equals zero clock cycles); and (4) the requester is immediately able to absorb the requested data (i.e., no retry due to wait). Only if all of these assumptions were true would a real-world memory read transaction such as that shown in Figure 35 match the 17

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artificial conditions assumed in Figure 25b. Micron has not shown by substantial evidence that these specific conditions would consistently occur in any particular memory access configuration of Bennetts Versatile Bus, as required by the representative limitation of claims 26 and 28. Perhaps recognizing this dilemma, Micron argues that sometimes the simplified assumptions are true, for example, in systems that do not require arbitration. (Micron Br. 41 (emphasis added).) But aside from the fact that there is no record evidence showing that sometimes the simplified assumptions are true for any actual memory transactions in Bennett, Micron faces an even bigger hurdle with this argument. Namely, it cannot point to any described embodiment in Bennett that includes a wait line and executes memory read requests without arbitration.4 Certainly, the large memory embodiments in Bennett do not satisfy this criterion because, as shown in Figure 34, all read transactions for large memory involve both requester arbitration (REQ. ARB.) and memory arbitration (MEM. ARB.), precisely as shown in Figure 35. (A1087[Fig. 34].) And as for Microns new argument that Fast Memory would not lose bus access requiring Claim 26 pertains specifically to memory read transactions, as opposed to write transactions, because it requires data to be output by the memory device in response to a first operation code. (A161[26:63-64] (emphasis added).) This is why Rambus has focused primarily on Figure 35, which discloses a read transaction, rather than Figure 36, which shows a write transaction. Micron, in contrast, scarcely discusses Figure 35, except to dismiss it as allegedly irrelevant. (See Micron Br. 39.) 18
4

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arbitration to regain bus access (Micron Br. 39-40), this is a nonstarter because, as shown in Figure 33, the fast memory configurations described in Bennett do not use wait lines. (A1086[Fig. 33]; see also A1365[92:46-51] (describing fast

memory with no Wait, the slave test memory must access data); A1366[94:2] (No Wait Lines are employed.).) Thus, it should come as no surprise that there are no findings of fact in the closed record below supporting Microns newly minted attorney argument regarding Bennetts fast memory. As a fallback, Micron argues that, even for embodiments subject to arbitration the memory device can win arbitration in the first try in which case the exact number of clock cycles to transpire is easily calculated . . . (Micron Br. 40.) This is simply false.5 As Rambus explained in its opening brief (Rambus Br. 2526, 52)and as Micron does not disputein a large-memory read transaction in Bennett, there is an indeterminate period of time before the memory attempts to arbitrate onto the bus to deliver the requested data. This is clearly shown in Figure 35, which includes two sets of vertical ellipses, the first of which indicates an arbitrary time period before the memory even begins attempting to arbitrate onto the bus:
5

Equally false is Microns unsupported assertion that Rambus admits that in some circumstances the delay would be definite even with an arbitration protocol, and thus claims 26 and 28 would be anticipated. (Micron Br. 4.) Tellingly, Micron provides no citation for this alleged bombshell admission, nor could it since Rambus has never admitted any such thing. 19

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Excerpt of Figure 35 of Bennett

Thus, even when memory win[s] arbitration in the first try (Micron Br. 40), this does not mean the exact number of clock cycles to transpire [can be] easily calculated (id.). Instead, there is still an indefinite time period, unknown to the requester, before the memory first attempts arbitration. Likewise, Micron igonores that the wait signal itself can result in a retry condition, in which the memory (acting as master) must retransmit the requested data to the original requester (acting as slave) because the original requester is unavailable to absorb it. (See A1357[76:25-30] ([O]currence of a Wait signal simply tells the User who is master that the currently outgoing data is failing to be absorbed by at least one slave User device and that the master User should (normally) try again after an interval to send the same data.).) Thus, Microns hypothesis that the exact number of clock cycles to transpire in Bennett can be calculated when arbitration is won on the first try (Micron Br. 40) is both factually unsupported and demonstratively incorrect. 20

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Finally, even assuming arguendo that sometimes the simplified assumptions [of Figures 25a and 25b] are true for actual memory transactions in Bennett (a proposition for which Micron cites no evidentiary support), this still would not support a finding of anticipation. Instead, this is simply a rehash of the Boards erroneous capability argument, which depends entirely on an incorrect construction of representative. As explained above, to be representative in the ordinary sense, the stored value recited in claims 26 and 28 must consistently correspond to the actual request-to-data delay time for a given memory device; it cannot do so merely occasionally or by happenstance. 5. The Presence or Absence of One Extra Clock Cycle Does Not Satisfy Claim 26s Requirement of a Stored Value That Is Representative of the Request-toData Delay Time

As explained above, Micron does not dispute that the wait-line setting in Bennetts configuration parameter VI can, at most, be configured to include or not an extra clock cycle of delay before the transmission of data. (Micron Br. 10 (emphasis added).) This extra clock cycle occurs only when the wait-line value is set to 1, specifying a multiplexed wait line. For all other values of

configuration parameter VI (i.e., 2, 3, 4 and 5) there will not be any extra clock cycle, because either the wait line(s) are dedicated (configuration settings 3, 4, and 5) or there are no wait lines at all (configuration setting 2). (A15.) Thus, the entire premise of Microns argument is that, when Bennetts configuration parameter VI 21

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is set to 1, the system allegedly stores a value that is representative of an amount of time to transpire after which the memory device outputs the requested data. (Micron Br. 11.) This, however, is fundamentally incorrect because the one extra clock cycle attributable to the multiplexed wait line indicates only the difference (i.e., the delta) between two different delay times in two different bus configurationsone with a multiplexed wait line and one without. This oneclock-cycle delta indicates nothing about what the actual delay time is in any given memory read transaction. By analogy, assume an employer wishes to store a value for each employee that is representative of their commute time to work. Assume further that a particular traffic signal near the office is known to add at least one extra minute to a persons commute time. If the only value that is stored for each employee is a 0 or 1, indicating whether or not that traffic signal is included in the employees commute, this value would obviously not be representative of each employees actual commute time. Instead, the only thing this value would indicate is whether an employee has at least one extra minute of commute time attributable to the traffic signal. Likewise, the only things Bennetts configuration parameter VI indicates about timing are whether there is an extra clock cycle in the time period between receipt of a read request and delivery of data and whether a slave may disturb timing by requesting a retry; it indicates nothing about what that actual 22

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time period is. Hence, as the examiner correctly found (A1567-68), the wait-line setting in Bennett is not representative of the relevant time period recited in claims 26 and 28 of the 916 patent. 6. Bennett Does Not Disclose Interleaved Transactions That Depend on Predetermined, Stored Delay Times

Micron contends that Bennett, like the 916 patent, discloses the ability to interleave transactions as one of its core objects. (Micron Br. 2, 14.) But what Micron is actually referring to is Bennetts disclosure that communication activities may be selectively configurably pipelined (time overlapped). (A1329[19:28-33] (emphasis added).) This is not a teaching of interleaving memory transactions using predetermined, stored values in an access-time register. Instead, the figure of Bennett that Micron relies upon (Figure 30) illustrates a full pipeline class of Versatile Bus having up to thirty-seven dedicated pins (lines). (A1364[89:37-41, 64-67].)

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(A1084[Fig. 30].) As shown above, because transactions can be pipelined in this configuration (i.e., handled on separate lines simultaneously), there is no need to interleave transactions in the manner taught in the 916 patent. For instance, as shown above, Transactions 1, 2, and 3 all occur simultaneously at Clock N+2i.e., they are not interleaved. Because of this, data delivery for Transaction 1 does not need to be delayed by a certain number of clock cycles in order to free up bus lines for the Slave ID/Function of Transaction 2 or the Arbitration cycle of Transaction 3, as would be the case if these transactions were interleaved on the same bus lines. Thus, Micron is mistaken when it describes Bennett as disclosing interleaving of memory transactions in the same sense as the 916 patent.

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Micron also attempts to discount Rambuss analysis of Bennett by asserting, incorrectly, that Rambuss argument presumes that Bennett is inoperable as Bennetts interconnect system could not operate without knowledge of the timing of transactions, including memory transactions. (Micron Br. 31.) Contrary to this unsupported assertion, Figure 35 specifically shows Bennett functioning perfectly fine despite the indefinite timing caused by arbitration losses and retry conditions, which render the total transaction time unknowable to the requester when the transaction initially begins. Thus, Bennett can indeed operate without a requester knowing how long it will take for a particular slave memory to respond to a read instruction. B. Microns Alternative Ground for Invalidity Based on JEDEC and Park Contradicts this Courts Prior Decisions

Without even addressing the merits of the references, Micron argues that JEDEC and Park render claims 26 and 28 invalid. As an initial matter, because that argument was not part of Microns request for reexamination, Micron does not have standing to raise it. Instead, Samsung (another requester) raised a similar (but not identical) argument in its request for reexamination, and Micron is now attempting to adopt Samsungs reexamination as its own, which is improper.6 See
6

This argument was more fully explained in the briefing in two co-pending cases before this Court. See Rambus, Inc. v. Micron Tech., Inc., No. 2013-1224 (Fed. Cir.) (brief for Rambus filed June 27, 2013); Rambus, Inc. v. Micron Tech., Inc., No. 2013-1228 (Fed. Cir.) (brief for Rambus filed June 28, 2013). 25

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35 U.S.C. 315(b) (2002) (contemplating appeal only of issues raised by that requester), 317(a) (prohibiting third-party requester from concurrently pursuing two inter partes reexaminations of the same patent). Moreover, as the examiner and the Board correctly concluded, Rambus is entitled to its priority date, such that JEDEC and Park are not prior art. (A1518-19 (relying on A10329-37); A1529; A1588; A23.1-23.4.) Micron contends claims 26 and 28 are overbroad because they are not limited to one particular type of bus, a multiplexed bus, even though these claims are directed exclusively to features other than the bus. As the examiner and the Board correctly found, however, the original disclosure of the 898 application is not limited to a multiplexed bus. (A23.1-23.4.) Indeed, this Court has already concluded the same thing, a decision that is stare decisis on this issue. In Rambus Inc. v. Infineon Techs. AG, 318 F.3d 1081, 1091-95 (Fed. Cir. 2003), in the context of claim construction, this Court analyzed whether the disclosure of the 898 application was limited to a multiplexed bus and found that a multiplexing bus is only one of many inventions disclosed in the 898 application. Id. at 1095. Micron asserts this Courts analysis of the disclosure was eclipsed by a later hypothetical statement by this Court in Hynix Semiconductor Inc. v. Rambus Inc., 645 F.3d 1336, 1352-53 (Fed. Cir. 2011). (Micron Br. 43-45.) But Micron misreads the Hynix decision. In Hynix, this Court held that a jury was reasonable 26

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in finding that Rambuss claims do, in fact, meet the written-description requirement without requiring a multiplexed bus. Hynix, 645 F.3d at 1351-53. Thus, the jurys determination and this Courts affirmance of it are themselves compelling evidenceand certainly provide substantial evidence to support the Boards determinationthat the claims meet the written-description requirement and are therefore entitled to their priority date. See Ariad Pharms., Inc. v.

Eli Lilly & Co., 598 F.3d 1336, 1351 (Fed. Cir. 2010) (en banc) (written description requirement is a question of fact reviewed for substantial evidence). Indeed, this Court determined in Hynix, 645 F.3d at 1352-53, that the jurys factfinding overcame any analogy to either ICU Medical or LizardTech, an analogy the Board similarly addressed and rejected (A23.2-3 (citing ICU Med., Inc. v. Alaris Med. Systems, Inc., 558 F.3d 1368, 1378 (Fed. Cir. 2009), and LizardTech, Inc. v. Earth Res. Mapping, Inc., 424 F.3d 1336, 1344 (Fed. Cir. 2005)).) Thus, each of this Courts statements about the written description of the 898 application supports the examiners and the Boards holding. Contrary to Microns argument (Micron Br. 50-57), the original disclosure describes inventions that do not require a multiplexed bus, including synchronous memory devices, controllers for controlling such devices, and systems that include such devices. (A150-51[3:24-49, 4:36-43, 5:55-60]; A1645.) The specification goes on to describe numerous object[s] of this invention, only one of which is to 27

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a multiplexed bus. (A150[3:23-49] (referring to a relatively narrow bus).) For example, the specification discusses a bus interface for large blocks of data (A150[3:24-28]), or a clocking scheme allowing for high speed clock signals to be sent along the bus with minimal clock skew (A150[3:29-31]), neither of which requires a multiplexed bus. See also Infineon, 318 F.3d at 1095 (noting that a multiplexing bus is only one of many inventions disclosed in the 898 application). The specification refers repeatedly and generically to a bus, without indicating whether the bus is multiplexed or not. (See, e.g., A150[4:39-40] (bus lines are controlled-impedance, double-terminated lines); A151[5:55-60] (a bus [is connected] to an independent cache memory).) Although the specification describes a byte-wide, multiplexed data/address/control bus, it is described simply as the preferred bus architecture. (A152[8:23-31].) The specification never limits further bus discussion to this preferred multiplexed architecture. And, as the Board recognized, one of skill in the art would recognize that it is not so limited and that other important touted features in the 898 disclosure, including clocking schemes and writing blocks of data, could have been practiced on generic buses without a multiplexing interface. (A23.3; A1645-47[30-34].) The original claims of the 898 application also demonstrate that the inventors were in possession of generic bus claims. 28 The Board correctly

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recognized that certain original claims (73 and 91) required only a generic bus; not necessarily a multiplexed bus. (A23.3.) Claim 73, for example, required only a bus subsystem (A10584-85) and claim 91 required a plurality of external bus lines (A10594), but both were silent as to whether the claimed bus is multiplexed. Micron essentially complains that neither of these claims was directed to the bus itself (Micron Br. 54), but that assertion applies even more strongly to claims 26 and 28 on appeal, since they also do not recite a bus. (See A23.4 (distinguishing ICU Medical because here claims 26 and 28 do not require a bus at all).) Micron similarly states that only one prior-art reference (U.S. Patent No. 4,247,817 to Heller) discussed in the specification does not discuss a multiplexed bus and asserts that Heller is distinguishable because it is directed to parts of the invention other than the bus. (Micron Br. 56.) But claims 26 and 28, like Heller, are also directed to parts of the invention other than the bus. Thus, Microns alleged distinction actually proves Rambuss point, that the invention claimed in claims 26 and 28 are supported by the original specification and do not require a multiplexed bus. (See A23.4.) In sum, Microns alleged alternative ground for affirmance based on JEDEC and Park fails because Micron has raised an issue not within the scope of its reexamination and because claims 26 and 28 are entitled to their original April 1990 priority date, predating both references. This Court has twice held a generic 29

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bus to be supported by the specification, and the examiners and Boards decisions and the specification itself all support such a holding. III. CONCLUSION For the foregoing reasons and those explained in Rambuss opening brief, this Court should reverse the Boards decision finding the 916 patent invalid as anticipated and reinstate the examiners finding of no anticipation.

Dated: August 26, 2013

Respectfully submitted,

/s/ James R. Barney J. Michael Jakes James R. Barney Molly R. Silfen Aidan C. Skoyles FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER, LLP 901 New York Avenue, NW Washington, DC 20001 (202) 408-4000 Attorneys for Appellant Rambus Inc.

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CERTIFICATE OF COMPLIANCE I certify that the foregoing REPLY BRIEF FOR RAMBUS INC. contains 6,827 words as measured by the word-processing software used to prepare this brief.

Dated: August 26, 2013

Respectfully submitted,

/s/ James R. Barney J. Michael Jakes James R. Barney Molly R. Silfen FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER, LLP 901 New York Avenue, NW Washington, DC 20001 (202) 408-4000

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CERTIFICATE OF SERVICE I hereby certify that copies of the foregoing REPLY BRIEF FOR RAMBUS INC. were served upon registered counsel by operation of the Courts CM/ECF system on this 26th day of August, 2013. Henry A. Petri, Jr. Novak Druce Connolly Bove + Quigg, LLP 1875 Eye Street, NW, 11th Floor Washington, DC 20001 henry.petri@novakdruce.com

/s/ Kay Wylie