- 1 -

Transient Operation of Grid-connected Voltage Source Converter Under

Unbalanced Voltage Conditions
Giuseppe Saccomando Jan Svensson
Department of Electric Power Engineering
Chalmers University of Technology
SE- 41296, Gothenburg, Sweden
jan.svensson@elkraft.chalmers.se
Abstract- In this paper, the operation of shunt-connected
Voltage Source Converters under unbalanced voltage conditions
is investigated. The attention focuses on voltage dips, thus on
transient operation. The importance of using a fast and accurate
method for detection of sequence components of the grid voltage
affected by a fault is emphasized. Four different sequence-
detection techniques are presented and compared on the basis of
their transient response. Three different current controllers for
VSC are implemented and compared in both cases of constant
and regulated dc-link voltage. In the latter case, the
corresponding dc-link voltage controllers are described. The
operation of the VSC equipped with the different current
controllers is analyzed with constant-power and fluctuating-
power loads. Results obtained with different type of loads
demonstrate that the optimal choice of the controller depends on
the expected application.
I. INTRODUCTION
The rapid increase of voltage and power ratings of semiconductor
valves is leading to a wide application of forced-commutated
Voltage Source Converters (VSCs) connected to the grid, both at
transmission and distribution levels. Interesting applications are
wind power plants (see Fig.1), adjustable speed drives using back-
to-back converters, HVDC transmission and custom power devices.
Benefits of using VSCs are sinusoidal currents, high current
bandwidth, controllable reactive power to regulate power factor or
bus voltage level and minimize resonances between the grid and the
converter.
A major drawback when using grid-connected VSCs is their
sensitiveness to grid disturbances. This is especially true for variable
speed wind turbines, which are often located in rural areas and
connected to the grid by long overhead lines, easily subject to faults.
Short-duration grid disturbances often result in forced stoppage of
the turbine, thus in production losses. An even more demanding
application is voltage sag mitigation by using a dynamic voltage
restorer (DVR) [1], where a shunt-connected VSC can be used to
supply power to the dc-link. In this application, the shunt-connected
VSC is mainly required to operate during faults. Moreover, the
power required by the DVR can fluctuate much. For these reasons, a
robust controller that can ensure correct operation of the VSC also
during disturbed supply condition is needed.
In the wide range of power quality disturbances, the interest focuses
on voltage dips, which can severely affect the performance of the
VSC. A voltage dip is a drop in voltage with duration between one
half-cycle and one minute [2], which is in most cases caused by a
short-circuit fault. A complete classification of voltage dips has been
carried out by Bollen [3]. Most faults result in dips characterized not
only by a positive-sequence voltage component, but also by
negative- and zero-sequence voltage components. Thus, a controller
capable of handling steps in both positive and negative sequence
components is needed. However, the zero-sequence component is
disregarded here, since only three-wire systems are analyzed.
The current controller (CC) of VSC can be designed to provide high
performance under normal operating conditions of the grid by only
using positive-sequence components [4]. Under unbalanced
conditions, sinusoidal and balanced currents can be obtained by
choosing a high sampling frequency. However, the dc-link voltage
will still ripple with twice the grid frequency. Otherwise, the dc-link
voltage can be controlled to be constant, but then the grid currents
will be unsymmetrical.
For inverter and rectifier operation, the main concern is normally to
minimize the dc-link voltage ripple. For this purpose, different CCs
have been proposed, which use phase-sequence components to deal
with unbalanced grid conditions. Reference [5] uses a current
controller in the positive synchronous reference frame (SRF), to
which the positive-sequence grid voltage is fed. Reference [6] uses
two different CCs for the two sequence components together with a
dc-link voltage controller based on instantaneous active and reactive
power. With this arrangement, steady-state cancellation of the
voltage ripple is obtained. However, in [6] the controller is only
operating in steady state and in [5] the method to separate the
positive and negative sequence components is not described.
In this paper, different CCs for shunt-connected VSC are
investigated in order to withstand voltage dips. The attention focuses
on transient operation. Both cases of constant and regulated dc-link
voltage are considered. In the latter case, both constant-power and
fluctuating-power loads are investigated. Moreover, four different
sequence-detection methods are presented and compared, on the
basis of their transient response.
estimator ) (k
R L
dc
t
u
) (
+

3
i ) (t
2
i ) (t
) (t
1
i
) (
3
t e
) (
2
t e
) (
1
t e
3
u ) (t
2
u ) (t
) (t
1
u

+
+
+
C
PWM

) (k
) (
e
) (k
) (t sw
i t) (
dc
dc-link VSC Rectifier Line Filter Grid

Generator
Turbine
sample and hold
3/2
sample and hold
3
i t) (
v
) (k
) (
i
2 2
dc
k u ) (
i k) (
dc
Vector Current Controller
+
Dc-link Voltage
Controller
G
Fig.1. Grid-connected VSC in variable-speed wind turbine application.
II. DETECTION METHODS OF SYMMETRICAL COMPONENTS
Correct operation of VSC controllers during grid disturbances
requires a fast and accurate on-line detection of positive and
2419
0-7803-7116-X/01/$10.00 (C) 2001 IEEE
- 2 -
negative phase-sequence components. In this Section, four
on-line sequence separation methods (SSMs) implemented in
rotating frames are analyzed. These methods are based on
notch-filter; band-stop filter (BS); low-pass filter (LP) and
delayed signal cancellation (DSC) [7]. For all detection
methods, the grid frequency
N
f is 50 Hz and the sampling
time
s
T is 200 s. The transformation angle ) (k is
synchronized with the grid flux vector and is not affected by
the applied dips.
Positive sequence components appear as dc quantities in the
dqp-frame rotating positively with the grid angular frequency,
while negative sequence components appear as 100 Hz
components. On the contrary, in the dqn-frame, rotating
clockwise with the grid angular frequency, positive sequence
components appear as 100 Hz quantities while the negative
ones appear as dc components. Thus, sequence components
can be detected using filters that cut-off the second order
harmonic.
delayed
by T/4
-
+
+
dq
n
dq
p 1/2
1/2
3/2 j
+
e
-j
e
j dq
n
dq
p
Notch
Notch 3/2
3/2
e
-j
e
j dq
n
dq
p
Band stop
Band stop
3/2
e
-j
e
j
Low Pass
Low Pass
dq
n
dq
p
(a)
(b)
(c) (d)
e
-j
e
j
Fig.2. On-line sequence separation methods. (a): band stop filter, (b):
notch filter, (c): low-pass filter; (d): delayed signal cancellation.
A. Notch filter
The notch filter contains a deep notch at
0
in its frequency
response and has the following the transfer function [7,8]:
2 2 1
0
2 1
0
F
cos 2 1
cos 2 1
) ( G


+
+
=
z r rz
z z
K z
F

(1)
where
s
T
0 0
= and
F
K is the gain, set equal to
1 cos 2 1
cos 2 1
0
2
0
+
+
=

r r
K
F
(2)
in order to obtain unity dc-gain.
Two step responses, using r=0.95 and r=0.25, respectively,
have been simulated. The steady-state performance of the
filter with r=0.95 is satisfactory, since it cuts off the 100 Hz
component of the signal. However, the transient performance
is rather slow. The transient lasts almost 120 samples
(24 ms). The step response that uses r=0.25 shows a fast
transient response of 10 samples (2 ms). The gain
F
K
introduced to force the dc-component to unity is large (36),
thus producing large transient overshoots. It can be concluded
that the notch filter detects symmetrical components in the
dqp- and dqn-frame by cutting-off the second order harmonic
but it responds too slowly.
B. Band-stop and low-pass filters
The BS-filter can be designed so that its frequency response
characteristics are similar to the notch filter. Narrowing the
frequency range reduces the bandwidth, thus obtaining a slow
and oscillating transient response. A faster transient
performance has been obtained by using low-order filters. For
instance, the step response of a 1
st
order Butterworth BS-filter
with a stop band between 57 and 175 Hz has been calculated.
The filter cuts off the 100 Hz component, but the transient
response is rather slow, approximately 80 samples (16 ms).
To attenuate the 100 Hz component with LP-filters, the best
arrangement between the cut-off frequency and the filter
order has to be found: the lower the cut-off frequency, the
slower the transient response; the lower the order, the faster
the transient response. An example is a 6
th
order Butterworth
LP-filter with a cut-off frequency of 25 Hz. The 100 Hz
component is cancelled out, but the transient lasts
400 samples (80 ms). In conclusion, SSMs based on filtering
techniques are not suitable for applications in which high
bandwidth operation is demanded.
C. Delayed signal cancellation
An effective detection method both for its steady state and
transient performance is the DSC method. The method, when
applied on the grid voltages in the fixed -plane is defined
by the expressions
( ) ( ) 4 / j ) ( 5 . 0 ) (
) ( ) ( ) (
T t e t e t e
pos
+ =

(3)
( ) ( ) 4 / j ) ( 5 . 0 ) (
) ( ) ( ) (
T t e t e t e
neg
=

(4)
where T is the period of the fundamental frequency. The
proposed method implies delaying the signal by one fourth of
period at the fundamental frequency (5 ms), which constitutes
its inherent time delay. Positive and negative sequence
components thus obtained are then transformed into the dqp-
and the dqn-frame, respectively.
D. Dip responses
To test the effectiveness of the above-described SSMs, a
50 % B dip has been simulated. Due to the dip, the voltage
amplitude in phase one is reduced down to 50 %. In Fig. 5,
the positive q-components of the grid voltages are shown.
The SSM using LP-filters (Fig.5a) is very slow compared
with the other tested methods (note the different x-axis scale).
The SSMs using BS-filter (Fig.5b) and notch filter with
r=0.95 (Fig.5c), showing almost the same response, are not
fast enough. By using the notch filter with r=0.25 (Fig.5e),
steady state is established within 2 ms. Unfortunately, the
2420
- 3 -
highly amplified response during the transients causes
inappropriate effects, such as overmodulation. The best
solution has been found to be the method using the DSC
(Fig.5d) both for its accuracy and transient response. Thus,
the DSC has been adopted in the forthcoming simulations.
0 50 100 150 200 250
0.8
0.9
1
1.1
e
q
p


[
p
u
]
(a)
0 10 20 30 40 50 60
0.8
0.9
1
1.1
e
q
p


[
p
u
]
(b)
0 10 20 30 40 50 60
0.8
0.9
1
1.1
e
q
p


[
p
u
]
(c)
0 10 20 30 40 50 60
0.8
0.9
1
1.1
e
q
p


[
p
u
]
(d)
0 10 20 30 40 50 60
0.8
0.9
1
1.1
Time [ms]
e
q
p


[
p
u
]
(e)
Fig. 5: Positive sequence q-components of grid voltages during 50% B dip.
(Solid line) SSM dip response,(dotted line) ideal response. (a) LP-filter (6
th
order Butterworth, 25 Hz), (b) BS-filter (1
st
order Butterworth, 57 to
175 Hz), (c) notch filter (r=0.95), (d) DSC, (e) notch filter (r=0.25).
TABLE 1
SYSTEM PARAMETERS.
E=400 V=1 pu udc=650 V=1 pu fN=50 Hz
L =0.73 mH=0.1 pu R= 23 m=0.01 pu fs=2fsw=5 kHz
VCC: kp=3.7 (deadbeat) kI=
3
10 23

DVCC: kp=2.6 (70% of deadbeat) kI=

3
10 16

III. INVESTIGATED CURRENT CONTROLLERS

In this section three different CCs will be introduced. Two
controllers are implemented in the positive SRF and the third
uses both positive and negative SRFs. System parameters are
presented in Table 1. The used SSM is the DSC.
The first controller analyzed here, denoted as VCC, is
implemented in the positive SRF [9]. Its block scheme is
shown in Fig. 6. Active and reactive currents are controlled
independently of each other with a high bandwidth (even in
the overmodulation region). The controller uses dead-beat
gain and a Smith predictor with a state observer is used for
delay compensation. To prevent integration wind-up, back-
calculation of the current error is used.
To improve the performance under unbalanced condition, the
grid voltage is divided into positive and negative sequence
components. The CC uses only the positive sequence voltage.
The negative sequence grid voltage is directly added to the
reference voltage vector as shown in Fig.7. The abbreviation
is VCCF, where F stands for feedforward [4].
The third controller consists of two CCs that are implemented
in positive and negative SRF, respectively, as shown in Fig.8.
The controller tracks positive- and negative-sequence
reference currents. Both grid current and voltage are
separated into positive- and negative-sequence components
[5]. The abbreviation is DVCC, where D stands for dual.
2
3
PWM
* ) (

u
* ) 123 (
u
) (t sw
3
2
3
dqp

) (k
CC
in
positive SRF
) (k

dqp

dqp
) (
e
) (
i
* ) (dq
i
) (dq
i
) (dq
e
* ) (dq
u
VCC
2
2
2
2
2
2
Fig. 6: Block scheme of VCC that uses positive SRF.
) (k

dqp
) (
i
) (dq
i
+
SSM ) (
e
) (dqp
e
dqp

) (k
CC
in
positive SRF
) (dqn
e
)* (dq
i
+
* ) (dq
u
VCCF
2
3
PWM
* ) (

u
* ) 123 (
u
) (t sw
3
2
3
2
2
2
2
2
2
2
Fig. 7: Block scheme of VCCF that uses positive SRF and feedforward of
negative sequence grid voltage.
dqp

dqn
+
+
) (k ) (k
DVCC
) (dqp
e
) (dqn
e
) (dqn
i
) (dqp
i
* ) (dqp
i
* ) (dqn
i
) (
e
) (
i
CC
in
negative SRF
SSM
SSM
CC
in
positive SRF
2
3
PWM
* ) (

u
* ) 123 (
u
) (t sw
3
2
3
2
2
2
2
2
2
2
2 2
2
Fig. 8: Block scheme of DVCC that uses positive and negative SRF.
IV. OPERATION DURING DIPS
USING CONSTANT DC-LINK VOLTAGE
In this Section, the three controllers are investigated when
the dc-link voltage is constant and a 50 % B dip occurs at
20 ms and ends at 80 ms. The positive-sequence components
2421
- 4 -
of active and reactive reference currents are

qp
i =0.50 pu and

dp
i =0.20 pu, respectively. As shown in Fig.9, the phase
currents when using VCC are unbalanced during the dip,
whereas when using VCCF and DVCC they are balanced and
thus not affected by the dip. This proves that the controller
should deal both with positive and negative sequence
voltages to track the reference currents correctly when the dc-
link voltage is fixed.
0 10 20 30 40 50 60 70 80 90 100 110
0.4
0.2
0
0.2
0.4
0.6
i1
,

i2
,

i3

[
p
u
]
0 10 20 30 40 50 60 70 80 90 100 110
0.4
0.2
0
0.2
0.4
0.6
i1
,

i2
,

i3

[
p
u
]
0 10 20 30 40 50 60 70 80 90 100 110
0.4
0.2
0
0.2
0.4
0.6
i1
,

i2
,

i3

[
p
u
]
Fig. 9: VSC current during 50 % B dip using constant dc-link voltage.
(Top) VCC, (middle) VCCF, (bottom) DVCC.
TABLE 2
SYSTEM PARAMETERS FOR DC-LINK VOLTAGE CONTROLLER
kFF =0.81 kp,dc=0.55 (VCC) kp,dc=0.17 (DVCC)
C=550F (1.7 ms) TI,dc=2 ms (VCC) TI,dc=10 ms (DVCC)
V. CONTROL OF DC-LINK VOLTAGE
In most applications the grid-connected VSC must control
and keep the voltage of the dc-link constant independently of
the load behavior. In this configuration, called weak dc
grid, the link consists of a capacitor C . The current from the
capacitor to the VSC is denoted by
v
i and the load current is
denoted by
dc
i . Two dc-link voltage controllers, one for both
VCC and VCCF and one for DVCC, are presented here. Both
dc-link parameters are listed in Table 2.
A. Dc-link controller when using VCC and VCCF
This controller uses a PI-regulator to eliminate the
deviation between the reference dc-link voltage

dc
u and the
dc-link voltage
dc
u . To decrease the voltage fluctuations a
feed-forward, denoted by F.F., of the load current
dc
i is used.
The feed-forward gain is determined from power invariance
between ac and dc side of the VSC. The controller output
constitutes the reference active current

q
i for the CC. The
block scheme of the system including the dc-link is shown in
Fig.10. When deriving the parameters of the PI-controller, the
current response of the VSC is assumed to be instantaneous.
The poles of the closed-loop system are selected as double
poles. To obtain a stable response with minimum voltage
overshoot that is still free of damping, a factor of 7 . 0 = is
selected. If the capacitor size and the integral time are fixed,
the proportional gain can be calculated.
dc
u
dc
i

=
C

+
F.F.
+

+
dc
u
*
dc
u

*
dp
i
*
qp
i
v
i
v dc
i i

+
+
+

sample & hold

PI
dc-link voltage
controller
Fig.10: Dc-link voltage controller when using VCC and VCCF.
B. Dc-link controller when using DVCC
When using DVCC, the implemented dc-link voltage
controller is based on instantaneous active and reactive
power, which can be calculated on line by using the
instantaneous sequence components of voltage and current as
)) ( 2 sin( )) ( 2 cos( ) (
2 2 0
k P k P P k p
s c
+ + = (5)
)) ( 2 sin( )) ( 2 cos( ) (
2 2 0
k Q k Q Q k q
s c
+ + = (6)
In Eqs.(5) and (6), the coefficients
2 s
P ,
2 c
P ,
2 s
Q and
2 c
Q are
a function of voltage and current components and are non-
zero values in case of unbalance. By setting these coefficients
to zero (together with
0
Q , to obtain unity power factor), the
four current reference values to the DVCC are obtained. The
only non-zero coefficient,
0
P , is obtained as output of a PI-
controller, similar to that presented in the previous Section.
VI. OPERATION DURING DIP WITH DC-LINK VOLTAGE
CONTROLLER AND CONSTANT LOAD POWER
In this Section, the behavior of the system using dc-link
voltage controllers is investigated when the load current is
constant, such as for wind turbines. Both an ideal dip and a
measured dip are used.
A. Operation during ideal dip
To test the effectiveness of the dc-controllers during
unbalanced voltage conditions, a 50 % B dip has been
simulated. The current from the dc-link load is constant
0.5 pu. In Fig.11, dc-link voltage and phase currents for VCC
2422
- 5 -
and DVCC systems are shown. The results for the VCCF are
not shown because its performance has proven to be the same
as the VCC. The dip starts at 20 ms and ends at 180 ms. As
shown, the dc-voltage ripple is almost zero for the DVCC
system. However, a transient can be noticed at the start and
end of the dip due to the delay introduced by the DSC. For
the VCC system, the dc-voltage ripple oscillates with twice
the grid frequency and the amplitude of the ripple is 4 %.
This demonstrates the limit of the VCC system in presence of
negative sequence components. Moreover, the phase currents
for the VCC system are unbalanced and not sinusoidal. The
phase currents of the DVCC system are also unbalanced but
are still sinusoidal.
0 50 100 150 200 250
0.94
0.96
0.98
1
1.02
1.04
1.06
Time [ms]
u
d
c

[
p
u
]
0 50 100 150 200 250
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
Time [ms]
i
1
,

i
2
,

i
3

[
p
u
]
0 50 100 150 200 250
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
Time [ms]
i
1
,

i
2
,

i
3

[
p
u
]
Fig.11: Dip response for VCC and DVCC. (Top) dc-voltage: DVCC solid
and VCC dotted. (Left) phase currents of VCC. (Right) phase currents of
DVCC.
B. Operation during measured dip
The performance has also been analyzed by utilizing actual
voltage waveforms during an unbalanced voltage dip. These
data, recorded by a power quality monitor, have been used as
input voltages in the simulations. Three-phase voltage
waveforms of the recorded dip, together with positive and
negative sequence components in the dq-plane, are presented
in Fig.12. In Fig.13, dc-link voltage and phase currents are
shown for the VCC and the DVCC systems during the
measured dip. It can be concluded that the response to the
measured dip is the same as for the ideal dip in Section IV.A.
However, the dc-voltage transient overshoot due to the DSC
is smaller compared with the dip in Fig.11, because the
voltage variation is not sudden in reality and thus the DCS
operates more effectively.
0 20 40 60 80 100 120
1
0.5
0
0.5
1
Time [ms]
e
1


e
2


e
3


[
p
u
]
0 20 40 60 80 100 120
0
0.2
0.4
0.6
0.8
1
Time [ms]
e
d
p
,

e
q
p


[
p
u
]
e
dp
e
qp
0 20 40 60 80 100 120
0.1
0.05
0
0.05
0.1
0.15
0.2
Time [ms]
e
d
n
,

e
q
n


[
p
u
]
e
dn
e
qn
Fig.12: Measured dip. (Top) phase voltages. (Left) positive dq-components.
(Right) negative dq-components.
0 20 40 60 80 100 120
0.95
1
1.05
Time [ms]
u
d
c

[
p
u
]
0 20 40 60 80 100 120
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
Time [ms]
i
1
,

i
2
,

i
3

[
p
u
]
0 20 40 60 80 100 120
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
Time [ms]
i
1
,

i
2
,

i
3

[
p
u
]
Fig.13: Response for VCC and DVCC when using measured dip. (Top) dc-
voltage: DVCC solid and VCC dotted. (Left) phase currents of VCC. (Right)
phase currents of DVCC.
V. OPERATION DURING DIP WITH DC-LINK VOLTAGE
CONTROLLER AND FLUCTUATING LOAD POWER
In this Section, the behavior of the VSC systems is
investigated when using dc-link voltage controllers.
Moreover, the load current changes heavily because the VSC
systems provide active power to an ideal DVR. Both an ideal
dip and a measured dip are used. The current through the
DVR is 1.0 pu and the power factor is 0.9 inductive.
A. Operation during ideal dip
A 50 % B dip has been simulated. In Fig.14, the dc-link
current to the DVR and the dc-link voltages for the VCC and
the DVCC systems are shown. The dip starts at 30 ms and
ends at 250 ms.
2423
- 6 -
As shown, the dc-link voltage ripple is almost equal for VCC
and DVCC. When the dip ends, the dc-voltage ripple of the
DVCC decreases oscillating very slowly compared to the
VCC. This is due to the error introduced by the DSC, which
does not manage to follow the fast variations of the positive
and negative sequence current.
0 50 100 150 200 250 300 350 400 450
0
0.1
0.2
0.3
0.4
0.5
0.6
Time [ms]
i
d
c

[
p
u
]
0 50 100 150 200 250 300 350 400 450
0.96
0.98
1
1.02
1.04
1.06
Time [ms]
u
d
c

[
p
u
]
Fig.14: (top) Dc-link current and (bottom) Dc-link voltages during DVR
load. (bottom, solid) VCC, (bottom, dotted) DVCC. A dip of type B with a
magnitude of 50 % has been simulated.
B. Operation during measured dip
In Fig.15, dc-link current and voltage for VCC and DVCC
systems during the measured dip are shown. The response is
the same as for the ideal dip, but the envelope of the voltage
ripple decreases very slowly after the dip has ended. To
conclude, when the power fluctuates quickly, such as in a
DVR application, VCC shows a better performance than
DVCC.
VI. CONCLUSIONS
In this paper, transient operation of a grid-connected VSC
under unbalanced voltage conditions has been analyzed. The
importance of using fast and accurate sequence-detection
techniques has been emphasized. Four methods for sequence
separation have been investigated. The delayed signal
cancellation method gives best transient performance.
Three current controllers have been described, along with
corresponding dc-link voltage controllers. Their performance
has been evaluated by using both ideal and measured voltage
dips. For constant load power, the DVCC controller has much
better performance compared with the other controllers.
However, when the load power fluctuates, VCC and VCCF
show a better performance than DVCC. When the dc-link
voltage is fixed, the controller should deal both with positive
and negative sequence voltages to track the reference currents
correctly. The type of controller has thus to be chosen
according to the application.
0 20 40 60 80 100 120
0
0.1
0.2
0.3
0.4
0.5
0.6
Time [ms]
id
c

[
p
u
]
0 20 40 60 80 100 120
0.95
1
1.05
Time [ms]
u
d
c

[
p
u
]
Fig.15: (top) Dc-link current and (bottom) Dc-link voltages during DVR
load. (bottom, solid) VCC, (bottom, dotted) DVCC. A real measured dip has
been used.
REFERENCES
[1] N. Hingorani, Introducing Custom Power, IEEE Spectrum, Vol. 32,
No. 6, June 1995, pp.41-48.
[2] IEEE Recommended Practice for Monitoring Electric Power Quality,
IEEE Std.1159-1995, New York, IEEE, 1995.
[3] M.H.J. Bollen, Understanding power quality problems: voltage sags and
interruptions, New York, IEEE Press, 1999.
[4] R. Ottersten, J. Svensson, Vector Current Controlled Voltage Source
Converter - Deadbeat Control and Overmodulation Strategies, IEEE
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Espoo, Finland, August 26-27, 1998, pp. 65-70.
[5] P. Rioual; H. Pouliquen, J-P. Louis, Regulation of a PWM Rectifier in
the Unbalanced Network State Using a Generalized Model, IEEE
Trans. on Power Electronics, Vol. 11, No. 3, May 1996, pp. 495-502.
[6] H.-S. Song; K. Nam, Dual Current Control Scheme for PWM
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[7] T.-N. Le, Kompensation schnell vernderlicher Blindstrme eines
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[8] K. J. strm, B. Wittenmark, Computer-controlled Systems: Theory and
Design, 2
nd
Ed., Prentice Hall, Englewood Cliffs, NJ, 1990.
[9] D. Basic, V.S. Ramsden, P.K. Muttik, Selective Compensation of
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