Yuan

COMPUTER METHODS FOR
ANALYSIS OF MIXED-MODE
SWITCHING CIRCUITS
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COMPUTER METHODS FOR
ANALYSIS OF MIXED-MODE
SWITCHING CIRCUITS
by
Fei Yuan
Associate Professor
Department of Electrical and Computer Engineering
Ryerson University
Toronto, Ontario, Canada
Ajoy Opal
Professor
Department of Electrical and Computer Engineering
University of Waterloo
Waterloo, Ontario, Canada
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Contents
List of Figures xi
List of Tables xxiii
Preface xxvii
Acknowledgments xxxi
Part I The Fundamentals

1. AN OVERVIEW OF
MIXED-MODE SWITCHING CIRCUITS 3
1 Classification 3
2 Switched Capacitor Techniques 4
3 Switched Current Techniques 6
4 Characteristics of Mixed-Mode Switching Circuits 9
2. COMPUTER FORMULATION OF
MIXED-MODE SWITCHING CIRCUITS 13
1 Modeling of Switches 13
1.1 Full-Transistor Models 14
1.2 Voltage-Modulated Resistor Models 14
1.3 Ideal Switch Models 15
2 Formulation Methods for Mixed-Mode Switching Circuits 16
2.1 A Historical Perspective 16
2.2 External Clocks 19
2.3 Conventions 19
2.4 Sub-Circuits 20
2.5 Matrix Stamps of Elements Without Memory 21
2.5.1 Controlled Sources 21
vi COMPUTER METHODS FOR MIXED-MODE SWITCHING CIRCUITS
2.5.2Ideal Switches 22
2.6 Matrix Stamps of Elements With Memory 23
2.6.1Capacitors 24
2.6.2Inductors 28
2.7 Formulation of Circuits with Externally Clocked
Switches 28
2.8 Formulation of Circuits with Internally Controlled
Switches 31
2.9 Formulation of Circuits with Both Externally Clocked
and Internally Controlled Switches 32
3 Summary 33
3. NETWORK FUNCTIONS OF
TIME-VARYING CIRCUITS 35
1 Transfer Functions of Linear Time-Varying Systems 36
1.1 Linear Time-Varying Systems 36
1.2 Linear Periodically Time-Varying Systems 37
2 Transfer Functions of Nonlinear Time-Varying Systems 40
2.1 Volterra Functional Series 40
2.2 Multi-Frequency Network Functions 41
2.3 Multi-Frequency Transfer Functions 42
3 Frequency Response of Nonlinear Time-Varying Systems 43
4 Frequency Response of Nonlinear Periodically Time-Varying
Systems 44
5 Summary 48
4. NUMERICAL INTEGRATION OF
DIFFERENTIAL EQUATIONS 53
1 Linear Single-Step Predictor-Corrector Algorithms 54
2 Linear Multi-Step Predictor-Corrector Algorithms 57
3 Integration Using Numerical Laplace Inversion 59
3.1 Padé Polynomials 60
3.2 Numerical Laplace Inversion 62
3.3 Multi-Step Numerical Laplace Inversion 69
4 Summary 79
Contents vii
Part II Time Domain Analysis

5. INCONSISTENT INITIAL CONDITIONS 83
1 Inconsistent Initial Conditions 84
2 Numerical Laplace Inversion Based Two-Step Algorithm 85
3 Backward Euler Based Algorithms 90
3.1 Two-Forward-Step Algorithm 92
3.2 Two-Step Algorithm 96
3.3 Four-Step Algorithm 97
3.4 Two-Step Algorithm for Linear Circuits 98
4 Taylor Series Based Algorithm 99
5 Volterra Functional Series Based Algorithm 102
6 Existence of Dirac Impulses at Switching Instants 103
6.1 Dirac Impulses in Linear Circuits 104
6.2 Dirac Impulses in Nonlinear Circuits 106
7 Summary 107
6. SAMPLED-DATA SIMULATION OF
PERIODICALLY SWITCHED
LINEAR CIRCUITS 109
1 Sampled-Data Simulation of Periodically Switched Linear
Circuits 110
3 Time-Domain Sensitivity 119
4 Inconsistent Initial Conditions of Sensitivity Networks 121
5 Statistical Analysis 122
5.1 Introduction 122
5.2 First-Order Second-Moment Method 123
6 Noise Analysis 125
6.1 Modeling of White Noise 126
6.2 The Algorithm 129
6.3 Examples 130
7 Clock Jitter 131
8 Summary 134
1 Computation of 135
viii COMPUTER METHODS FOR MIXED-MODE SWITCHING CIRCUITS
NONLINEAR CIRCUITS 139
1 Multi-Linear Theory 140
2 Volterra Circuits 144
3 Sampled-Data Simulation of Periodically Switched Nonlinear
Circuits 146
5 Sensitivity of Periodically Switched Nonlinear Circuits 152
6 Discussion 155
6.1 Stability 155
6.2 The Maximum Step Size 155
6.3 Accuracy 155
6.3.1 The Order of Taylor Series Expansion 156
6.3.2 The Order of Volterra Series Expansion 157
6.3.3 The Order of Interpolating Fourier Series 157
6.3.4 Simulation Window 158
6.3.5 Error Propagation 160
7 Examples 162
7.1 Time-Invariant Nonlinear Circuits 162
7.2 Switched Capacitor Integrator with Nonlinear Op
Amp 166
7.3 General Periodically Switched Nonlinear Circuits 168
8 Summary 172
CIRCUITS WITH INTERNALLY
CONTROLLED SWITCHES 177
1 Internally Controlled Switches and Switching Variables 178
1.1 Diodes 178
1.2 MOSFETs 179
1.3 Static CMOS Inverters 180
1.4 Comparators 181
2 Switching Instants 181
4 Examples 183
5 Summary 189
Contents ix
OVER-SAMPLED SIGMA-DELTA
MODULATORS 191
1 Introduction 192
2 Modeling of Clocked Quantizers 194
3 Modeling of Unclocked Quantizers 194
4 Modeling of Digital-to-Analog Data Converters 196
5 Modeling of Other Blocks 196
6 Simulation Methods 197
7 Examples 198
8 Summary 201
Part III Frequency Domain Analysis

10. ADJOINT NETWORK OF PERIODICALLY
SWITCHED LINEAR CIRCUITS 207
1 Tellegen’s Theorem 208
2 Inter-reciprocity 211
3 Adjoint Network 212
3.1 Ideal Switches 212
3.2 Resistors 212
3.3 Capacitors and Inductors 213
3.4 Controlled Sources 214
3.5 Operational Amplifiers 215
4 Transfer Function Theorem 216
5 Frequency Reversal Theorem 220
6 Examples 223
7 Summary 225
11. FREQUENCY DOMAIN ANALYSIS OF
LINEAR CIRCUITS 229
1 Frequency Response 230
2 Sensitivity Analysis 235
2.1 Direct Sensitivity Analysis 237
2.2 Sensitivity Analysis Using Adjoint Network 240
2.3 Sensitivity Analysis Using Sensitivity Network 250
2.4 Numerical Examples 255
x COMPUTER METHODS FOR MIXED-MODE SWITCHING CIRCUITS
3 Group Delay Analysis 260

4 Noise Analysis 264
4.1 Noise Characterization 266
4.2 Noise Sources 275
4.3 Noise Equivalent Circuits 277
4.4 The Algorithm 284
4.5 Numerical Examples 286
5 Statistical Analysis 293
6 Summary 297
12. FREQUENCY DOMAIN ANALYSIS OF
NONLINEAR CIRCUITS 303
1 Fundamentals 306
1.1 Harmonic Distortion 306
1.2 Intermodulation Distortion 307
2 Distortion Analysis of Periodically Switched Nonlinear
Circuits 309
3 Harmonic Distortion 314
3.1 The First-Order Volterra Circuit 314
3.2 The Second-Order Volterra Circuit 315
3.3 The Third-Order Volterra Circuit 316
3.4 The Fold-Over Effect 318
4 Intermodulation Distortion 318
4.1 The First-Order Volterra Circuit 319
4.2 The Second-Order Volterra Circuit 320
4.3 The Third-Order Volterra Circuit 320
5 Examples 321
5.1 Modulator 321
5.2 Stray-Insensitive Switched Capacitor Integrator 322
5.3 Switched Capacitor Integrator With Nonlinear Op
Amp 325
6 Summary 332
List of Figures
1.1 Implementation of resistors using switched capacitors. 5

1.2 Implementation of resistors using stray-insensitive
switched capacitors (the dotted line shows the con-
nection of the parasitic bottom plate-substrate ca-
pacitor) . 6
1.3 Stray-insensitive switched capacitors integrators. 7
1.4 Stray-insensitive switched capacitors biquad. 7
1.5 Switched current memory cells. The first genera-
tion of switched current memory cell is sensitive to
the effect of mismatches whereas the second gen-
eration switched current memory cell is mismatch-free. 8
1.6 Switched current integrators. 9
1.7 Switched current biquad. 10
2.1 Ideal switch model. 15
2.2 Test circuit for demonstrating the difference be-
tween voltage-modulator resistor switch model and
ideal switch model. 16
2.3 Time domain response of the circuit of Fig.2.2 with
ideal and voltage-modulated resistor switch mod-
els. The ON-resistance of voltage-modulated re-
sistor switch is varied from 0 to with
step. 17
xii COMPUTER METHODS FOR MIXED-MODE SWITCHING CIRCUITS
2.4 Clock phases in a clock period represents the

clock phase). 19
2.5 Circuits with externally clocked switches with a to-
tal of K phases in a clock period are represented by
K time-invariant sub-circuits operated in a time-
interleaved fashion. 21
2.6 Matrix stamps of nonlinear controlled sources. 23
2.7 Matrix stamps of ideal switches. 24
2.8 Matrix stamps of linear and nonlinear capacitors. 26
2.9 Matrix stamps of linear and nonlinear inductors. 29
2.10 Switching time is determined from solving
numerically. 32
3.1 Foldover effect. 38
3.2 The spectrum of the output of nonlinear periodi-
cally time-varying system to input 48
3.3 The spectrum of the output of nonlinear periodi-
cally time-varying systems to input
49
4.1 Stable region of Euler formulae. The boundary of
the unit circle is also included in the stable region. 57
4.2 Linear single-step and linear multi-step predictor-
corrector algorithms. 59
4.3 Dependence of the relative error of the exact solu-
tion and that from numerical Laplace inversion of
the unit step function with {N, M} = {2, 4}
on the step size. 67
4.4 Dependence of the relative error of the exact so-
lution and that from numerical Laplace inversion
of exponentially decaying function with {N, M} =
{2, 4} on the step size. 68
4.5 RC network. 68
List of Figures xiii
4.6 Dependence of the relative error of the exact solu-

tion and that from numerical Laplace inversion of
RC Network of Fig.4.5 with {N, M} = {2, 4} on
the step size. 69
4.7 Relative error of the response of the RC network
of Fig.4.5 using stepping and non-stepping algorithms. 73
4.8 Piece-wise linear approximation of a given input
waveform. is the given input wave form and
is the piecewise linear approximation of
is chosen such that Nyquist sampling theorem is
satisfied. 74
5.1 Test circuit. 85
5.2 Relative error of the exact response of the circuit
of Fig.5.1 and the response of the circuit computed
from numerical Laplace inversion. 87
5.3 Relative error between the exact value of
of the network of Fig.5.1 and that computed from
two-step algorithm with {N, M} = {2, 4}. 88
5.4 Example circuit for two-step algorithm 90
5.5 Test circuit for inconsistent initial conditions. 93
5.6 Comparison of the relative errors of algorithms for
computing the consistent initial conditions of the
circuit of Fig.5.1. 102
6.1 Piecewise-linear approximation of an arbitrary in-
put waveform. is the input wave form and
is the piecewise linear approximation of
with step 114
6.2 Graphical illustration of two-step algorithm (one
forward step and one backward step), is dis-
continuous at but continuous at 116
6.3 Periodically switched linear circuit example. 118
6.4 Response of the circuit of Fig.6.3. Legends:
Sampled-data simulation, – Exact. 119
xiv COMPUTER METHODS FOR MIXED-MODE SWITCHING CIRCUITS
6.5 White noise is represented by a train of pulses with

random amplitude. 126
6.6 Equivalent noise bandwidth. 127
6.7 Time domain waveform of the thermal noise volt-
age of the resistor with
128
6.8 Spectrum of the thermal noise of the resistor with
512 samples. 129
6.9 Switched capacitor integrator. 131
6.10 Power spectral density of the output noise of the
switched capacitor integrator of Fig.6.9. Legends
measurement, – this book. 132
6.11 Clock jitter is represented by step variation
where 133
7.1 Multi-linear equivalent circuits of nonlinear voltage-
controlled voltage source. (a) first-order, (b) second-
order, and (c) third-order. 142
7.2 The multi-linear equivalent circuits of nonlinear el-
ements in phase of periodically switched nonlin-
ear circuits. 144
7.3 Volterra circuits of periodically switched nonlinear
circuits. 147
7.4 Interpolation window and approximation of the in-
put of the second-order Volterra circuits using in-
terpolating Fourier series. 148
7.5 Conversion of aperiodic sequence to periodic se-
quence using transformation. 159
7.6 Propagation of interpolating error. 161
7.7 Current-mirror amplifier. 163
7.8 Response of the current-mirror amplifier of Fig.7.7. 164
7.9 Circuit with nonlinear conductor. 165
7.10 Response of the circuit of Fig.7.9. The numerical
numbers in the figure are the amplitude of the input. 166
List of Figures xv
7.11 Absolute error between the response obtained from
sampled-data simulation and that from LSS-PC of
the circuit of Fig.7.9. 167
7.12 Dependence of the error on the order of interpola-
tion used in sampled-data simulation of the circuit
of Fig.7.9. 167
7.13 Comparison of CPU time of sampled-data simula-
tion and LSS-PC algorithms of the circuit of Fig.7.9. 168
7.14 Switched-capacitor integrator with nonlinear oper-
ational amplifier. 169
7.15 Response and its sensitivity with respect to
of the Switched-capacitor integrator with non-
linear operational amplifier of Fig.7.14. 170
7.16 Sensitivity of of the switched-capacitor integra-
tor with nonlinear operational amplifier of Fig. 7.14
with respect to using both sampled-data simu-
lation and brute-force methods. Legends : Brute-
force; – Sampled-data simulation. 171
7.17 General periodically switched nonlinear circuit. 171
7.18 Response of the circuit of Fig.7.17. The results
from sampled-data simulation compare well with
those from PSPICE simulation at time points other
than switching instants. Legends : PSPICE sim-
ulation; – Sampled-data simulation. 172
7.19 Normalized difference of the response of the circuit
of Fig.7.17 obtained from sampled-data simulation
and that from PSPICE. The maximum normalized
difference is below 0.5%. 173
7.20 Charge conservation at the switching instants of
the circuit of Fig.7.17. Legends : total charge
immediate before switching; + total charge imme-
diate after switching. 174
xvi COMPUTER METHODS FOR MIXED-MODE SWITCHING CIRCUITS
7.21 Sensitivity of of the circuit of Fig.7.17 with

respect to Legends : Brute-force; – Sampled-
data simulation. 175
7.22 Sensitivity of of the circuit of Fig. 7.17 with
respect to Legends : Brute-force; – Sampled-
data simulation. 175
8.1 Internally controlled switches - diodes. 179
8.2 Internally controlled switches - MOSFETs. 180
8.3 Internally controlled switches - static CMOS inverters. 180
8.4 Internally controlled switches - comparators. 182
8.5 Bulk linear voltage regulator (step-down chopper). 184
8.6 Linear voltage regulator 186
8.7 Linear voltage regulator 186
9.1 Configuration of clocked single-bit first-order sigma-
delta modulator. 192
9.2 Quantizers. 193
9.3 Modeling of clocked quantizers with no dead zone.
is the input and is the output. 195
9.4 Typical configurations of single-bit DACs. Q is the
output of the quantizers 197
9.5 Single-bit second-order continuous-time over-sampled
sigma-delta modulator. 199
9.6 Time-domain response of the single-bit second-order
continuous-time over-sampled sigma-delta modu-
lator of Fig.9.5. 199
9.7 Spectrum of the response of the single-bit second-
order continuous-time over-sampled sigma-delta mod-
ulator of Fig.9.5. 200
9.8 Single-bit second-order switched capacitor over-sampled
sigma-delta modulator. This modulator is a switched
capacitor implementation of the continuous mod-
ulator of Fig.9.5. 201
List of Figures xvii
9.9 Spectrum of the response of the single-bit second-

order switched capacitor over-sampled sigma-delta
modulator of Fig.9.8. 202
9.10 Signal-to-noise ratio of the single-bit second-order
switched capacitor over-sampled sigma-delta mod-
ulator of Fig.9.8 (Ideal – ideal operational ampli-
fier; Nonideal – operational amplifier with gain-
bandwidth 500kHz.) 203
10.1 Time reversal of a periodically switched linear cir-
cuit N and its adjoint network 211
10.2 Equivalent circuit of operational amplifier with single-
pole model and its adjoint network. 215
10.3 Elements and their counterparts in the adjoint network. 216
10.4 Transfer function theorem - voltage output. 217
10.5 Transfer function theorem - current output. 217
10.6 Frequency reversal theorem. 220
10.7 Stray-insensitive switched capacitor integrator. 224
10.8 Adjoint network of the stray-insensitive switched
capacitor integrator of Fig.10.7. 225
10.9 Switched capacitor band pass filter. 226
10.10 Adjoint network of the switched capacitor band
pass filter of Fig. 10.9. 227
11.1 Fifth-order elliptic switched capacitor low pass filter. 236
11.2 Frequency response of the fifth-order elliptic switched
capacitor low pass filter of Fig.11.1. 238
11.3 The passband of the frequency response of the fifth-
order switched capacitor low pass filter of Fig.11.1.
Dashed line - ideal operational amplifier with fre-
quency characteristics given by Solid
line - non-ideal operational amplifier with frequency
characteristics given by 239
11.4 Error of discretization. 242
xviii COMPUTER METHODS FOR MIXED-MODE SWITCHING CIRCUITS
11.5 Sensitivity analysis of periodically switched linear

circuits using adjoint network. 243
11.6 Fold-over effect in sensitivity analysis of periodi-
cally switched linear circuits. 251
11.7 Sensitivity networks of basic elements. 253
11.8 Sensitivity network of periodically switched linear
circuits. (a) Original circuit N, (b) Sensitivity net-
works (c) Adjoint network of N
and 254
11.10 Sensitivity of the response of stray insensitive switched
capacitor integrator of Fig.11.9 to (real part). 257
11.11 Sensitivity of the response of stray insensitive switched
capacitor integrator of Fig.11.9 to (imaginary part). 257
11.12 Normalized sensitivity of the response of magni-
tude of the stray insensitive switched capacitor in-
tegrator of Fig.11.9 to 258
11.13 Response of stray insensitive switched capacitor in-
tegrator of Fig.11.9 and that of its adjoint network
(20 sidebands are plotted). 259
11.14 Switched capacitor band pass filter. 260
11.15 Sensitivity of the response of the switched capaci-
tor band pass filter of Fig.11.14 to (Real part). 261
11.16 Sensitivity the response of the switched capacitor
band pass filter of Fig.11.14 to (Imaginary part). 261
11.17 Normalized sensitivity of the response of the switched
capacitor band pass filter of Fig.11.14 to 262
11.18 Relative difference between the sensitivity of Fig.11.14
from adjoint network analysis and that from direct
sensitivity analysis. 263
11.19 Response of the switched capacitor band pass filter
of Fig.11.14 and that of its adjoint network. 264
11.20 Fifth-order switched capacitor low pass filter. 265
List of Figures xix
11.21 Group delay of the fifth-order switched capacitor

low pass filter of Fig.11.20. 267
11.22 Sampling of stationary random signal. 272
11.23 Aliasing effect of band-limited noise signals. The
bandwidth of the input noise is and the band-
width of the circuit is assumed to be infinite with
unity gain. 274
11.24 Low-frequency noise equivalent circuit of resistors.
(a) Norton equivalent, (b) Thevenin equivalent. 278
11.25 Noise equivalent circuit of BJTs in the forward ac-
tive region. is the thermal noise of the base
resistance is the shot noise at the emitter-
base pn-junction, represents the shot noise and
flicker noise in the emitter-base region. 279
11.26 Low-frequency noise equivalent circuit of MOSFET
switches. 282
11.27 Equivalent noise circuit of MOSFET transistors in
saturation. 283
11.28 Noise equivalent circuits of operational amplifiers.
(a) Complete noise equivalent circuit, (b) Simpli-
fied noise equivalent circuit. 284
11.29 Switched capacitor low-pass. 288
11.30 Power spectral density of the switched capacitor
low-pass of Fig.11.29. Legends: measurement; –
this book. 288
11.31 Switched capacitor integrator and its noise equiv-
alent circuit. 290
11.32 Power spectral density of switched capacitor inte-
grator of Fig.11.31. Legends : measurement; –
this book. 290
11.33 CPU time of the noise analysis of the switched ca-
pacitor integrator of Fig.11.31. 291
xx COMPUTER METHODS FOR MIXED-MODE SWITCHING CIRCUITS
11.34 Ratio of CPU time of the brute-force approach for

noise analysis of the switched capacitor integrator
of Fig.11.31 to that of the adjoint network approach. 292
11.35 Noise equivalent circuit of the switched capacitor
band pass filter of Fig.11.14. All noise current gen-
erators are modeled as 294
band pass filter of Fig.11.35 due to thermal noise
sources. Legends : data from Tóth and Suyama
(1997); – this book. 295
band pass filter of Fig.11.35 due to flicker noise
sources. No foldover is considered in thermal noise
analysis. 296
11.38 Mean of the response of the switched capacitor
band pass filter of Fig.11.14. Legends: Monte
Carlo; – FOSM. 297
11.39 of the response of the switched capacitor band
pass filter of Fig.11.14. Legends: - Monte Carlo;
– FOSM. 298
12.1 Fold-over effect in distortion analysis of periodi-
cally switched nonlinear circuits. 319
12.2 Modulator. 322
12.3 Convergence of the second-order harmonic of the
modulator of Fig.12.2. 323
12.5 Convergence of the second-order harmonic of the
response of the stray-insensitive switched capacitor
integrator of Fig.12.4. 326
12.6 Stray-insensitive switched capacitor integrator with
nonlinear operational amplifier. 327
List of Figures xxi
12.7 Spectrum of the output of the stray-insensitive switched

capacitor integrator of Fig.12.6 with
(Baseband). 329
capacitor integrator of Fig12.6 with
(First positive sideband). 330
capacitor integrator of Fig.12.6 to two sinusoidal
inputs at 1 kHz and 1.1 kHz (Baseband). 332
capacitor integrator of Fig.12.6 to two sinusoidal
inputs at 1 kHz and 1.1 kHz (Baseband, first and
second positive sidebands). 333
List of Tables
4.1 Padé approximates of 62

4.2 The zeros of Padé polynomial 64
4.3 The residues of Padé polynomial 64
4.4 The zeros of Padé polynomial 64
4.5 The residues of Padé polynomial 65
5.1 Comparison of the relative errors of algorithms for
computing consistent initial conditions of the cir-
cuit of Fig.5.1. 101
7.1 Parameter values of the current-mirror amplifier of
Fig.7.7. 164
7.2 Parameter values of the circuit of Fig.7.9. 165
10.1 Transfer function theorem. 220
10.2 Frequency reversal theorem 223
10.3 Parameter values of the stray-insensitive switched
10.4 Transfer function and aliasing transfer functions of
the stray-insensitive switched capacitor integrator
of Fig.10.7. 225
10.5 Frequency response of the adjoint network of the
stray-insensitive switched capacitor integrator of Fig.10.7. 226
10.6 Parameter values of the stray-insensitive switched
xxiv COMPUTER METHODS FOR MIXED-MODE SWITCHING CIRCUITS
10.7 Frequency response of the band pass filter of Fig.10.9

and its adjoint network. 228
11.1 Parameters of the fifth-order elliptic switched ca-
pacitor low pass filter of Fig.11.1. 237
11.2 Sensitivity of periodically switched linear circuits
(Subscripts 1 and 2 identify the controlling and
controlled branches of controlled sources, respectively). 249
11.3 Sensitivity of linear time-invariant circuits (Sub-
scripts 1 and 2 identify the controlling and con-
trolled branches of controlled sources, respectively). 250
11.4 Parameters of stray-insensitive Switched-capacitor
integrator of Fig.11.9. 256
11.5 Parameters of switched capacitor band pass filter
of Fig.11.14. 259
11.6 Parameters of the fifth-order switched capacitor
low pass filter of Fig.11.20. 266
11.7 Parameter values of the switched capacitor low-
pass of Fig.11.29. 287
11.8 Parameter values of the switched capacitor inte-
grator of Fig.11.31. 289
11.A.1 Relationship between original periodically switched
linear circuit and its adjoint network. 301
12.1 Frequency components of the response of nonlinear
circuit to the input 308
12.2 Parameters of the modulator of Fig.12.2. 321
12.3 Harmonic distortion of the modulator of Fig.12.2 323
12.4 Parameter value of the stray-insensitive switched
12.5 Harmonic distortion of the stray-insensitive switched
12.6 Parameter value of the stray-insensitive switched
capacitor integrator of Fig.12.6 326
List of Tables xxv

328
328
capacitor integrator of Fig.12.6 using adjoint net-
work and brute-force methods. 330
12.10 Inter-modulation distortion of the stray-insensitive
switched capacitor integrator of Fig.12.6. 331
12.11 Harmonic distortion of the stray-insensitive inte-
grator with nonlinear capacitors. 332
Preface
Mixed-mode switching circuits distinguish themselves from other cir-

cuits by including switches that are either clocked externally or con-
trolled internally. These circuits have found broad applications in telecom-
munication networks, instrumentation, and power electronic systems, to
name a few. It is the emergence of switched capacitor networks in the
early 1970s and switched current circuits in late 1980s that sparked
a broad interest in and the rapid development of computer methods
and numerical algorithms for analysis and design of mixed-mode switch-
ing circuits. Recent advance in mixed analog-digital circuits and the
systems-on-chip realization of complex electronic systems have further
stimulated the enthusiasm of both the academia and industry in mixed-
mode switching circuits as these circuits provide a viable and yet eco-
nomical means to realize both analog and digital systems on a silicon
substrate using low-cost digitally-oriented CMOS technologies.
As compared with time-invariant circuits, the time-varying charac-
teristics, incomplete charge transfer, inconsistent initial conditions, and
th under-sampling of broadband noise of mixed-mode switching circuits
significantly complicate the analysis of these circuits, both in the time
domain and frequency domain. Since the early 1970s, a significant ef-
fort has been made on the development of computer methods for the
analysis and design of mixed-mode switching circuits. Many novel com-
puter methods and numerical algorithms have emerged. A systematic
presentation of these methods and an in-depth assessment of their ad-
vantages and limitations, however, are not available presently. This book
xxviii COMPUTER METHODS FOR MIXED-MODE SWITCHING CIRCUITS
is an attempt to summarize the recent advance in computer methods for

mixed-mode switching circuits and to provide an in-depth and compre-
hensive assessment on the pros and cons of these methods.
The book comprises of three parts.
Part I is concerned with the issues that are fundamentally important

to analysis of mixed-mode switching circuits. This part consists of four
chapters. Chapter 1 provides an introduction of mixed-mode switching
circuits and their applications. This chapter lays down a foundation for
subsequent chapters. Chapter 2 describes the computer-oriented formu-
lation of mixed-mode switching circuits. Starting with a brief review
of the historic perspective of the computer formulation of mixed-mode
switching circuits, the chapter details modified nodal analysis approach
for computer formulation of mixed-mode switching circuits. Chapter 3
introduces the network functions of linear and nonlinear time-varying
systems and their usefulness in characterization of periodically switched
linear and nonlinear circuits. Chapter 4 examines numerical integra-
tion methods for differential equations. Specifically, it investigates the
advantages and limitations of linear multi-step predictor-corrector algo-
rithms, including linear single-step predictor-corrector algorithms, and
introduces numerical Laplace inversion based numerical integration algo-
rithms. It explores the advantages of numerical Laplace inversion based
numerical integration method both analytically and numerically.
Part II deals with the time domain analysis of mixed-mode switching
circuits. This part consists of five chapters. Chapter 5 explores incon-
sistent initial conditions arising from ideal switching. In addition, it
presents several numerical methods that yield consistent initial condi-
tions when inconsistent initial conditions are encountered. Moreover, it
explores numerical techniques that detect the existence of inconsistent
initial conditions at switching instants. Chapter 6 addresses the time
domain analysis of periodically switched linear circuits. A number of
design objectives including response, parameter sensitivity, noise, the
effect of clock jitter, and the statistical quantities, such as the mean
and variance of the response of periodically switched linear circuits are
PREFACE xxix
analyzed. The effectiveness of these methods is assessed using exam-

ple circuits. Chapter 7 is concerned with the time domain analysis
of periodically switched nonlinear circuits. The method presented in
this chapter is based on time-varying Volterra functional series. Both
the time-domain response and sensitivity of these circuits are analyzed.
Chapter 8 deals with the analysis of circuits with internally controlled
switches. The switching variable of internally controlled switches typ-
ically encountered in mixed-mode switching circuits that controls the
state of these switches is defined. The methods that calculate the exact
time instant at which internally controlled switches change their state
are developed. The inconsistent initial conditions and impulsive net-
work variables generated at switching instants are examined in detail.
The detailed analysis of these circuits is illustrated using a linear voltage
regulator. Chapter 9 is concerned with the analysis of a special class of
mixed-mode switching circuits - over-sampled sigma-delta modulators.
We show that sampled-data simulation method for periodically switched
linear circuits, together with the behavioral modeling of quantizers, can
be applied to analyze over-sampled sigma-delta modulators effectively
and efficiently.
Part III is devoted to the frequency domain analysis of mixed-mode
switching circuits. This part consists of three chapters. Chapter 10 in-
troduces Tellegen’s theorem for periodically switched linear circuits in
the phasor domain. In addition, it derives the adjoint network of peri-
odically switched linear circuits using the principle of inter-reciprocity.
Frequency reversal theorem and transfer function theorem for periodi-
cally switched linear circuits are introduced, and their effectiveness in
efficient calculation of both the transfer functions and aliasing trans-
fer functions of these circuits is examined. Frequency domain analysis
of periodically switched linear circuits including the response, sensitiv-
ity, group delay, the noise, mean and variance of the response of these
circuits are analyzed in Chapter 11. Chapter 12 covers the frequency
analysis of periodically switched nonlinear circuits. Both the harmonic
distortion and intermodulation distortion of these circuits are derived.
The book can serve as a reference book on computer methods for anal-
ysis of mixed-mode switching circuits. It can also serve as the text book
xxx COMPUTER METHODS FOR MIXED-MODE SWITCHING CIRCUITS
of a graduate course on computer-aided analysis of mixed-mode switch-

ing circuits. The book assumes that readers have a solid understanding
of the basics of electrical networks, computer methods for analysis of
electrical networks, and integrated devices and circuits. This book pro-
vides both graduate students and computer-aided design (CAD) tool de-
velopment engineers with an in-depth understanding of computer meth-
ods and numerical algorithms for the analysis of mixed-mode switching
circuits in both the time an frequency domains.
FEI YUAN AND AJOY OPAL
FEB. 2004
Acknowledgments
The authors wish to take this opportunity to express their sincere

gratitude to the Natural Science and Engineering Research Council of
Canada, University of Waterloo, Ryerson University, and Canada Foun-
dation for Innovations for their financial support to both the authors and
their graduate students for their research on computer aided analysis and
design of mixed-mode switching circuits. Special thanks go to
for many of his pioneering work on computer-aided analysis and
design of integrated circuits that have inspired the authors profoundly,
and to the members of our research teams both at University of Waterloo
and Ryerson University, especially Drs. D. Bedrosian, B. Raahemifar,
Y. Dong, for many of their original contributions to computer methods
for mixed-mode switching circuits upon which this book is built. Our
heartfelt appreciation also goes to the reviewers of the initial proposal
of the book, (University of Waterloo), Dr. Timothy
Trick (University of Illinois at Urbana-Champaign), Dr. John Swell
(University of Glasgow) and Dr. Michael Nakhla (Carleton University).
Canadian Microelectronics Corporation, Kingston, Ontario, deserves a
special recognition for providing state-of-the-art computer-aided design
tools for analysis and design of integrated circuits.
The editorial staff of Kluwer Academic Publishers has, as always, been
wonderfully supportive from the beginning of the project. The authors
thankfully acknowledge the warm support of Mr. Michael S. Hackett,
senior publishing editor, electrical engineering and optics, Kluwer Aca-
demic Publishers, during the course of the writing of the book.
xxxii COMPUTER METHODS FOR MIXED-MODE SWITCHING CIRCUITS
This book could not have been completed without the unconditional
support of our families.
Fei Yuan is grateful to his abiding wife, Jing, for her love, support, un-
derstanding, and patient during many long nights of writing and proof-
reading of the book, and to our little girl and boy, Michelle and Jonathan,
for the joy that you have brought to our life. Daddy can finally have
more time to play violins with you.
Ajoy Opal is indebted to his grand parents Parkash and Ram Pershad
Mehra for fostering an interest in science and engineering, to his parents
Swadesh and Brij Kumar Opal for bringing him into this world and
for raising him, to his children Ambika and Anuj for all the joy and
wonderment that only children can bring.
I
THE FUNDAMENTALS
Chapter 1
AN OVERVIEW OF
MIXED-MODE SWITCHING CIRCUITS
This chapter presents an overview of mixed-mode switching circuits.

Section 1 gives a general classification of mixed-mode switching circuits.
In Section 2, switched capacitor techniques are introduced. Section 3
gives a brief introduction to switched current techniques. The charac-
teristics of mixed-mode switching circuits and their impact on numerical
algorithms for analysis of these circuits are investigated in Section 4.
1. Classification
Mixed-mode switching circuits have found a broad range of applica-
tions in many areas of electrical engineering, from telecommunication
networks, instrumentation, to power electronic systems. Mixed-mode
switching circuits distinguish themselves from time-invariant circuits by
including switches that are either clocked externally or controlled inter-
nally. These circuits can be broadly classified into the following cate-
gories:
Circuits with externally clocked switches. The switches in these cir-

cuits are controlled by external periodic clocks. Typical examples in
this category include switched capacitor networks and switched cur-
rent networks where switches are implemented using either NMOS
transistors or CMOS pairs with external clocks applied to the gate
of MOS transistors.
4 COMPUTER METHODS FOR MIXED-MODE SWITCHING CIRCUITS
Circuits with internally controlled switches. The switches in these

circuits are controlled by internal network variables of the circuits.
Rectifiers and switching voltage regulators where switches take the
form of diodes and thyristors are representative examples in this cat-
egory.
Circuits with both internally controlled and externally clocked switches.

Examples in this category include switched capacitor and switched
current over-sampled sigma-delta modulators where the integrators
are implemented using switched capacitor or switched current net-
works and the output of the quantizer of the modulators is set by the
input of the quantizer.
2. Switched Capacitor Techniques

Early applications of switched capacitor networks are the implemen-
tation of active filters where switched capacitors are used to replace
monolithic diffusion resistors to overcome the following difficulties en-
countered in realization of these resistors :
Large variation of resistance - Although diffusion resistors have a

large resistance value, the absolute value of these resistors is heavily
affected by the variation of the fabrication process by which the re-
sistors are fabricated and has a large variance, usually in the range
of ±30~40%. Such a large error significantly affects the performance
of filters.
Large parasitic capacitance - diffusion resistors have a large parasitic

junction capacitance that exists between the n-diffusion that forms
the resistors and the p-substrate upon which the resistors are fabri-
cated. This junction capacitance is not only nonlinear but also varies
greatly with the voltages at the terminals of the resistors [1].
Strongly nonlinear characteristics - the resistance of diffusion resistors

is a strongly nonlinear function of the terminal voltages of the resistor,
mainly due to the dependence of the effective area of the cross-section
of the resistors on the voltages at the terminals of the resistors [2].
An Overview of Mixed-Mode Switching Circuits 5
To overcome these difficulties, switched-capacitor techniques that syn-

thesize diffusion resistors using capacitors that are clocked periodically
emerged in the early 1970s. The essence of this technique can be demon-
strated conceptually using the circuit of Fig.1.1 where the capacitor C
is connected to two constant voltages and The connection is con-
trolled by two externally clocked switches. It is trivial to show that the
average current flowing through the capacitor in a clock period is given
by
where
C is the capacitance of the capacitor, is the clock period,

and is the equivalent resistance of the switched
capacitor. It is seen that the equivalent resistance can be controlled by
(i) the value of the capacitor and (ii) the clock frequency. For example,
with C = 1 pF and we have
Since monolithic IC techniques can ensure that the ratio of floating
capacitors be controlled very accurately, usually in the range of ±0.01%,
switched capacitor networks are always designed in such a way that the
response of the networks is only a function of (i) the clock frequency
and (ii) the ratio of the capacitors, rather than the absolute value of the
capacitors, such that the behavior of filters can be controlled accurately.
This is clearly a big advantage, as compared with active filters realized

using diffusion resistors.
The bottom plate of the capacitors usually has a large parasitic capac-
itance to the substrate, particularly if the capacitors are implemented us-
ing poly-diffusion capacitors. To minimize the effect of the parasitic bot-
tom plate-substrate capacitance of switched capacitor networks, stray-
insensitive switched capacitor techniques shown in Fig.1.2 were pro-
posed. Consider the circuit in Fig.1.2a, in phase 1 where
the two terminals of the bottom plate-substrate capacitor are shorted to
ground. In phase 2 where they are connected to both
the ground and the virtual ground of the following operational ampli-
fier. As a result, this parasitic capacitor has no effect on the operation
of the network. Fig.1.3 shows the basic configurations of inverting and
non-inverting stray-insensitive switched capacitor integrators [3].
The basic switched capacitor integrators can be combined to form
more complex switched capacitor networks, such as the biquad shown in
Fig.1.4.
3. Switched Current Techniques

The implementation of switched capacitor networks requires linear
capacitors that are realized using two floating conducting layers. These
floating conducting layers, however, do not exist in standard digitally-
oriented CMOS technologies in which most digital CMOS circuits are
realized. For most applications, the majority of the system blocks are
digital. It can not be economically justified to implement these system
blocks using analog or mixed-mode IC technologies, as they are much

more costly as compared with standard digitally-oriented CMOS tech-
nologies. Instead, it is highly desirable to realize analog blocks using
standard digitally-oriented CMOS technologies. Switched current tech-
niques emerged in the late 1980s [3] provide such a solution. Shown in
Fig.1.5 are the first generation and second generation switched current
memory cells. It is seen that switched current memory cells make use
of the gate capacitance of the sampling transistor to hold the sampled
input current, in the form of charge stored in and then exports it to
the output in the subsequent clock phase in the form of current. Note
that in these implementations, no linear capacitors are needed. Only
MOS transistors are used. Switched current techniques are therefore
fully compatible with and can be implemented using standard digitally-
oriented CMOS technologies.
Using the basic memory cells, other building blocks, such as integra-
tors, can be realized conveniently using switched current techniques, as
shown in Fig.1.6 [4].
The basic switched current integrators can be combined to form more
complex switched current networks, such as the biquad shown in Fig.1.7.
4. Characteristics of Mixed-Mode Switching

Circuits
Since the early 1970s, a significant effort has been made on the devel-
opment of numerical algorithms and computer methods for analysis and
design of mixed-mode switching circuits. Many computer methods, such
as frequency domain analysis of ideal switched capacitor networks [5, 6],
frequency domain analysis of non-ideal switched capacitor networks and
general periodically switched linear circuits [7, 8, 9, 10, 11, 12, 13], time
domain analysis of nonlinear circuits with internally controlled switches
[14, 15], adjoint network-based noise analysis of periodically switched lin-
ear circuits [16], Volterra series-based distortion analysis of periodically

switched nonlinear circuits [17], sampled-data simulation algorithms for
analysis of periodically switched linear and nonlinear circuits and sigma-
delta modulators [18, 19, 20], to name a few, have emerged. As compared
with time-invariant circuits and other time-varying circuits, mixed-mode
switching circuits exhibit the following distinct characteristics :
Time-varying topology - The topology of mixed-mode switching cir-

cuits varies with time. For circuits with externally clocked switches,
such as switched capacitor networks and switched current networks,
the time instants at which the topology of the circuits changes are
known a priori. For circuits with internally controlled switches, the
time instants at which the topology of the circuits varies, however, is
not known at the start of simulation and is determined by the numer-
ical value of the network variables controlling the state of switches,
such as the voltage across diodes and the effective gate-source voltage
of MOSFET switches, during simulation.
Dual-time systems - Periodically switched circuits are dual-time sys-

tems that contain rapidly varying clocks and slowly varying signals.
They have to be simulated over a large number of clock cycles with
fine steps in order to obtain their time domain characteristics accu-
rately and reliably.
Instantaneous charge (flux) distribution - When the loop resistance

is neglected, the re-distribution of charge in ideal switched capacitor
networks, which are composed of a limited set of elements including
ideal switches, independent voltage sources, voltage-controlled volt-
age sources, and capacitors, takes place at switching instants only.
This unique characteristic of ideal switched capacitor networks en-
ables the analysis of these networks using simple algebraic equations
derived from the charge conservation of the networks at switching
instants.
Incomplete charge (flux) transfer - When the loop resistance becomes

comparable to the duration of clock phases, the assumption that the
network variables reach their steady value of a clock phase before
reaching the end of the clock phase is violated. In this case, the
behavior of the circuits can not be depicted using algebraic equa-
tions that only take into account the value of the network variables
at discrete time instants, i.e. the clocking instants. Instead, differ-
ential equations that adequately depict the behavior of the circuits
continuously in the entire clock phase are needed. The value of the
network variables at the end of the clock phases must therefore be
determined by solving the differential equations using numerical in-
tegration. This not only increases the cost of simulation but also
complicates the analysis.
Inconsistent initial conditions - Because practical switched capacitor

networks and switched current networks are designed in such a way
that the initial transient portion of the time domain response of these
networks in each clock phase is not important and the network vari-
ables reach their steady value of the clock phase before reaching the
end of the clock phase, i.e. the loop time constant is much small as
compared with the duration of the clock phases. In this case, it is
computationally advantageous to model switches as an ideal device,
leading to ideal switching. Ideal switching, however, may cause an
abrupt change in nodal voltages, as will be detailed in Chapter 5.
The abrupt change in the capacitor voltage gives rise to an impul-
sive capacitor current. Similarly, ideal switching may give rise to an
abrupt change in loop currents, resulting in impulsive inductor volt-

ages. The impulsive currents (voltages) re-distribute charge (flux) in
the networks at switching instants instantaneously. As a result, the
value of the network variables of these circuits immediately before
switching differs from that immediately after switching, leading to
inconsistent initial conditions, which can not be handled by conven-
tional numerical integration methods.
High output noise power- for circuits with externally clocked switches,
the clocking frequency is usually much higher than the frequency of
input signals, mainly due to the need to avoid spectrum overlap-
ping of the sampled signals (Nyquist theorem). The equivalent noise
bandwidth of these circuits, however, is usually several orders of mag-
nitude higher than the sampling frequency. The under-sampling of
the broad-band noise sources in these circuits, such as shot noise and
thermal noise that are white in nature, gives rise to the fold-over ef-
fect where the output noise power of these circuits is not determined
by the in-band noise power of the noise sources, but rather dominated
by the noise power of the sideband components of these white noise
sources that is folded over to the baseband. As a result, mixed-mode
switching circuits exhibit a significantly high level of output noise
power in the baseband.
Chapter 2
COMPUTER FORMULATION OF
MIXED-MODE SWITCHING CIRCUITS
This chapter deals with computer-oriented formulation of mixed-mode

switching circuits. Section 1 investigates the modeling of switches. The
advantages and limitations of various switch models are examined. Sec-
tion 2 presents a historic perspective of the computer-oriented formu-
lation of mixed-mode switching circuits. We show that although many
computer-oriented formulation methods were proposed, only modified
nodal analysis (MNA) remains popular. This section also examines the
implementation of the computer formulation of mixed-mode switching
circuits using modified nodal analysis. Specifically, the matrix stamps
of elements used in modified nodal analysis formulation are developed.
Special attention is given to circuit elements with memory, as the en-
ergy stored in these elements is intrinsic to the operation of switching
circuits. The chapter is summarized in Section 3.
1. Modeling of Switches
Mixed-mode switching circuits distinguish themselves from time-invariant
circuits by including switches. Switches appears physically in the form of
NMOS transistors or as a pair of CMOS transistors in externally clocked
circuits, such as switched capacitor networks and switched current net-
works, and diodes and thyristors in circuits with internally controlled
switches. They can be characterized at different levels of circuit ab-
straction, among which, full-transistor model, voltage-modulated resistor
model, and ideal switch model are the most widely used circuit-level
switch models.
1.1 Full-Transistor Models

A full-transistor model of MOS switches takes into account both the
intrinsic and parasitic parameters of MOS devices [21]. It is capable
of capturing the rapidly varying characteristics of the time-domain be-
havior of the switches. Simulation based on the full-transistor model,
however, is costly, mainly due to the large size of the equivalent circuit
of MOS switches and the small value of the parasitic parameters of MOS
switches. The same holds true for other types of switches as well. The
use of the full transistor model is therefore warranted only if a detailed
analysis of the transient behavior of the circuits is required. For practical
applications, because most mixed-mode switching circuits are designed
in such a way that the transient behavior of the circuits in a clock phase
dies out before reaching the end of the clock phase, the full-transistor
models are rarely needed.
1.2 Voltage-Modulated Resistor Models

When the rapidly changing transient characteristics of the circuits are
not of a critical concern, switches can be modeled as a voltage-modulated
resistor that has a small resistance in the ON state, usually a few
depending upon the technology in which MOS switches are realized and
the width of the switches, and a large resistance in the OFF state, often
in the range of several hundred The large difference between the
ON and OFF resistances of the voltage-modulated resistor gives rise to
largely distinct time constants for the ON and OFF states, respectively.
As a result, stiff systems with numerically ill-conditioned circuit matrices
occur. The time-domain analysis of these circuits requires fine time steps
in order to capture the rapid transient behavior of the circuits in the ON-
state. On the other hand, simulation needs to be executed over a long
period of time in order to account for the large time constant associated
with the OFF state, resulting in excessive computation and exceedingly
long simulation time.
Computer Formulation of Mixed-Mode Switching Circuits 15
1.3 Ideal Switch Models

To avoid the drawbacks arising from the voltage-modulated resistor
models, the ideal switch model that has zero resistance in the ON state
and infinite resistance in the OFF state, as shown in Fig.2.1, is of par-
ticular interest.
The difference between the voltage-modulated resistor models and the

ideal switch models manifests itself in the transient response of mixed-
mode switching circuits and is best illustrated using the circuit given
in Fig.2.2, where and Capacitor is
initially charged to 2V and is initially at rest, i.e.
and The MOSFET switch closes at The response
of the circuit with the ideal switch models and that with the voltage-
modulated resistor switch models are shown in Fig.2.3. It is seen that
the response with the ideal switch models does not have the initial rising
transient portion of the response that the response of the circuit with
the voltage-modulator resistor models does. Due to the rapidly time-
changing characteristics, the analysis of the transient portion requires a
large number of small time steps in order to capture the time-varying
response. As a result, an excessive amount of computation time, usually
up to 90 % of the total simulation time, is used up in the initial rising
transient [22]. Also observed is that in the limiting case where
the time domain response with the voltage-modulator resistor switch
model approaches that with the ideal switch model.
Most switched capacitor and switched current networks are designed
in such a way that the initial transient portion of the time domain re-
sponse is not important and the network variables reach their steady-
state values before reaching the end of clock phases. In these cases, it is
computationally advantageous to model switches as an ideal device, lead-
ing to ideal switching. Ideal switching, however, may cause an abrupt
change in nodal voltages, as observed in Fig.2.3. The abrupt change in
the capacitor voltage gives rise to an impulsive capacitor current that
redistributes the charge instantaneously. In a similar manner one can
show that when inductors are encountered, ideal switching may give rise
to an abrupt change in loop currents, resulting in impulsive inductor
voltages.
2. Formulation Methods for

Mixed-Mode Switching Circuits
2.1 A Historical Perspective
In the early stages of the development of computer methods for cir-
cuits with externally clocked switches, in particular, ideal switched ca-
pacitor networks that are composed of ideal operational amplifiers, ideal
voltage sources, voltage-controlled voltage sources, capacitors, and ideal
switches only, many formulation methods were proposed to deal with
the time-varying topology of these circuits. In ideal switched capacitor
networks, due to zero loop time constants, the charge redistribution pro-
cess among capacitors takes place at switching instants instantaneously.
Once the ON resistance of MOS switches are considered, the redistri-
bution of charge is governed by the loop time constant. These circuits
exhibit distinct characteristics as compared with ideal switched capaci-
tor networks and are called periodically switched circuits to distinguish
them from ideal switched capacitor networks. Clearly, ideal switched
capacitor networks are a subset of general periodically switched circuits.
Due to incomplete charge transfer, numerical integration algorithms are
needed to determine the voltage of capacitors and the current of induc-
tors in these circuits at the end of each clock phase.
Many computer-oriented formulation methods were proposed for anal-
ysis of ideal switched capacitor networks and general switched networks.
Among them, equivalent-circuit [23, 24], transmission matrix [25, 26, 27],
switching matrix [28, 29], signal flow diagram [30, 31, 32], state-space
[33], two-graph [34, 5], and modified nodal analysis are most cited. The
equivalent-circuit approach represents switched capacitor networks with
a set of building blocks that have known characteristics. This approach
is effective for small switched capacitor networks only. Transmission ma-
trix approach maps the building blocks of switched capacitor networks
to a set of matrices so that the networks can be analyzed conveniently.
It is effective for networks of small size. Signal-flow diagram approach
makes use of Mason’s rule [35] to yield the transfer function from a given
input node to an arbitrary output node. This approach provides many
insights of the operation of networks, it, however, is not particularly
convenient for computer analysis of switched networks.
Modified nodal analysis (MNA), an extension of the nodal analysis,
has been used extensively in analysis of electrical networks since its emer-
gence in 1970s [36]. For ideal switched capacitor networks, due to the
existence of impulsive currents at switching instants in these networks,
nodal charge conservation law is used at switching instants [37, 28]. This
approach possesses many advantages over other formulation methods in-
cluding [38] :
Ease in circuit formulation. MNA formulation inherits the intrinsic

advantages of Tableau formulation in circuit formulation [39]. The
MNA formulation for arbitrarily large circuits is straightforward. No
manipulation of equations is necessary.
Branch voltages and many branch currents are eliminated in MNA

formulation as compared with Tableau formulation, leading to much
smaller circuit matrices.
Circuit matrices are sparse. The sparsity of circuit matrices enables

the use of sparse matrix solvers to significantly reduce the cost of
computation.
Convenience in calculating parameter sensitivity [5].
Time derivatives of independent sources are never needed.

2.2 External Clocks

External clocks used for clocking switches are multi-phase and non-
overlapping, as shown in Fig.2.4, where denotes the period of the
clock and K denotes the number of phases in a clock period. Note that
and
2.3 Conventions
To avoid any ambiguity, the following conventions are adopted in this
book.
If a switch changes its state at the time instant we

shall use to denote the time instant immediately before
switching and to denote the time instant immediately
after switching.
denotes the vector of the network variables of mixed-mode switch-

ing circuits in the time domain. denotes the vector of the
network variables of mixed-mode switching circuits in the frequency
domain.
denotes the vector of the network variables of mixed-mode

switching circuits in phase denotes the vector of the
Fourier transform of the network variables of mixed-mode switching
circuits in phase
denotes the vector of the first-order time derivative of the

network variables of mixed-mode switching circuits in phase
denotes the vector of the network variables of mixed-

mode switching circuits at the time instant It can also
be written as where denotes Dirac
impulse function.
2.4 Sub-Circuits
The topology of an externally clocked circuit changes from one clock
phase to another and remains unchanged during each clock phase. This
observation suggests that an externally clocked circuit with a total of K
phases in a clock period can be considered as an assembly of K time-
invariant sub-circuits that are interconnected via the initial conditions
of elements with memory (capacitors and inductors), as depicted graph-
ically in Fig.2.5. These sub-circuits are operated in a time-interleaved
fashion such that
and
The time duration in which the input is connected to the sub-circuit

is specified by the window function defined as
The input to the sub-circuit is therefore given by
2.5 Matrix Stamps of Elements Without Memory

2.5.1 Controlled Sources
Memoryless elements are those whose response is determined by their
present inputs only. Typical memoryless elements include resistors and
controlled sources. As an example, consider the nonlinear voltage-controlled
voltage source characterized by
where and are the controlling and controlled voltages, re-

spectively, and are constants. The primitive schematic of non-
linear voltage-controlled voltage sources in phase is shown in Fig.2.6.

The behavior of the controlled source is completely characterized by the
following relations called constitutive equations
and
Eqs.(2.7) and (2.8) can be written in a matrix format, leading to the

matrix stamps of the nonlinear controlled source, as shown in Fig.2.6.
The missing entries of the added rows and columns are zeros. Note that
nonlinear terms are purposely placed in the vector on the right hand
side of the equations such that the matrices and vectors on the left hand
side of the equation are all linear. The matrix stamps of other nonlinear
controlled sources can also be derived in a similar manner and they are
shown in Fig.2.6. The matrix stamps of linear controlled sources can be
obtained from that of the corresponding nonlinear controlled sources by
simply setting the nonlinear coefficients to zero.
2.5.2 Ideal Switches

As shown in Fig.2.7, there are only two distinct states associated
with the operation of an ideal switch connected to nodes and : the
ON state and the OFF state. Ideal switches are characterized by the
following constitutive equations:
The ON state is characterized by
The OFF state is characterized by
These characteristics can be mapped to the equations given in Fig.2.7.
The matrices for the ON and OFF states can also be combined by in-
troducing the switching variable
2.6 Matrix Stamps of Elements With Memory

An element is said to have memory if its response is a function of
both its present inputs and its previous states. Capacitors and inductors
are typical elements in this category. The energy storage capability of
these elements is intrinsic to the operation of mixed-mode switching
circuits. In this section, we examine the matrix stamps of capacitors

and inductors in circuits with externally clocked switches.
2.6.1 Capacitors
Consider a linear time-invariant capacitor C. Let the initial voltage
of the capacitor be The capacitor is connected to nodes and
with its current flowing from node to node The constitutive
equation governing the capacitor in the Laplace domain is given by
where and are the Laplace transform of the capacitor current

and that of the voltage respectively. Eq.(2.10) can be written
equivalently in the time domain as
where is the Dirac impulse function. Now, consider a linear capacitor

in phase of a periodically clocked linear circuit. Let the voltage of the
capacitor at be Note that
is the initial condition of the capacitor in phase Making use of
(2.11), we arrive at
The time interleaved operation of externally clocked circuits, as detailed

in Fig.2.5, requires that be zero outside phase To ensure that
is zero for the input to the sub-circuit of phase must be
removed. Also, the charge of the capacitor at the end of the clock phase,
i.e. must be extracted completely. This is accomplished
by subtracting from
In MNA, the above equation can be written in a matrix format, as shown

in Fig.2.8.
Most nonlinear capacitors encountered in integrated mixed-mode switch-
ing circuits are pn-junction induced. The small-signal behavior of a non-
linear capacitor is often characterized using its charge-voltage relation,
usually up to the order of three [2]
where and are the AC components of the charge stored in

the capacitor and the voltage across the capacitor, respectively.
and are constants and are functions of the DC operation point of the
capacitor. To exemplify the procedures of how (2.14) is derived, consider
the junction capacitance of an abrupt pn-junction
where is the junction capacitance at zero biasing voltage, is the

total reverse biasing voltage, and is the built-in potential of the pn-
junction. and are functions of the doping of the and
that of the extrinsic silicon of the junction and the temperature
of the junction [40]. Let where and are the DC
and AC components of respectively. Further we assume
Expanding at the DC operation point in its Taylor series and

truncating the series at its third-order term yield
where
The first term on the right had side of (2.16) gives the junction capaci-
tance at the DC operating point
whereas the remaining terms quantify the AC capacitance.
It is seen that the AC capacitance is a nonlinear function of both the DC

operating point and the AC amplitude of the reverse biasing voltage.
If a nonlinear capacitor has initial charge the capacitor is char-
acterized in the Laplace domain by
or equivalently in the time domain
Now consider a nonlinear capacitor in an externally clock circuit. Let

denote the charge of the capacitor at
This is the initial condition of the capacitor in phase The current of

the capacitor in phase is given by
Following the same arguments as those for linear capacitors, to ensure

that vanishes outside phase the charge stored in the capacitor at
the end of phase denoted by must be
extracted from
The MNA formulation of the nonlinear capacitor is based on (2.14)

and (2.23) exclusively and is given in Fig.2.8.
2.6.2 Inductors
Inductors in mixed-mode switching circuits can be handled in a similar
manner as that for capacitors. The effect of the magnetic flux stored in
the inductors in phase on the behavior of circuits in the following
phase must be considered. Fig. 2.9 shows the matrix stamps of linear
and nonlinear inductors.
2.7 Formulation of Circuits with

Externally Clocked Switches
As stated earlier that to facilitate analysis, an externally clocked circuit
with input and an external clock of K clock phases can be con-
sidered as an assembly of K time-invariant sub-circuits interconnected
via their initial and final conditions of the elements of the circuit with
memory. Each sub-circuit must ensure that its network variables satisfy
To achieve this, the following criteria are followed in formulation of these

sub-circuits:
The input is connected to the sub-circuit of phase only

and is disconnected from the sub-circuit outside phase This is
consummated by making use of the window function defined
earlier.
The effect of the initial voltage (charge) of the capacitors and that of
the initial current (flux) of the inductors of the sub-circuit must be
accounted for as they have an impact on the behavior of the circuit
in phase
The voltage (charge) of the capacitors and the current (flux) of the
inductors at the end of phase must be extracted so that they will
not affect the behavior of the sub-circuits in subsequent clock phases.
The circuit matrices of each sub-circuit are obtained by applying ap-

propriate matrix stamps introduced in the preceding sections to each
circuit element. In implementation, the matrix stamps of each type of
elements are coded as functions with element type, element values, and
their electrical connections as input parameters of the functions so that
the overall circuit matrices can be formulated in an automated manner.
where is the input of the circuit whose connection in phase is

specified by the constant vector is the window function for
the input, is the network vector in phase which may contain
nodal voltages, branch currents, the charge of nonlinear capacitors, and
the flux of nonlinear inductors. is the linear conductance matrix
whose entries are made of linear elements and the linear portion of non-
linear elements, is the linear capacitance matrix in phase whose
entries are from linear capacitors and inductors; is a nonlinear
vector containing all nonlinear terms of the Taylor series expansion of
the nonlinear elements in the circuit. Clearly, for a linear circuit we

have The Dirac delta function term at takes
into account the contribution of the initial voltage (charge) of capacitors
and the initial (current) flux of inductors at the beginning of phase
whereas the Dirac delta function term at resets all ca-
pacitors and inductors so that the output of the sub-circuit of phase
vanishes outside the phase.

Internally Controlled Switches
Unlike circuits with externally clocked switches, the time instants at
which the topology of circuits with internally controlled switches changes
are determined by the state of the switching variable of the switches in
the circuits. The switching variable controls the state of the switch
in accordance with
As an example, of a NMOS transistor is the effective gate-source

voltage given by where is the threshold voltage
of the transistors. Because the value of the switching variables is not
known at the start of simulation, an initial state is assumed and the
circuit is formulated accordingly. is then computed and monitored in
every time step of the simulation of the circuit. A change in the polarity
of indicates a change in the state of the corresponding switch in the
current time step. Iterative algorithms, such as Newton-Raphson, are
then employed to accurately compute the exact time instant by solving
numerically [14], as shown in Fig.2.10. Once the exact time is
detected, the topology of the circuit is updated and the initial conditions
of the new circuit are computed. It should be noted that because ideal
switching gives rise to impulse currents or impulse voltages, as will be
shown in Chapter 5, the impulses generated at switching instants may
trigger other switches in the circuit and change the topology of the circuit
subsequently. In analysis of these circuits, it is important to further
examine the state of each internally controlled switches after a switch

changes its state.

Both Externally Clocked and Internally
Controlled Switches
Formulation of circuits with both externally clocked and internally
controlled switches can be handled conveniently by integrating the ap-
proaches for circuits with externally clocked switches and those with
internally controlled switches. Specifically, during each clock phase, the
circuits are handled using the approach for circuits with internally con-
trolled switches. At switching instants, they are handled using the ap-
proach for circuits with externally clocked switches. Since the state of
internally controlled switches is not known a priori, this requires the re-
formulation of the circuit equations at each switching instant. It should
be noted that current or voltage impulses generated at the clocking in-
stants may trigger switches that are internally controlled. Detection of
impulsive network variables at clocking instants is critical. The current
or voltage impulses generated by the switching of internally controlled
switches, on the other hand, have no effect on the operation of externally
clocked switches.
3. Summary
In this chapter, we have examined the advantages and disadvantages
of various switch models. We have shown that full-transistor models are
rarely used in analysis of mixed-mode switching circuits due to the in-
significance of the transient portion of the response and the high compu-
tational cost associated with these models. In comparison with the full-
transistor models, the voltage-modulator resistor models are much sim-
pler and yet are able to capture the essential characteristics of switches.
The voltage-modulator resistor models, however, give rise to stiff sys-
tems that have two largely distinct time constants for the ON and OFF
states of switches, leading to excessive simulation time. Ideal switch
model removes this difficulty by using an open-circuit for the OFF state
and a short-circuit for the ON state. Ideal switching, however, may
cause an abrupt variation in nodal voltages or loop currents, resulting in
inconsistent initial conditions and impulsive network variables that can
not be handled by conventional numerical integration methods.
To formulate the circuit equations of mixed-mode switching circuits,
we have examined the reasons why only modified nodal analysis for-
mulation method continues to remain popular. The matrix stamps of
both memoryless elements and elements with memory have been devel-
oped, and the computer-oriented formulation of circuits with externally
clocked switches and those with internally controlled switches have been
developed. Special attention has been given to elements with memory,
i.e. inductors and capacitors, as the energy storage capability of these
elements is intrinsic to the operation of mixed-mode switching circuits.
Chapter 3
NETWORK FUNCTIONS OF
TIME-VARYING CIRCUITS
This chapter examines mathematical tools that are fundamentally im-

portant to the analysis of mixed-mode switching circuits. In Section
1, the time-varying network function of linear time-varying systems is
introduced and its usefulness in characterization of linear time-varying
systems is investigated. The aliasing transfer functions for characterizing
linear periodically time-varying systems are also introduced. We show
that although the input to a linear periodically time-varying systems is
a single tone, the response of the system has an infinite number of tones
located at the baseband and sideband frequencies. This characteristic of
linear periodically time-varying systems differs fundamentally from that
of linear time-invariant systems. In Section 2, Volterra functional series
for characterizing nonlinear time-invariant and time-varying systems is
introduced first. We then introduce multi-frequency time-varying net-
work functions and multi-frequency network functions to characterize
the behavior of nonlinear time-varying systems in both the time and
frequency domains. Section 3 derives the frequency response of non-
linear time-varying systems. Section 4 presents the frequency domain
response of a special class of nonlinear time-varying systems, nonlinear
periodically time-varying systems, to both single-tone inputs for har-
monic distortion and multi-tone inputs for intermodulation. The chap-
ter concludes in Section 5. A proof of the periodicity of the time-varying
network function of linear periodically time-varying systems is given in

Appendix 3.A.
1. Transfer Functions of Linear Time-Varying

Systems
1.1 Linear Time-Varying Systems
In steady state, the behavior of a linear time-varying system in time
domain is described by the impulse response of the system which
is a function of both the excitation time at which the impulse is
launched and the observation time at which the response of the sys-
tem to the impulse is measured. The input and output of the
system are related to each other in the time domain by
For linear time-invariant systems, Eq.(3.1) becomes
Note that the impulse response is evaluated at the excitation time only
in (3.2). The behavior of linear time-varying systems is characterized by
the time-varying network function introduced by Zadeh in [41].
is defined as
The impulse response can be derived from using the inverse

transform
Substituting (3.4) into (3.1) gives

Network Functions of Time-Varying Circuits 37
where is the Fourier transform of
1.2 Linear Periodically Time-Varying Systems

If a system is linear periodically time-varying, we show in Appendix
3.A of this chapter that time-varying network function is also
periodic in Assume that satisfies Dirichlet-Jordan criterion,
i.e. is bounded, piecewise continuous, and has at most a finite
number of minima, maxima, and discontinuities per period, can
be represented in the Fourier series
where and is the period. The coefficients are determined

from
The frequency response of the output, denoted by is obtained by

taking Fourier transform of (3.5)
Further making use of (3.6), Eq.(3.8) becomes
Because
we arrive at
Eq.(3.11) reveals that :
The frequency response of a linear periodically time-varying system

at frequency consists of the contribution of the input signal at
both and This characteristic differs fundamentally from
linear time-invariant circuits. If the input to a linear periodically
time-varying circuit is a broadband signal, such as thermal and shot
noise, then the response of the circuit at a given baseband frequency
contains the contribution of the input at both the baseband frequency
and that at corresponding sideband frequencies, resulting in much
higher output power.
The quantity characterizes the relation between the

input at the side band frequency and the output at the base
band frequency It is called the aliasing transfer function. Note
that aliasing transfer functions are a generalization of the transfer
functions for linear time-invariant circuits where both the input and
output are evaluated at the same frequency, i.e. the frequency of the
input.
If the system is linear time-invariant, Eq.(3.11) is simplified to

Network Functions of Time- Varying Circuits 39
Clearly, for linear time-invariant systems, there is a one-to-one map-

ping between the input and output frequency components whereas for
linear periodically time-varying systems, the mapping is multiple-to-
one.
If the input of the linear time-varying system is an exponential func-

tion of time where is the frequency of the input, because
the Fourier transform of is given by
using (3.5), we obtain the response of the system
If the system is further linear periodically time-varying, then

can be represented in the Fourier series given in (3.6) with replaced
by Substituting the results into (3.14) yields
where is the coefficient of the Fourier series given by

(3.7). The following important observations are made from the pre-
ceding derivation:
The response of a linear periodically time-varying system to a input at

the frequency contains an infinite number of frequency components
at frequency and corresponding sideband frequencies
where
specifies the magnitude of the frequency component

at the frequency in the complex plane. It is the phasor
representation of at the frequency
For linear time-invariant systems, phasors are defined at the input

frequency only. For linear periodically time-varying systems, they are
defined at both the input frequency and the sideband frequencies
This is a distinct characteristic of these systems.
2. Transfer Functions of Nonlinear Time-Varying

Systems
2.1 Volterra Functional Series
Nonlinear time-invariant systems are most often analyzed using power
series [42] where the response of the system, denoted by is repre-
sented as the power series of the excitation
where are constants. It is seen that the response is related to the

inputs at the present time only. Because it does not take into account the
effect of the past states of elements with memory, such as capacitors and
inductors, power series approach is only valid for circuits consisting of
memoryless elements or circuits with memory elements but operated at
sufficiently low frequencies such that the contribution of the past states
of elements with memory is negligible. For high-frequency applications,
the effect of past states must be considered. In this case, the coefficients
of the power series become frequency-dependent. The response in this
case is characterized by Volterra functional series, also known as power
series with memory [43]
where
and is the Volterra kernel. When the system

is nonlinear time-varying, the Volterra series become [44]
2.2 Multi-Frequency Network Functions

It was shown in the preceding section that a set of time-varying
Volterra kernels, are needed to characterize the
behavior of nonlinear time-varying systems in the time domain. To de-
pict the behavior of the systems in the frequency domain, we extend the
definition of the time-varying network functions for linear time-varying
systems given earlier to nonlinear time-varying systems by defining the
following multi-frequency time-varying network functions
The Volterra kernel is obtained from the inversion transform
Substitute (3.21) into (3.17)
where is the Fourier transform of with frequency As

an example, consider a nonlinear time-varying system with the input
The response is obtained from
It is evident from the above equation that multi-frequency network func-

tions quantify the fundamental and harmonic components of the fre-
quency response of nonlinear time-varying systems.
2.3 Multi-Frequency Transfer Functions

It is well known that the transfer function of linear time-invariant
systems completely characterizes the behavior of the systems in the fre-
quency domain. It is perhaps less well known that Zadeh’s bi-frequency
transfer function defined as
where and are the output and input frequencies, respectively, depicts
the behavior of linear time-varying systems in the frequency domain
effectively. The output is obtained from
The corresponding time-varying network function is obtained from the

inverse transform
If i.e. is a single-tone at with unit amplitude.

Because we have This result
reveals that represents the aliasing transfer function of the
system from the input at the frequency to the output at the
frequency
To analyze nonlinear time-varying systems in the frequency domain,
we extend the definition of Zadeh’s bi-frequency for linear time-varying
systems to nonlinear time-varying systems by introducing the following
multi-frequency transfer function
The corresponding time-varying network function is obtained from the

inverse transform
3. Frequency Response of
Nonlinear Time-Varying Systems
The frequency response of nonlinear time-varying systems is obtained
from the Fourier transform of (3.17)
It was shown earlier that the Fourier transform of the 1st-order response
is given by
where denotes Fourier transform operator. The Fourier transform

of is obtained from
Continuing this process and substituting these results into (3.29) give
The following comments are made with respect to the preceding devel-
opment:
Eq.(3.32) is a frequency-domain representation of the time-varying

Volterra series. Analogous to the time-domain representation of time-
varying Volterra series, can be considered as
the kernel of the order frequency-domain Volterra series.
Clearly seen is that once is known, the spectrum

of the response of nonlinear time-varying systems to the input
is defined completely.
Consider the special case where because
we have
Eq.(3.34) provides a general means to characterize the behavior of

nonlinear time-varying system in the frequency domain. In the next
section, we will make use of these results to obtain the frequency
response of a special class of nonlinear time-varying systems, namely,
nonlinear periodically time-varying systems.
4. Frequency Response of
Nonlinear Periodically Time-Varying Systems
In this section, we make use of the results from the preceding section
to derive the frequency response of nonlinear periodically time-varying
Network Functions of Time- Varying Circuits 45
systems to both single-tone and dual-tone inputs. In Appendix 3.A of

this chapter, we have shown that of nonlinear periodi-
cally time-varying systems is periodic in with the period equal to the
switching period They can be represented in Fourier series
where
If the input is given by we obtain
Consequently
In the base band where the fundamental component of the

response is given by whereas the second-, third-, ..., and
harmonic components are given by and respectively.
The similar pattern repeats in side bands where To obtain the
harmonic components of the response of nonlinear time-varying systems
to a sinusoidal input because
we have
Note that we have assumed symmetrical kernels in the above derivation.

The 2nd- and 3rd-order harmonic distortion, denoted by and
respectively, are computed from
If the system is nonlinear time-invariant, then (3.41) and (3.42) simplify

to the familiar expressions of and of nonlinear time-invariant
systems [45].
If the system is further nonlinear periodically time-varying, we have
The complete spectrum of the response is given in Fig.3.2. The 2nd-order

and 3rd-order harmonic distortions in the base band are computed from
provided that
If the input of a nonlinear time-varying system contains two different
frequencies
with the spectrum of the response can also be obtained in a

similar manner. It can be shown that the 3rd-order intermodulation
distortion, denoted by is computed from
If the system is further nonlinear periodically time-varying, then it can

be shown that the spectrum of the response is given in Fig.3.3. The
3rd-order intermodulation distortion at in the base band is
computed from
where has been assumed.

5. Summary
Mathematical tools that are fundamentally important to the analysis
of mixed-mode switching circuits have been presented. Specifically, the
time-varying network function of linear time-varying systems has
been introduced and its usefulness in characterization of the time-domain
behavior of linear time-varying systems from its frequency-domain ex-
citation has been investigated. Aliasing transfer functions that charac-
terize linear periodically time-varying systems has been introduced. We

have demonstrated mathematically that the response of a linear peri-
odically time-varying system to an input of single frequency contains
an infinite number of tones located at both the input frequency and
corresponding sideband frequencies. This characteristic of linear peri-
odically time-varying systems differs fundamentally from that of linear

time-invariant systems.
To analyze nonlinear systems, we have shown that power series ap-
proaches are valid for characterizing nonlinear systems without memory
or general nonlinear systems at low frequencies at which the contribu-
tion of the past states of elements with memory is negligible. When
the effect of the past states of elements with memory can not be ne-
glected, Volterra functional series must be employed. We have intro-
duced multi-frequency time-varying network function
to characterize time-varying nonlinear systems in the time domain, and
multi-frequency network functions to characterize the
behavior of these systems in the frequency domain. The use of these
network functions allows us to derive the spectrum of nonlinear period-
ically time-varying systems to inputs of both single-tone and multiple
tones.
APPENDIX 3.A: Periodicity of

The Network Functions of
Nonlinear Periodically Time-Varying Systems
In this appendix, we show that the time-varying network functions of nonlinear
periodically time-varying systems are periodic in time with the same period.
Consider a linear periodically time-varying system characterized by
where is the input and is the response. The periodicity of the system is
characterized by where is the period of time variation. Note that
although we have chosen scalar form for the purpose of simplicity the results can be
readily extended to vector form. The solution of (3.A.1) is given by [46]
where
Without losing generality, let the input of the system be . Representing

in Fourier series
APPENDIX 3.A 51
where is the coefficient of the Fourier series and Substituting (3. A.4)
into (3.A.2) and carrying out integration give
where and are constant and
and is the order coefficient of the Fourier series expansion of A few

comments with respect to the above results are made.
is periodic in with period Similarly, one can also show that the reciprocal
of denoted by is also periodic in with period
The necessary condition for the system to be asymptotically stable is
This ensures is bounded as
In the steady state, the first and second terms in (3.A.5) vanish, and the third
term gives the steady-state response of the system
Since is periodic in with period it is evident that is also periodic in

with period By comparing (3.A.7) with (3.14), the relation
follows. We therefore conclude that is periodic in with period
Having proved the periodicity of we now examine the periodicity of

higher order time-varying network functions. Because for asymptotically stable sys-
tems the zero-input response dies down in the steady state, in the following analysis we
will only focus upon the zero-state response in the steady state. Consider a nonlinear
periodically time-varying system represented by
where is a nonlinear function of If the nonlinearities encountered are

mild, can be approximated using only a truncated Taylor series expansion of
the nonlinear equations of the nonlinearities, mathematically
where and are constants. Using Volterra series, equation (3.A.8) can be repre-
sented by the following set of linear periodically time-varying systems
where and are the 1st-, 2nd-, and third-order terms of the Volterra
series expansion of respectively. and
If we have
Since is periodic in with period we have
where is the Fourier series coefficient. The input of the second order Volterra
circuit, denoted by is given by
Using (3.A.5) we obtain the zero-state response of the second order Volterra circuit
where is a constant. If the system is asymptotically stable, then

as Thus, the steady-state response is given by
Clearly, is periodic in with period Comparing (3.A.11) with (3.A.15)

we conclude that is also periodic in with period In a very like
manner, one can show that is periodic in with period
Chapter 4
NUMERICAL INTEGRATION OF
DIFFERENTIAL EQUATIONS
The behavior of mixed-mode switching circuits is depicted in the time

domain using differential equations. This chapter is concerned with nu-
merical integration algorithms for differential equations. The conven-
tional linear single-step predictor-corrector (LSS-PC) algorithms and lin-
ear multi-step predictor-corrector (LMS-PC) algorithms are reviewed in
Sections 1 and 2. We show that although these algorithms are robust in
solving both linear and nonlinear circuits, the accuracy of these methods
is limited by the order of polynomials used in extrapolation and the use of
the first-order derivatives. In Section 3, we show that numerical Laplace
inversion that derives the time domain solution from its coun-
terpart is an elegant high-order numerical integration methods for linear
circuits. The accuracy of this method is orders of magnitude higher as
compared with that of LMS-PC algorithms. In addition, this method is
capable of handling both impulses and discontinuities in network vari-
ables that can not be handled by LMS-PC algorithms. This unique
characteristic makes numerical Laplace inversion algorithm particularly
attractive for analysis of mixed-mode switching circuits where impulses
and discontinuities might be encountered at switching instants. We ex-
amine the properties of numerical Laplace inversion by first introducing
Padé polynomials. Our focus is then shifted to the use of Padé approxi-
mation in numerical Laplace inversion. The dependence of the accuracy
of numerical Laplace inversion on the time displacement from the time
origin is studied in detail and a stepping algorithm that can provide

superior numerical accuracy in computing the time domain response of
linear circuits over a time interval of arbitrary length is introduced. The
chapter is summarized in Section 4.
1. Linear Single-Step
Predictor-Corrector Algorithms
Consider the first-order differential equation
where denotes time and Assume that is con-

tinuously differentiable with respect to time. Let the solution of (4.1)
at time instants and be given by and respectively.
Expand in Taylor series at with the time displacement
If is sufficiently small, the above series can be truncated at the first

order without introducing a large truncation error
Because (4.3) derives from the known point it is known

as the forward Euler formula. The forward Euler formula is explicit in
the sense that it computes directly from the present point whose
value and the first-order derivative are known. Forward Eu-
ler formula is also known as the first-order predictor. Because the trun-
cation error given by where is directly proportional
to (i) the square of the step size and (ii) the second-order derivative of
if varies rapidly with time, the step size must be kept suffi-
ciently small such that a reasonably good prediction of can be
obtained.
Numerical Integration of Differential Equations 55
We can also expand at with the time displacement

and truncate the series at the first order
Eq.(4.4) is known as the backward Euler formula. Note that the back-
ward Euler formula computes using which is also
unknown. To find an initial guess of is used. The
correct value of is obtained by solving (4.4) iteratively using
Newton-Raphson. Eq.(4.4) is therefore also known as the corrector.
It is well understood that Newton-Raphson provides quadratic con-
vergence provided that the initial estimate is sufficiently close to the so-
lution. In order to achieve fast convergence, the predictor is often used
to provide a starting point for the corrector, leading to the predictor-
corrector numerical integration algorithms. If the forward Euler formula
is used as the predictor and the backward Euler is used as the correc-
tor, the algorithm is known as the linear single-step predictor-corrector
(LSS-PC) algorithm. The essential steps of LSS-PC algorithm are given
as follows:
For a given time point with known and the forward

Euler formula is used to obtain an estimate of
The first-order time derivative of at is then obtained

from
These quantities are then substituted into (4.4), which is then solved
iteratively using Newton-Raphson.
It was shown in [5] that the numerical stability of the forward and
backward Euler formulae can be best studied using the following bench-
mark equation
where and denotes the complex domain. The solution of (4.5) is

given by
Eq.(4.6) shows that the system is stable if where de-

notes the real part of a complex variable. In what follows we examine
the stability of the LSS-PC algorithm.
Let us consider the forward Euler formula first. Applying the forward
Euler formula to (4.5) gives
where To have a bounded response for a given initial condition

when the following condition must be met
Let where and denotes the real domain, we have
In order to have a stable numerical solution, the step size must be such
that is confined within the unit circle centered at (-1,0), as shown in
Fig.4.1. It is seen that for large the step must be small enough in
order to ensure numerical stability of the forward Euler formula. The
following important conclusions are drawn with respect to the stability
of forward Euler formula:
If the system itself is unstable, from we have

forward Euler formula yields unstable response.
If (4.9) is violated, even though the system itself is stable, i.e.

the computed response from the forward Euler formula will be di-
verging.
In a very like manner, one can shown that the stable region of back-
ward Euler formula is given by
The above equation reveals that in order to have a stable numerical

solution, the step size must be such that is outside the unit circle
centered at (1,0), as shown in Fig.4.1.
It should be noted that if i.e. the system itself is unstable,
if the step size is chosen such that the response computed
from backward Euler formula will, however, be stable. We conclude from
the preceding analysis that:
Forward Euler formula could yield an erroneous diverging response

for a stable system.
Backward Euler formula could provide a false converging response for

an unstable system.
2. Linear Multi-Step Predictor-Corrector

Algorithms
The linear single-step predictor-corrector algorithms suffer from both
the poor accuracy and the lack of computational efficiency due to the
following reasons:
Only the first-order derivatives are used. With only the first-order
derivatives, for rapidly changing the step size must be kept suffi-
ciently small in order to meet the stability and accuracy requirements.
Only the information of the present and that of the most recent past
data point are used in estimation of Both the accuracy and
speed can be improved if more past data are used to predict
It is evident that in order to increase the step size and in the mean
time to improve the accuracy, more past data points and higher-order
derivatives should be used in prediction of Calculation of high-
order derivatives numerically is generally not only difficult and but also
costly. For this reason, in practice, multiple past data points are used,
but only the first-order derivatives at these data points are usually used
as a compromise to estimate leading to the linear multi-step
predictor-corrector (LMS-PC) algorithms.
Let a total of past data points, denoted by
and are known. Also assume the first-order time derivatives at these
past data points, denoted by and are known as
well. The predictor of LMS-PC that predicts the next data point
is given by
Note that the predictor uses only the known information of the past
points. The corrector of LMS-PC algorithm is given by
The corrector contains and that are both unknown. Eq. (4.12)
needs to be solved iteratively using Newton-Raphson iterations. Substi-
tuting (4.12) into (4.1)
Because and are constant for the derivative

of (4.13) with respect to gives
Newton-Raphson iterations proceed as follows
and
Integration stops when is sufficiently small.
3. Integration Using Numerical Laplace Inversion

LMS-PC algorithms improve the accuracy by employing more past
data. Its accuracy, however, is still limited because only the first-order
derivatives of the past data points are used. For linear circuits, the accu-
racy of numerical integration can be significantly improved by consider-
ing high-order derivatives. This section introduces a numerical Laplace
inversion based high-order numerical integration method for linear cir-
cuits.
3.1 Padé Polynomials

Padé approximates are a special type of rational fraction approxima-
tion to a given function. For a given power series
The Padé fraction
where and are polynomials in of orders N and M, re-

spectively, is used to approximate The coefficients of is
determined from
Eq.(4.19) indicates that the first M + N + 1 terms of matches

those of and the remaining terms are negligibly small. Assume
where M > N. Substituting these results into (4.19) yields
Making use of the identity that a polynomial is zero if and only all the
coefficients of the polynomial are identically zero, we arrive at
from which the coefficients of the Padé approximates can be determined.

They are given by
A special Padé polynomial is that for Because
Using (4.24), one can show that the Padé polynomial of is given by
where (M + N), match the corresponding coefficients of

the Taylor series expansion of The remaining terms differ. The
low-order Padé polynomials of are tabulated in Table 4.1.
3.2 Numerical Laplace Inversion

Laplace inversion derives the time domain response of a circuit
from its counterpart
where
and are Laplace transform and inverse Laplace transform

operators, respectively. The analytical solution of Laplace inverse trans-
form is available for a set of known functions only. For arbitrary func-
tions, numerical approximation is needed. Since varies from cir-
cuits to circuits, it is a natural choice to apply Padé approximation to

rather than Let where we arrive at
Next, we approximate using Padé polynomial given earlier
It was shown in [5] that under the condition all the poles
of are simple and are located in the right half of the complex
plane. As a result,
where and are the residues and poles of respectively.

The integral in Laplace inverse transform can thus be evaluated using
the residue theorem by closing the path of integration along an infinite
arc around the poles in the right half plane.
where is the displacement from the time origin. If is a real function,

then
where and Let us examine the properties of the

preceding numerical Laplace inversion in detail:
Because and where and are Dirac

impulse function and unit step function, respectively, the Laplace
transform of both Dirac impulse function and that of unit step func-
tion are well defined in Laplace domain, numerical Laplace inversion
thus provides an effective way to handle Dirac impulses and discon-
tinuities that exist in mixed-mode switching circuits and can not be
handled by conventional LMS-PC integration methods in the time
domain.
The computation of the time-domain response involves the frequency-

domain evaluation of the network function at frequencies
Since is independent of the network and time, the value
of and that of do not vary with circuits and can therefore be
pre-computed to a very high degree of accuracy and stored. Tables
4.2-4.5 tabulate the value of and that of for { N , M } = {2,4}
and {N, M} = {8,10} with 15 digits, the maximum accuracy of most
numerical packages at the present time.
The accuracy of numerical Laplace inversion depends upon

The order of Padé polynomial. When {N, M} = {8, 10} is used,

the corresponding order of integration is M + N +1 = 19, i.e. the
first 19 terms of the Taylor series expansion of are considered.
The order of integration is hence 18. Numerical Laplace inversion
is thus a high-order numerical integration method.
Because approximates the Taylor series expansion of
at the time origin to minimize the error, the time
displacement from the time origin should be kept small.
The method does not apply to nonlinear circuits simply because it

is generally difficult to obtain the response of nonlinear
circuits.
In what follows we use several examples to demonstrate the effective-

ness and accuracy of numerical Laplace inversion.
A. Dirac Impulse Function
Consider Dirac impulse function The function takes infinite value

at and zero at Because the time-domain value at
is obtained from
When {N, M} = {2, 4} is employed, because when 15 digits are used,

we have This agrees with the theoretical
result. We conclude that numerical Laplace inversion yields the correct
results of Dirac impulse function.
B. Unit Step Function
The unit step function is defined as
Its Laplace transform is given by Using numerical Laplace

inversion, its time-domain value at with {N, M} = {2, 4} is ob-
tained from
The relative error defined as
with is plotted in Fig.4.3. It is seen that numerical Laplace

inversion yields the accurate results of even for large step sizes. The
error is in the range of
C. Exponentially Decaying Function
The exponentially decaying function, represents the charac-

teristics of RC networks. Because
its time-domain response at with {N, M} = {2, 4} can be com-

puted from
The response is computed using Matlab with the maximum accuracy

(15 digits) [71]. Fig.4.4 plots the relative error. It is seen that numer-
ical Laplace inversion yields very accurate results of when
the step is small. The error increases drastically when the step size is
large. This agrees with our early statements that the error of numerical
Laplace inversion grows when the displacement from the time origin is
large.
D. RC Network
Consider the RC network shown in Fig.4.5. Let C = 1F, and

the input is a unit step function applied at Assuming zero initial
voltage of the capacitor. The exact output voltage is given by
Its counterpart is given by
The dependence of the normalized error between the exact solution and
that computed from numerical Laplace inversion with {N, M} = {2, 4}
on the step size is plotted in Fig.4.6. It is seen that the error decreases
monotonically when the size step is increased from to approxi-
mately The error, however, increases drastically when the step

size is large. Also observed is that an optimal step size exists. The large
relative error when is small is mainly due to The large error
when is large, however, is due to the large time displacement from the
time origin.
3.3 Multi-Step Numerical Laplace Inversion

Because numerical Laplace inversion is based on Padé approximation
of in the vicinity of the time origin, its accuracy deteriorates if the time
point has a large displacement from the time origin, as observed in the
preceding section. Practical applications usually require the time domain
behavior of circuits over a long period of time, Eq.(4.31) therefore can
not be applied directly.
An effective way to reduce the error due to a large time displacement
from the time origin is to divide the long time interval into multiple small
sub-intervals of equal width such that the results obtained from numer-
ical Laplace inversion is sufficiently accurate over these small intervals.

As long as the time origin is reset to the start of each sub-interval and
the effect of the initial conditions of the circuit at the start of the sub-
interval is accounted for, numerical Laplace inversion will yield accurate
results.
To illustrate this, let us consider the linear time-invariant circuit de-
picted by
where G and C are conductance and capacitance matrices formulated

using the modified nodal analysis, is the network variable vector,
and g is a constant vector specifying the nodes to which the input is
connected. Laplace transform of is obtained from
where
The time interval in which we are interested in the behavior of the circuit
is first divided into multiple small sub-intervals of equal width The
first sub-interval is given by (0, The circuit in this sub-interval is
depicted by (4.41). The response of the circuit at is given by
where
and
In the second step, we reset the time origin to The input

becomes and the initial condition becomes
subsequently. The circuit in the second sub-interval is depicted
by
Following the similar steps as those for the first sub-interval, one can
show that the response of the circuit at the end of the second sub-interval
is given by
Continuing this process, we obtain the response of the circuit at the end
of the sub-interval
The preceding algorithm computes the response of linear circuits over

a time interval of arbitrary length in a stepping manner, and is hence
termed the stepping algorithm. It is seen from (4.49) that is
the transition matrix of the circuit as it links the present state
to the next state in the absence of the input. on
the other hand, quantifies the response of the circuit when the initial
state is zero, and is hence termed the zero-state vector. The response
of the circuit is completely defined by the transition matrix and the
zero-state vector.
As an example, consider the RC network of Fig.4.5 studied earlier.

This time, the stepping algorithm is employed to compute the output
voltage of the network. When the initial condition of the capacitor is
considered, the output voltage in is given by
As seen in Fig.4.6 that when the step size is a small error in

the range of can be achieved. The response of the circuit from
to is computed with step size (100 steps).
Assuming that in the first step The response of the circuit
at is given by
In the second step, the voltage across the capacitor is given by and
the response is computed from
In the step
The relative error of the response computed using the non-stepping al-
gorithm and that using the stepping algorithm are shown in Fig. 4.7.
It is evident that the relative error is significantly reduced at large step
sizes when the stepping algorithm is employed.
In what follows we examine the properties of the stepping algorithm.
Input Waveform
Although in the preceding development, an exponential signal was

used as the input in the derivation of the stepping algorithm, the in-
put waveform is not restricted to be either sinusoidal or exponential.
A given input waveform can be represented by the linear combination

of a set of basic functions, possibly infinite, that are linearly indepen-
dent. The response of the circuits to each of these basis functions is
first computed separately and the complete response of the circuit is
then obtained by summing up its response to the basis functions.
As an illustration, consider a linear circuit. The input waveform
is shown in Fig.4.8. The input waveform is approximated with a
piecewise-liner input waveform shown in Fig.4.8.
The input in the interval is represented by
where is the unit step function. Note that the time origin of
(4.54) is at It can be shown that under the condition
the response is obtained from
where
and
are constant vectors for fixed step size The two basis functions
in this case are the unit step function defined earlier and the unit
ramping function defined as
This approach can be generalized to use an infinite number of basis

functions, such as Fourier series and wavelet, to represent arbitrary
input waveforms.
Efficiency
Because and are constant for fixed they only

need to be computed once and can be computed to high precision
prior to the start of simulation. Only one matrix multiplication and
one matrix addition are required in each step of simulation. No costly
Newton-Raphson iterations are required. The stepping algorithm is
computationally efficient.
Accuracy
Eq.(4.49) is accurate provided and are computed to

high precision. To ensure a high degree of accuracy, and
should be computed using numerical Laplace inversion of or-
der {N, M} = {8, 10} and fine step size. The followings give an
computationally efficient and yet numerically accurate algorithm that
computes these two quantities over a large number of fine steps.
To compute to high precision, we first divide into multiple
fine steps with equal step size From the definition of given
in (4.43), we see that the solution of the circuit
at gives the first column of Denote the first column of

by we have
Similarly, the second column of denoted by is obtained

from the response of the circuit
at Other columns of can be obtained in a similar manner.

To compute the time origin is reset from to The
initial condition becomes and the circuit is depicted
by
Note that there is no input in this step because the original input
dies out for The solution of the circuit at gives
Similarly we have
Combining these results, we arrive at

where
Continuing this process, one can show that
The cost for evaluating (4.66) can be greatly reduced if is chosen

to be where is an integer. For instance, if can
be obtain in only ten matrix multiplications.
Similarly, is obtained from
where
The preceding analysis shows that both and can be

computed efficiently over a large number of fine steps to achieve high
accuracy.
Stability
To investigate the stability of numerical Laplace inversion, we follow

the approach for Euler formulae and the same benchmark equation
(4.5) is used. The response of (4.5) at is obtained by using
numerical Laplace inversion
By letting we have
In the second step, the circuit is depicted by
It can be shown that the response at the end of the second step is
given by
Continuing this process, we arrive at
To ensure that (4.73) is bounded for the following condition

must be met
With this is equivalent to

It was shown in [5] that for M – N = 2, if numerical

Laplace inversion will yield a stable response. Numerical Laplace
inversion is therefore an absolutely stable (A-stable) numerical inte-
gration algorithm.
4. Summary
In this chapter, we have reviewed the linear single-step predictor-
corrector algorithms and linear multi-step predictor-corrector algorithms,
their imitations in analysis of mixed-mode switching circuits. Numer-
ical Laplace inversion that derives the time domain solution from its
response has been introduced. We have shown that Padé ap-
proximation based numerical Laplace inversion is a high-order numerical
integration method for linear circuits with accuracy orders of magnitude
higher as compared with LMS-PC algorithms. In addition, we have
shown that this method is capable of handling both impulses and dis-
continuities in network variables that can not be handled by LMS-PC
algorithms. The dependence of the accuracy of numerical Laplace inver-
sion on the time displacement from the time origin has been studied in
detail. For a given function, an optimal step size at which the error is
the minimal, exists. To improve accuracy, we have shown that the step-
ping algorithm with the step size set to the optimal step size can provide
superior numerical accuracy in computing the time domain response of
linear circuits over a time interval of arbitrary length.
II
TIME DOMAIN ANALYSIS

Chapter 5
INCONSISTENT INITIAL CONDITIONS
Inconsistent initial conditions arise from ideal switching and cause the
value of network variables immediately before switching to differ from
that immediately after switching. Because the topology of switching
circuits may change at switching instants, the value of network variables
immediately before switching, denoted by can not be used to
compute the response of circuits after switching. Instead, the value of the
network variables immediately after switching, denoted by must
be used to continue integration. This chapter investigates computer
methods that compute from
Section 1 investigates the cause of the inconsistent initial conditions
of mixed-mode switching circuits. Section 2 examines the two-step al-
gorithm derived from numerical Laplace inversion and its applications.
We show that the two-step algorithm is an accurate and computationally
efficient algorithm that yields from of linear circuits. Sec-
tion 3 shows that the conventional backward Euler formula is capable
of yielding from This approach is applicable to mixed-
mode switching circuits with both linear and nonlinear elements. In
addition, it is capable of computing the area of impulses at switching
instants. Section 4 presents a Taylor series based approach for deriving
from In Section 5, we show that the inconsistent initial
conditions encountered in nonlinear circuits can also be handled using
Volterra functional series based methods. Section 6 is concerned with
the detection of the existence of impulses at switching instants. The de-

termination of the existence of impulses at switching instants is critical
to the analysis of circuits with internally controlled switches as impulses
generated at switching instants are usually high enough to change the
states of other switches in the circuits. The chapter is summarized in
Section 7.
1. Inconsistent Initial Conditions

It was shown in Chapter 2 that the full-transistor model is capable of
capturing the rapidly time-varying transient characteristics of circuits.
Simulation based on the full-transistor model, however, is costly. The
use of this model is warranted only if the transient behavior of the cir-
cuit in the vicinity of switching instants is critically needed. Analysis
based on the voltage-modulated resistor model, on the other hand, is
much less expensive computationally. The large ratio of the ON and
OFF resistances of the voltage-modulated resistor model, however, gives
rise to stiff systems that have ill-conditioned circuit matrices and require
excessive simulation time. This drawback can be eliminated if the ideal
switch model that has zero resistance in the ON state and infinite re-
sistance in the OFF state is employed. Ideal switching, however, may
cause an abrupt change in nodal voltages due to impulsive capacitor cur-
rents, as shown in Fig.2.3. Similarly when inductors are encountered,
ideal switching may give rise to an abrupt change in loop currents, re-
sulting in impulsive inductor voltages. As a result, not only the value of
branch currents and nodal voltages immediately before switching may
differ from that immediately after switching, impulses are also generated
at switching instants. Difficulties arising from ideal switching include :
i) Impulses and discontinuities encountered at switching instants can

not be handled by conventional linear multi-step predictor-corrector
algorithms as these algorithms usually require the continuity of net-
work variables.
ii) Because switched circuits change their topology at switching instants,

and (immediately before switching) can not be used to
Inconsistent Initial Conditions 85
continue integration after switching. Instead, or (imme-

diately after switching) must be used.
iii) Impulses generated at switching instants may trigger the switching of

other switches that are controlled by internal variables of the circuits.
Numerical algorithms that compute from and the detec-

tion of the existence of impulses at switching instants are the focuses of
this chapter.
2. Numerical Laplace Inversion Based

Two-Step Algorithm
It was shown in Chapter 4 that numerical Laplace inversion is a high-
order numerical integration method that yields the accurate time domain
response of linear circuits. An important advantage of this approach is
that it is capable of handling both the impulses and discontinuities that
can not be handled by conventional numerical integration methods in
the time domain.
To illustrate this, consider the circuit shown in Fig.5.1. The output

voltage of the circuit is given by
Its time-domain response is given by

It is seen that the response contains both a Dirac impulse function and
an exponentially decaying function. Also Its time-domain
response at using {N, M} = {2, 4} is obtained from
If we evaluate (5.3) by opening the brackets
then with 15 digits, the first term of (5.4) vanishes and the second term
is identical to (4.38) except the negative sign. The relative error between
the analytical results and those from numerical Laplace inversion is the
curve-b in Fig.5.2, which is identical to Fig.4.4.
However, if (5.3) is evaluated without separating the terms associated
with the Dirac impulse function and those associated with exponentially
decaying function, the relative error is the curve-a in Fig.5.2. It is ob-
served that the relative error is much higher in this case, as compared
with curve-b.
Because for arbitrary networks, it is general not trivial to separate
the terms associated with the Dirac impulse function and those with-
out, the above results reveal that the existence of a Dirac impulse will
significantly increase the error of numerical Laplace inversion when the
time step is small. Because a Dirac impulse may exist at switching
instants in mixed-mode switching circuits, special algorithms are needed
to minimize the error in computing from Also observed is
that the relative error is large when the step size is small and decreases
monotonically with the increase in the step size until a minimum point
is reached. The error then increases rapidly if the step size is further
increased. This observation suggests that to achieve high accuracy in
the presence of impulses, the step size should not be too large, nor too
small. The use of large step size although avoiding the effect of Dirac
impulses at only yields a poor approximation of simply be-
cause the time point is distance away from the switching instant
It was shown in [47] that this difficulty can be overcome by first taking
a large forward step from to where As long as is
sufficiently large, the effect of Dirac impulse at dies out and the
result obtained at has good accuracy (in this example, ).
Note that the function must be continuous at This ensures
Second, a backward step of the same size is taken from
to the circuit in this case has no input nor its response
has a Dirac impulse. The capacitor, however, carries the initial voltage
as shown in Fig.5.1. The output voltage of the circuit in this step
is given by
and the response at the end of the backward step is obtained from
The normalized error between the analytical result and that

computed from numerical Laplace inversion using the two-step method is
plotted in Fig. 5.3. It is seen that a minimum error exists. For example,
when the normalized error is in the range of This result
demonstrates that for this particular circuit, if is used, the
relative error between and is in the range of
To demonstrate the effectiveness of the preceding two-step algorithm,

consider the circuit shown in Fig.5.4. Let the input be
It can be shown that the output voltage is given by

and
The response contains a Dirac impulse at We have

and The step size and {N, M} = {2, 4}
are used to compute the consistent initial condition. In the forward step,
the transfer function is given by
In the backward step, the time origin is reset to

The Dirac impulse in the input has died out in the forward step and the
input of the circuit in the backward step becomes Also,
the capacitor at the onset of the backward step carries the initial voltage
calculated from
The expression of the output voltage in the backward step

is given by
It is evident that With the step size

we arrive
It is seen that the two-step algorithm yields very accuracy result with
the relative difference
The preceding example reveals an important characteristic of mixed-

mode switching circuits at switching instants, that is the ex-
pression of network variables used in the forward step may differ from
that used in the backward step. The reasons for this are as follows :
i) The input of circuits immediately before switching may differ from

that immediately after switching. This is particularly true if the input
contains impulses at switching instants and step functions with the
step transition at switching instants.
ii) Impulsive network variables may exist at switching instants. Dirac
impulses make their appearance in the forward step only and die out
at the end of the forward step.
iii) The initial condition of circuit elements with memory at the onset of
the backward step may differ from that of these element at the onset
of the forward step.
3. Backward Euler Based Algorithms

The preceding numerical Laplace inversion based two-step algorithm
is most effective for linear circuits, and can not be applied to nonlinear
circuits simply because it is generally difficult to obtain the

response of these circuits. Nonlinear circuits are most often analyzed
using LMS-PC algorithms in the time domain, among which LSS-PC
algorithm, i.e. forward Euler as the predictor and backward Euler as
the corrector, is widely used. Although LMS-PC algorithms require the
continuity of network variables, it was demonstrated in [48] that the
backward Euler
is capable of handling Dirac impulses, subsequently inconsistent initial

conditions encountered at switching instants. To illustrate this, consider
step function It represents the discontinuity and its first-order
derivative gives the Dirac impulse function
Using the backward Euler, the derivatives of unit step function

is obtained from
Note that the first-order derivative was obtained from
Eq.(5.14) reveals that the derivatives of can be computed cor-

rectly using backward Euler despite of the discontinuity at
Applying backward Euler to the linear circuit depicted by
where G and C are the conductance and capacitance matrices respec-

tively and is the input vector, we obtain
In what follows we use the circuit shown in Fig.5.5 to demonstrate

the usefulness of (5.17) in handling impulses encountered at switching
instants. The switch was initially at position A and changes its position
from node A to node B at As a result, inductor carries an initial
current of 2A whereas inductor is initially at rest, i.e.
and also, The circuit in is
depicted by
from which we obtain the time-domain response
It is seen that both and contain a Dirac impulse of strength

at and on the other hand, are impulse-free. Also
observed is that and

and are discontinuous at
3.1 Two-Forward-Step Algorithm

Because no input to the circuit for we have In the
step immediately after Eq.(5.17) becomes
Its solution is given by
In the second step, and carry the initial currents and

respectively. Eq.(5.17) becomes
The solution is given by

Continuing this process, one can show that
Let us examine these results in detail prior to further development :
The impulses of and encountered at only affect

and as when They die out after
the first step and have no effect on the subsequent steps.
For small and can be quite large. If the circuit con-
tained switches that are internally controlled, such as diodes, they
could be activated and alter the topology of the circuits. Detection
of the existence of impulses at switching instants is therefore critical.
and provide an approximation of the area of the im-

pulses. The error of such an approximation can be determined from
These products can be used to detect the existence of impulses. If

when no impulse exists at Otherwise, an
impulse exists. This observation also suggests that the response of

circuits at the end of the step immediately after switching can be
written in the following general form
where is a constant, quantifying the strength of the impulse, and

is an impulse-free function, i.e. when
The subscripts “ici” specifies “inconsistent initial conditions”
whereas “ci” represents “consistent initial conditions”.
From the analytical results, we have and

Clearly, and can not be used to obtain and
and on the other hand, provide the correct value of
and when The same holds for and
as well.
If and are used to approximate and

respectively, the error can be determined as follows :
Since
we have
where we have neglected higher order terms because It is seen

that the relative error defined as
is given by and are used to approximate

and respectively, we have
The relative error is quantified by The preceding analysis shows

that the use of more forward steps does not warrant an improvement
in the accuracy. In fact the accuracy is reduced if more forward steps
are employed. Also observed is that the relative error is linearly
proportional to the step size
3.2 Two-Step Algorithm

To improve the accuracy, a two-step algorithm similar to that using
numerical Laplace inversion for switched linear circuits was proposed in
[48]. In this approach, a forward step from to is taken first.
It is then followed by a backward step of the same step size. Re-writing
(5.22) with step size gives
The solutions of (5.32) are given by
Because
It is seen that the relative error of the two-step algorithm is given

by which is proportional to Since usually the two-step
algorithm with one step forward and one equal step backward provides
better accuracy as compared with the preceding algorithm with two
equal forward steps.
3.3 Four-Step Algorithm

To investigate whether the use of more steps can lead to an improve-
ment in accuracy, a four-step approach in which two forward steps of
equal step size are taken first, followed by two backward steps of the
equal step size, is examined in this section. Using (5.23) as the initial
conditions of the first backward step, we have
The responses of (5.35) are given by

Further taking another equal step backward with (5.36) as the initial
conditions yields
The error is obtained from
The relative error is As compared with the error of the two-step

algorithm presented earlier, which is given by no improvement in
accuracy is achieved.
3.4 Two-Step Algorithm for Linear Circuits

The above two-step algorithm is applicable to both linear and nonlin-
ear circuits. For linear circuits, the consistent initial conditions can be
obtained as follows. Assume that switching occurs at and the
initial condition of the circuit is given by In the forward step,
Eq.(5.17) becomes
In the backward step, the initial condition vector is given by
Substituting (5.39) into (5.40) gives
where
For a fixed and are constant and can be computed in a

pre-processing step before the start of simulation. can therefore
be computed from directly.
4. Taylor Series Based Algorithm

It was shown in the preceding section that when inconsistent initial
conditions are encountered at switching instant Dirac impulses
make their appearance only in the step immediately after switching and
do not affect the response in steps thereafter. This observation suggests
that the response of the circuit in the step immediately after switching
can be written in the following form [48]
The first term in (5.43) represents the inconsistent initial conditions at

whereas the second term represents the consistent initial condi-
tions. In the second step, the effect of the Dirac impulse vanishes and
only the impulse-free component remains.
Because is continuous and impulse-free, we expand at

in its Taylor series with the time displacement and truncate the series
to the first order
Similarly,
can then be obtained from by solv-

ing (5.43), (5.45), and (5.46) simultaneously. Once they are available,
can be obtained by taking a backward step from where
Apply this method to the circuit in the preceding section, we have
The solutions of (5.48) are given by

Substituting these results into (5.47) yields
The error is obtained by expending (5.50) with
The relative error given by is higher as compared with that of

the two-step algorithm presented earlier. Also, in comparison with the
two-step method, this approach has the drawbacks of the high cost of
computation due to the need for and
The relative errors of the two forward-step, two-step, four-step, and
Taylor series based methods in computing are tabulated in Ta-
ble 4 and plotted in Fig.5.6. It is seen that the relative error of these
algorithms increases monotonically with the increase of the step size.
The two-step algorithm with one forward step and one backward step
provides the best accuracy.
5. Volterra Functional Series Based Algorithm

It is well known that Volterra functional series is an effective means for
the analysis of weakly nonlinear circuits in both the time and frequency
domain. It was shown in [20] that the response of a weakly nonlinear
circuit can be obtained by summing up the response of its Volterra
circuits
where is the response of the Volterra circuit. Writ-

ing (5.52) at the time instant immediately before switching and after
switching give
and
Eqs.(5.53) and (5.54) reveal that the consistent initial condition of a pe-
riodically switched nonlinear circuit can be obtained from that of its
Volterra circuits. An important advantage of this approach is that
because Volterra circuits are linear, the numerical Laplace inversion
based two-step algorithm can be employed to yield accurate from
We will come back to this in Chapter 7 in detail when we deal with

the analysis of periodically switched nonlinear circuits.
6. Existence of Dirac Impulses

at Switching Instants
The strength of impulsive voltage or currents generated by the switch-
ing of one switch may be quite large. Such a large current or voltage
may trigger other switches in the circuits that are controlled internally.
It is therefore critical to detect whether a Dirac impulse exists at ev-
ery switching instant in analysis of circuits with internally controlled
switches.
It was shown earlier that the response of circuits in the step immedi-
ately after switching can be decomposed into a consistent initial condi-
tion component, denoted by which is impulse-free, and an incon-
sistent initial condition component, denoted by mathematically
Because is continuous, we have

Also because
we arrive at
These results indicate that the existence of the impulsive component at

switching instants can be sensed by monitoring the integral
The integral is nonzero if contains a Dirac impulse at and zero,

otherwise. In what follows we show how (5.59) is evaluated numerically.
6.1 Dirac Impulses in Linear Circuits

For linear circuits, the integration of (5.59) can be evaluated conve-
niently using numerical Laplace inversion.
Notice that
we have
is thus obtained by first integrating from to and

then from to
It should, however, be noted that in the time interval

usually differ from that in the time interval due to the following
reasons :
Dirac impulses encountered at exist in the time interval

only and die out at the end of this time interval. In other words,
there will be no Dirac impulses in the backward step.
Circuit elements with memory at the onset of the backward step carry
initial conditions (capacitors have initial voltages and inductors have
initial currents). These initial conditions make their appearance in
in the backward step.
In the forward step, we have the step size
where the subscript specifies that the expression of is for the

network in the forward step, i.e. only. In the backward step,
we have the step size and the expression of is given by
As an example, consider the circuit in Fig.5.4. We have shown in

Chapter 5 that the response of the circuit in the forward step
is given by
Choose we have
In the backward step, the Dirac impulse in the input has died out.
Also, the capacitor carried a initial voltage of
The expression of the output voltage becomes
The integration in the backward step is thus computed from
The area of the impulse is then obtained from
The relative difference between the exact value of the area of the
impulse, which is -5, and that computed from the preceding steps is
only
6.2 Dirac Impulses in Nonlinear Circuits

For nonlinear circuits, the simplest approach to integrate over
the switching instant is the backward Euler formula. As pointed out
in the preceding section that Dirac impulses encountered at are
represented by a rectangular pulse of width and height Eq. (5.55)
can be written as
The integration over the step immediately after switching is obtained

from
If the result is zero when no impulse exists. Otherwise, an impulse

exists and the area of the impulse is quantified by
7. Summary
We have shown in this chapter that due to ideal switching, and
may differ, leading to inconsistent initial conditions and the cre-
ation of impulses at switching instants. Because the topology of circuits
changes before and after switching, instead of must be
used to continue integration after switching. Several computer methods
that compute from have been examined in detail in this
chapter. We have shown that for linear circuits, can be computed
efficiently using the numerical Laplace inversion based two-step algo-
rithm to achieve a high degree of accuracy. The accuracy of this method
depends upon the step size used in the integration. Both too small and
too large steps should be avoided.
To handle the inconsistent initial conditions of nonlinear circuits, nu-
merical Laplace inversion based approach is ineffective because it is dif-
ficult to obtain the response of these circuits. Backward Euler
formula, on the other hand, yields the correct consistent initial condi-
tions for both linear and nonlinear circuits immediately after switching.
The initial conditions can be obtained in two consecutive forward steps
from switching instants, one forward step and one backward step of equal
step size. The latter provides better accuracy. We have also shown that
two forward step, followed by two backward steps of identical step size,
through yield the correct consistent initial conditions, does not lead to
an improvement in accuracy. The Taylor series based approach also
fails to offer better accuracy. The consistent initial conditions can also
be obtained using Volterra functional series based approach where the
consistent initial conditions are obtained from those of corresponding
Volterra circuits that are linear. An advantage of this approach is that
numerical Laplace inversion based two-step algorithm can be used for
better accuracy.
In analysis of circuits with internally controlled switches, because the
state of these switches is determined by the network variables associated
with the switches and because the strength of the impulses generated
at switching instants can be quite large, the switching of one switch
may activate the switching of other switches in the circuits. This pro-
cess continues until no switching occurs. The detection of impulses at
switching becomes critical to the analysis of circuits with internally con-

trolled switches. The numerical methods for the detection of impulses
in both linear and nonlinear circuits have been presented.
Chapter 6
SAMPLED-DATA SIMULATION OF
LINEAR CIRCUITS
This chapter introduces an efficient and accurate numerical integra-

tion algorithm called sampled-data simulation for the time domain anal-
ysis of periodically switched linear circuits. Section 1 develops this al-
gorithm using Laplace transform and its inverse. Section 2 is concerned
with inconsistent initial conditions encountered in periodically switched
linear circuits and the algorithms that yield consistent initial conditions
of these circuits. Section 3 analyzes the sensitivity of the response of pe-
riodically switched linear circuits. The inconsistent initial conditions of
sensitivity networks are addressed in Section 4. In section 5, a computa-
tionally efficient statistical analysis method for computing the mean and
variance of the response of periodically switched linear circuits is pre-
sented. Section 6 addresses the noise analysis of periodically switched
linear circuits in the time domain. We show that by modeling white
noise using random pulses with the pulse width set by the noise band-
width of the circuit to be analyzed and the amplitude set by the output
noise power of the circuits due to the noise sources, the time domain re-
sponse of periodically switched linear circuits to both signals and noise
sources can be computed efficiently using sampled-data simulation. Sec-
tion 7 analyzes the effect of clock jitter on the response of periodically
switched linear circuits. By assuming that clock jitter is much smaller
than clock period, the response of periodically switched linear circuits in
the presence of clock jitter is computed efficiently. The chapter concludes

in Section 8.
1. Sampled-Data Simulation of Periodically

Switched Linear Circuits
Periodically switched linear circuits can be analyzed using LMS-PC
algorithms introduced in Chapter 4. The inconsistent initial conditions
encountered at switching instants can also be handled using Backward-
Euler based methods presented in Chapter 4. A major drawback of these
algorithms is their limited accuracy. High accuracy can be obtained at
the cost of small step size, subsequently long simulation time. In this
section, we introduce an accurate and computationally efficient method
for time domain analysis of periodically switched linear circuits. The
essential part of this section was originally reported in [18].
Consider a periodically switched linear circuit with the input
The circuit in phase is formulated using modified nodal analysis
where is the network variable vector in phase and are

the conductance and capacitance matrices in phase respectively, and
is a constant vector specifying the nodes to which the input is
connected in phase Laplace transform of (6.1) gives
where and is the Laplace transform of The

time-domain response is obtained from the inverse Laplace transform of
(6.2)
where
Sampled-Data Simulation of Periodically Switched Linear Circuits 111
and
Observed from (6.3) that :
is the state transition matrix quantifying the response of the

circuit from the initial state to the present state when
the input is removed. The first term on the right hand side of (6.3)
is hence the zero-input response of the circuit
is the zero-state vector specifying the response of the circuit to

the input with zero initial conditions. The second term on the right
hand side of (6.3) is thus the zero-state response of the circuit
is independent of the input. For a given circuit topology, it

needs to be computed once only.
is both topology and input-dependent. It must be re-computed

each time the input varies.
Both and are functions of the time displacement from

the time origin. If the time displacement changes, both and
must be re-computed.
Without the loss of generality, let the input be Writing

(6.3) for where T is the time step, yields
In the where the time origin is shifted from

to Subsequently, the input is changed to The
initial condition of the circuit becomes The circuit in this step
is depicted by
Following the same procedures as those for we arrive at
Let us examine the properties of (6.11):

If the frequency of the input and the step size T are kept un-
changed, and are constant. They only need to be
computed once and can be computed in a pre-processing step prior
to the start of simulation. The computation required in each step is
only one matrix-vector multiplication and one vector addition. The
response of the circuit is obtained at time points of the fixed time in-
terval T efficiently. The method is henceforth referred to as sampled-
data simulation.
The method is exact. No approximation is made in derivation of
the method. In order to obtain the accurate time domain response
of circuits numerically, both and must be computed
to high precision. In Chapter 4 we showed that a high degree of
accuracy can be achieved in computing and if the
multi-step numerical Laplace inversion algorithm is employed.
If the circuit has multiple exponential inputs with different frequen-
cies
the response of the circuit can be obtained using the principle of

superposition. Note that the zero-input response remains unchanged
as it is independent of inputs. The zero-state response, however,
becomes
where is the zero-state vector to the input and

is obtained from
where is a constant vector specifying the connection of the

input source to the circuit and
The complete response is given by
A special case of interest is when corresponding to a unit step

input. The response of the circuit to the unit step input is computed
from
Sinusoidal inputs can also be handled conveniently. For example, if

the response is given by
Similarly, if we have
The input waveform is not restricted to be either sinusoidal or ex-

ponential. A given input waveform can be represented by a set of
elementary basis functions. The response of circuits to each of these
basis functions is first computed separately. The complete response
of the circuit is then obtained by summing up its response to each of
these basis functions using the principle of superposition.
As an example, consider a linear circuit with its input approxi-

mated by the piecewise-linear waveform with step as shown
in Fig.6.1. The input in the time interval is given by
where
and is the unit step function. Note that should be chosen in

such a way that Nyquist theorem is not violated in representation of
using The time origin is reset to and the circuit in
the time interval is depicted by
Following the same procedures as those for circuits with an exponen-

tial input, one can show that the response of the circuit is given by
[49]
where
and
For fixed step size T, both and are constant and need
to be computed only once. In Appendix 6.A of this chapter, the
algorithms for computing and are given. Also note
that T should be chosen no larger than

It was shown in Chapter 2 that if the initial transient portion of the
response of mixed-mode switching circuits is not of a critical concern, it
is advantageous computationally to model switches as an ideal device.
Ideal switching, however, may cause an abrupt change in nodal voltages
or branch currents, giving rise to inconsistent initial conditions.
In Chapter 5, several numerical algorithms for computing from
of both linear and nonlinear switching circuits were examined in
detail. For linear circuits, the two-step method that is based on numeri-
cal Laplace inversion not only yields the correct consistent initial condi-
tions at switching instants, it also provides better accuracy as compared
with those that are based on backward Euler formula. In this section we
show that by incorporating the numerical Laplace inversion based two-
step algorithm into the preceding sampled-data simulation algorithm for
periodically switched linear circuits, the inconsistent initial conditions of
these circuits can be handled effectively [50].
Assume a switching occurs at and the network variables of

the circuit immediately before switching is given by To yield
from a forward step from to is
taken first, as shown graphically in Fig.6.2. The response at
is obtained from
The step size T should be chosen such that no switching at

i.e. Step size different from that of
other steps can be used in this step to ensure the continuity of at
Following the forward step, the time origin is reset to

The initial condition is subsequently given by and the input
becomes A backward step of the same step size
from to is then taken to compute
Because Laplace transform is defined from to only, to
accommodate the backward step, the transform
is employed. In the the time origin is and

the input becomes The circuit in the during
is depicted by
Using Laplace transform in the backward step, we obtain the response

at the time instant immediately after switching
where
is the transition matrix for the backward step and
is the zero-state vector for the backward step. Similar to and

if the step size T is fixed, ˆ and are constant
and need to be computed only once for a given network topology. Once
is available, integration continues from in a sampled-
data manner.
As an example, consider the circuit shown in Fig.6.3 with
and The input is a unit step current source. The
clock frequency is 5 Hz. The circuit is constructed in such a way that
no floating node exists in either clock phases. Both and are
modeled as ideal switches. The voltage at node 3 is computed using
the sampled-data simulation and is plotted in Fig.6.4, together with the
response from analytical analysis.
3. Time-Domain Sensitivity
The need for quantifying the effect of the variation of the value of
circuit parameters on the performance of the circuits is signified by the
trend that the minimum feature size of MOS devices in modern CMOS
technologies is being scaled down much more aggressively as compared
with the improvement in process tolerance [51]. For example, the resis-
tance of poly resistors in a typical CMOS process has an error of
±20% approximately and that of n-well resistors has an error of ±30%
approximately. Analysis of these effects is vital to both the performance
of circuits and the yield of production. As compared with costly statis-
tical analysis, such as Monte Carlo analysis, sensitivity analysis provides
a deterministic and effective measure of the effect of the variation of one
circuit parameter on the performance of the circuits.
The time domain sensitivity of the response of a periodically switched

linear circuit with respect to a circuit parameter is defined as
The normalized sensitivity defined as
removes the impact of the value of the parameter to which sensitivity

is calculated on the sensitivity. The sensitivity to parasitic parameters
whose value is usually extremely small can also be computed from
To obtain the time-domain sensitivity of the response of periodically

switched linear circuits to a circuit parameter we differentiate (6.1)
with respect to
Comparing the circuit depicted by (6.1) and that delineated by the above
expression one can see that both circuits are linear and have the same
topology but distinct inputs. The unknown of the circuit depicted by
the above equation is sensitivity and the circuit is hence called sensitiv-
ity network of For each circuit parameter, there is a corresponding
sensitivity network. The sensitivity networks have the identical topol-
ogy but distinct inputs. Also, these sensitivity networks are periodically
switched linear circuits with the same clock frequency as that of the
original circuit.
The time domain response of the sensitivity network is obtained by
differentiating (6.11) with respect to
The algorithm of (6.34) has the following properties:
For fixed T, and are constant. They can be com-

puted in a pre-processing step prior to the start of simulation, the
sensitivity of the circuit at time points of a fixed time interval can be
computed efficiently in two matrix-vector multiplications and three
vector additions. The algorithms that compute and
are given in Appendix 6.B of this chapter.
To compute must be available a priori.
No approximation is made in the derivation of the method. The

method is thus exact. To yield accurate sensitivity numerically,
and their derivatives to circuit parameters must be
computed to high precision. This is accomplished by using the multi-
step numerical Laplace inversion, as detailed in Appendix 6.B of this
chapter.
The algorithm computes the sensitivity to a single element in one

analysis of sensitivity network. For different circuit elements,
and must be re-computed. The method becomes costly if

sensitivities to a large number of circuit parameters are needed.
4. Inconsistent Initial Conditions of Sensitivity

Networks
Similar to the inconsistent initial conditions encountered in analysis
of the time domain response of periodically switched linear networks,
discontinuity may occur at switching instants of sensitivity networks.
We need to compute from Since sensitivity networks
are periodically switched linear circuits, the two-step algorithm effective
for computing the consistent initial conditions of periodically switched
linear circuits is applicable. In what follows, we detail this algorithm.
To compute from a forward step of step size T
is taken from is computed using (6.34) in the
forward step.
The step size T should be such that is continuous at i.e.

In the backward step, the sensitivity at the
time instant immediately after switching can be solved by differentiating
(6.29) with respect to
where
and
Similar to and for fixed T,
and are constant and need to be com-

puted only once. They can be computed along with
in a pre-processing step prior to the start of simu-
lation. Once these matrices and vectors are known, the time domain
sensitivity at time points of an equal interval can be obtained efficiently.
5. Statistical Analysis
5.1 Introduction
Sensitivity analysis is not capable of analyzing the joint effect of the
variation of multiple circuit parameters, especially when correlation ex-
ists. In addition, the results obtained are only valid at the nominal
value of circuit parameters and may not be valid at other values of
these random parameters. Worst-case analysis determines the bound-

ary of the design objective using the so-called corner technique. Due
to the over-estimation nature of the method, the results obtained usu-
ally lead to expensive over-designs [52]. Monte Carlo analysis, available
in most commercial CAD tools for circuit design, yields a converging
results only if the number of samples, each obtained from one circuit
analysis, is large. The effectiveness of these methods is often quickly
offset by the excessive computation, especially for periodically switched
circuits where the cost of computation of each circuit analysis is high.
Most recently, interval analysis has been applied to statistical analysis
of linear analog circuits [53]. Its application to statistical analysis of
time-varying circuits, specifically periodically switched linear circuits,
however, is yet to be exploited. In practice, to quantify the effect of
random variation of circuit parameters, designers often rely on costly
multiple runs of SPICE-type simulators to determine the upper and
lower bounds of circuit parameters, resulting in exceedingly long design
cycles. In this section, we introduce an explicit and computationally
efficient non-Monte Carlo method for statistical analysis of periodically
switched linear circuits in the time domain. The method computes the
first and second moments of the time domain response of periodically
switched linear circuits with normally distributed circuit parameters at
time points of an equal interval.
5.2 First-Order Second-Moment Method

In analysis of the mean and variance of the response of circuits, it is
often assumed that the value of circuit elements is normally distributed
with the mean to be the nominal value of the elements. When the
coefficient of variance of the circuit parameters, defined as the ratio of
the standard deviation of the circuit parameters to the mean of the
parameters, is small, the response of the circuit at denoted by
where x is the vector containing all random variables of the
circuits, can be approximated by only considering the first and second-
order terms of its Taylor series expansion at the mean of x
Where x, is normally dis-

tributed with and
are the gradient and Hessian of at respectively, and de-
note the real and complex domains, respectively, and M is the number
of random variables in the circuit. The mean of is obtained by
taking expectation of (6.39) and neglecting the moments whose order is
higher than two
where is the covariance of The variance of the

response, denoted by is obtained form
Substituting (6.40) into (6.41) and neglecting the moments whose order
exceeds 2 give
Eqs.(6.40) and (6.42) demonstrate that when up to the second-order

moments are considered, and are linear functions of
the covariance of the circuit parameters. The method is hence referred
to as the first-order second-moment (FOSM) method. It should be noted
that in derivation of FOSM method, the objective function is expended
at the mean of x. Recent study shows that approximation can also be
made at the boundary of the design objective and yields the advanced
first-order second-moment (AFOSM) method [54].
The accuracy of the method depends upon (i) the accuracy in com-
puting the derivatives of the response with respect to circuit parameters
and (ii) the accuracy of FOSM method. It was shown earlier that com-
putation of the derivatives of the response to circuit parameters can be
made very accurate if the multi-step numerical Laplace inversion algo-
rithms are employed. The accuracy of the method is thereby mainly
determined by that of FOSM method, which is determined by both the
coefficient of variance of circuit parameters, the degree of their corre-
lation, and the characteristics of the circuits. Because only up to the
second-order moments were considered in the derivation of FOSM, the
error of FOSM method will rise if or equivalently the
coefficient of variance of the circuit parameters are large.
6. Noise Analysis
Noise considered here is the small fluctuation of currents or voltages
that are generated within devices themselves. Noise coupled externally,
such as the switching noise generated by digital circuits and electromag-
netic interference, is excluded.
Noise encountered in integrated circuits typically includes thermal
noise, shot noise, and flicker noise among which thermal noise and shot
noise are white in nature. They have constant power spectral density
over a wide frequency range. The power spectral density of flicker noise,
however, is inversely proportional to frequency. The corner frequency of
the flicker noise of MOS devices is in the range of several MHz [2, 1]. Due
to the under-sampling of white noise sources by and the large bandwidth
of periodically switched linear circuits, the total output noise of these
circuits is usually dominated by the noise power folded over from the
sideband components of the white noise sources in the circuits [55]. For
this reason, in what follows only white noise is considered.
The two key issues encountered in time domain noise analysis are (i)
the generation of random noise signals in the time domain and (ii) the
accuracy of numerical integration methods used for solving circuits with
white noise sources.
6.1 Modeling of White Noise

There are two widely used methods for representing white noise in
the time domain. The first approach models a white noise source using
a set of sinusoids. It was shown in [56] that a stationary random process
in can be represented by
where and
Note that is a random variable. The usefulness of this approach

in practice, however, is rather limited, mainly due to the high cost of
computation because the circuit needs to be solved at frequencies
in order to yield the output noise power of the circuit.
The second approach represents a white noise source with a train of

pulses with the pulse width set by the noise bandwidth of the circuit
where is the equivalent noise bandwidth of the circuits
[19], and the pulse amplitude A set by where N(0,1) is
a normally distributed random number generator with zero mean and
unit standard deviation, and is the total output noise power of the
circuit due to the noise source, as shown graphically in Fig.6.5. is

obtained from
where is the power spectral density of the noise source and is

the equivalent noise bandwidth of the circuit. For white noise whose
power spectral sensitivity is independent of frequency, the equivalent
noise bandwidth, as shown in Fig.6.6, is determined from [2],
where is the transfer function from the white noise source to the
output of the circuit. For circuits whose frequency behavior is charac-
terized using the single-pole system with the pole at
we have
As an illustration, consider a resistor R with one-sided power spectral

density where is Boltzmann constant and T
is the absolute temperature in degrees Kelvin. Let the equivalent noise
bandwidth of the circuit in which R resides be The step
size used in representation of the thermal noise of the resistor in the time-
domain is given by Nyquist theorem seconds and the
total noise power of the resistor is calculated from
The time-domain noise waveform of the resistor is shown in Fig.6.7.
The power spectral density of the thermal noise of the resistor is ob-
tained by performing FFT on its time domain wave form. The spectrum
of the thermal noise of the resistor with 512 samples is shown in Fig.6.8,
the interval between two adjacent frequency samples can be calculated
from The average of ten sets of data of
the noise waveform has a mean of and standard deviation of
The averaged power is For reliable simulation, the
period of the pseudo-random number generator should be much larger

than simulation time, usually 10 times the simulation time.
6.2 The Algorithm

Numerical integration methods whose accuracy is sufficiently higher
than the amplitude of noise signals are needed for time domain noise
analysis. Conventional numerical integration methods that are based
on LMS-PC fail to provide the needed accuracy for noise analysis of
periodically switched linear circuits. It was shown earlier that sampled-
data simulation algorithm is an efficient and exact algorithm for time
domain analysis of linear circuits. In this section, we make use of this
algorithm to analyze the noise of periodically switched linear circuits.
Consider a periodically switched linear circuit with an input
and a set of white noise sources In the time
interval in phase the time origin is set to The
circuit in the time interval is depicted by
where and are constant vectors specifying the nodes of the

input and those of the noise source in phase respectively. The
time domain response is obtained from
where
and
An efficient algorithm for computing is given in Appendix

6.A of this chapter. At the boundary of adjacent clock phases, the two-
step algorithm is employed to compute from The
spectrum of the output noise of the circuit is obtained in a post FFT
analysis on a set of time-domain response data of the circuit in the steady
state.
6.3 Examples
Consider the switched capacitor integrator shown in Fig.6.9. The
clock frequency is 10 kHz. The clock has four equal phases per clock
period. The MOS switches are modeled as a resistor in series with
an ideal switch. The operational amplifier is modeled using the macro-
model [5] with 700 kHz unit-gain frequency. The noise of the operational
amplifiers is represented by the thermal noise of an equivalent resistor

at the non-inverting input terminal of the operational amplifier with the
resistance The output noise power spectrum is obtained
using the method presented in this section and the results are shown in
Fig. 6.10, together with the measurement results extracted from [57].
An excellent agreement is obtained.
7. Clock Jitter
Clock jitter causes clock period to deviate from its nominal value
to in a random manner, where is a random variable
with For practical circuits, usually holds. To
analyze the effect of clock jitter on the response of periodically switched
linear circuits, a change in the clock period is represented by a random
variation in the step size T of the sampled-data simulation, as shown in
Fig.6.11. Note that
where M is the number of steps that sampled-data simulation algorithm

takes in one clock period. The step size is changed from T to
for the step, where and Subsequently, both
and are changed to and

respectively. Because and can be
approximated from their Taylor series expansions of a finite terms
and
The algorithms for computing the time derivatives of and

are given in Appendix 6.C of this chapter. For small clock jitter, only
the first-order derivatives are usually needed. Note that for fixed T, the
derivatives need to be computed only once. The truncation errors can

be easily estimated from
and
where Once these derivatives are available, the response

of the circuit in the presence of clock jitter is obtained from
In simulation, is generated from

where is the standard deviation of the clock jitter and N(0,1) is a

normal random number generator with zero mean and unity standard
deviation.
8. Summary
Sampled-data simulation, an efficient, accurate, and absolutely stable
time domain algorithm for periodically switched linear circuits has been
developed in this chapter. We have shown that this algorithm computes
response, sensitivity, mean and variance of the response, output noise
power in the presence of white noise sources, and the effect of clock
jitter of periodically switched linear circuits at time points of a fixed
time interval. In computation of the time domain response, only one
matrix multiplication and one vector addition are needed in each time
step. Once the transition matrix and zero-state response vector
are computed to high precision, the response can be obtained
with a very high degree of accuracy. The inconsistent initial condi-
tions arising from ideal switching are handled using numerical Laplace
inversion based two-step algorithm effectively. In sensitivity analysis,
the sensitivity of the response of periodically switched linear circuits
to a circuit parameter is computed at time points of a fixed interval.
No approximation is made. A drawback of this method in sensitivity
analysis is that it yields the sensitivity of the response to one circuit pa-
rameter, rather than to all circuit parameters, in one network analysis.
It is therefore computationally costly if sensitivities to a large number
of circuit parameters are needed. In statistical analysis, the first-order
second-moment method that yields the mean and variance of the re-
sponse of periodically switched linear circuits without multiple analyses
of the circuits has been introduced. As compared with Monte Carlo
based methods, the method is computationally efficient. Because only
up to the second-order moments were considered in the derivation of the
first-order second-moment method, the accuracy of the method deterio-
rates if the coefficient of variance of circuit parameters is large. In noise
analysis, white noise signals of a given circuit are represented by a train
of pulses with the pulse width set by the noise bandwidth of the circuit
and the pulse amplitude set by the output noise power of the circuits
APPENDIX 6.A: Computation of and 135
due to the noise signals. Using sampled-data simulation, the response

of periodically switched linear circuits to both input signals and noise
sources can be computed to high precision. The power spectrum of the
output noise of the circuit is obtained in a post FFT analysis.
APPENDIX 6.A: Computation of and
In this appendix, we develop efficient and accurate algorithms for computing the
vectors and introduced in this chapter.
1. Computation of
Consider the circuit
Laplace transform of (6.A.1) is given by
It is seen that the response of the circuit is To compute for an arbitrary

T with a high degree of accuracy, a multi-step numerical Laplace inversion approach
similar to that for computing and given in the preceding chapters is
taken here. The time interval in which we are interested in the behavior of the circuit
is first divided into multiple small sub-intervals of equal width such that the error
of numerical Laplace inversion over each sub-interval is sufficiently small. The first
sub-interval is given by (0, Using numerical Laplace inversion, we obtain the
response of the circuit at
In the second step, the time origin is shift from to The circuit in this
step is depicted by
Following the same steps as those for we obtain
where
Continuing this process, we arrive at
2. Computation of
To compute we consider the circuit
It is seen that the response of the circuit is Following the same approach as
that for one can show that
3. Computation of
To compute we consider the circuit

APPENDIX 6.B 137
It is seen that the response of the circuit is In step 1, the circuit is depicted
by (6.A.10) and its time domain response is given by
In step 2, the time origin is reset to and the circuit is represented by
It can be shown that at
Continuing this process one obtain
Notice that in computing and numerical Laplace inversion is

performed in the first step only. Once and are
available, and can be computed efficiently and accurately in a
recursive manner.
APPENDIX 6.B: Computation of Parameter Deriva-

tives of and
It was shown in Chapter 4 that and can be computed using multi-
step numerical Laplace inversion to high precision as follows
and
relates to by
and
The derivatives with respect to a circuit element are obtained by differentiating

(6.B.1) and (6.B.2) with respect to directly
and
APPENDIX 6.C: Computation of Time Derivative of

and
The derivative terms can be computed using numerical Laplace inversion for high
precision. Making use of the property
we arrive at
and
These quantities can be computed simultaneously with and with little

additional computation.
Chapter 7
NONLINEAR CIRCUITS
Due to the aggressive reduction in both the feature size of devices and
the supply voltage of modern CMOS technologies, mixed-mode switching
circuits exhibit increasingly nonlinear characteristics. These nonlinear
characteristics include junction capacitances, nonlinear channel current
of MOSFET devices due to velocity saturation and mobility degradation
[58], the finite slew rate, clock feed-through and charge injection [59],
to name a few. To analyze the nonlinear behavior of these circuits,
general-purpose analog simulators, such as PSPICE and Spectre [60]
that use linear multi-step predictor-corrector algorithms [60, 61] as their
simulation engines, can be used. These algorithms, however, exhibit
the following deficiencies when analyzing periodically switched nonlinear
circuits, particularly when switches are modeled as an ideal device :
Inability to handle inconsistent initial conditions arising from ideal

switching [60]. Inconsistent initial conditions that may occur at
switching instants not only generate current or voltage impulses but
also cause network variables to exhibit discontinuous characteristics.
Both can not be handled by LMS-PC algorithms.
Reliance on Newton-Raphson iterations in every time step of inte-

gration to find the correct solution. Not only the cost of Newton-
Raphson is normally high, the step size used in these algorithms has
also to be kept sufficiently small so that a better starting point, and

subsequently quadratic convergence, can be achieved.
The accuracy of general-purpose analog simulators is limited by the

local truncation error (LTE) of the numerical methods used. Due
to stability constraints, the order of numerical integration algorithms
used by general-purpose analog simulators is low. Most SPICE-like
simulators employ only the first and second-order algorithms (back-
ward Euler and Trapezoidal).
This chapter investigates non LMS-PC algorithms for time-domain

analysis of periodically switched nonlinear circuits, specifically, it ex-
tends the sampled-data simulation algorithm for periodically switched
linear circuits given in the preceding chapter to periodically switched
nonlinear circuits with weakly nonlinearities. In addition, it extends the
two-step algorithm for periodically switched linear circuits to periodi-
cally switched nonlinear circuits to handle inconsistent initial conditions
encountered at switching instants. Both the response and sensitivity of
periodically switched nonlinear circuits at equally spaced time points are
investigated in this chapter. The chapter is organized as follows: Section
1 presents the multi-linear model of nonlinear elements typically encoun-
tered in periodically switched nonlinear circuits. Section 2 derives the
Volterra circuits of periodically switched nonlinear circuits. In Section 3,
a sampled-data simulation algorithm for periodically switched nonlinear
circuits is developed. A two-step algorithm for handling the inconsistent
initial conditions of these circuits is derived in Section 4. Section 5 is
concerned with the sensitivity analysis of periodically switched nonlin-
ear circuits. In Section 6, factors that affect the accuracy and efficiency
of the method are examined. The simulation results of example circuits
are presented in Section 7. The chapter concludes in Section 8.
1. Multi-Linear Theory
A large number of circuits encountered in telecommunication systems
operate at a fixed DC operating point and the signals to be processed
by these circuits are usually of small amplitude. The behavior of nonlin-
ear elements in these circuits can be characterized adequately using the
Sampled-Data Simulation of Periodically Switched Nonlinear Circuits 141
truncated Taylor series expansion of these nonlinear elements at their

DC operating points [45]. Elements of such a characteristic are said
to be weakly nonlinear. To illustrate this, consider a nonlinear voltage-
controlled voltage source in a periodically switched nonlinear circuit with
the input
where and are the controlling and controlled voltages of the

voltage-controlled voltage source in phase respectively, as shown in
Fig.7.1, and are constants. In phase the circuit is nonlinear
time-invariant. The network variable of the circuit can be represented
in their Volterra series to the order of 3
where is the Volterra series expansion of Rep-

resenting the voltages of both the controlling branch and that of the
controlled branch of the voltage-controlled voltage source in Volterra se-
ries of the input using (3.17) of the order of three, where is a
nonzero constant, and substituting the results into (7.1) give
Note that the second subscript in (7.3) specifies the order of Volterra
series expansion. Eq.(7.3) is a power series in Since a power series
equals to zero if and only if all the coefficients of the power series are
identically zero, we obtain
Note that in derivation of (7.4), we discarded Volterra series expansion

terms whose order is higher than 3. Eq.(7.4) reveals that the behavior
of the nonlinear voltage-controlled voltage source can be characterized
equivalently by three linear voltage-controlled voltage sources, as shown
in Fig.7.1. The effect of the nonlinear characteristics is accounted for by
the embedded nonlinear voltage sources in the second and third-order
circuits.
To derive the multi-linear model of nonlinear elements with memory,

let us consider a nonlinear capacitor modeled by
where and are the charge and voltage of the capacitor in the
phase, respectively, and are constants. To ensure that the
current of the capacitor vanishes outside phase the effect of the charge
of the capacitor at the onset of phase denoted by and
that at the end of phase denoted by must be accounted
for. This leads to
Representing and using Volterra

series to the order of 3 with the input substituting the results into
(7.6), and equating the terms of the same power in we arrive at
where and
are the terms of the Volterra series expansions of
and respectively. In a similar manner,
one can show that (7.5) can be written as
So the behavior of nonlinear capacitors in phase of a periodically

switched nonlinear circuit is completely characterized by the linear re-
lationships given by (7.7) and (7.8). Other nonlinear elements can be
handled in a similar manner and their multi-linear equivalent circuits
are shown in Fig.7.2.
2. Volterra Circuits
Having derived the multi-linear equivalent circuits of weakly nonlinear
elements, in this section we introduce the Volterra circuits of periodi-
cally switched nonlinear circuits. Consider a periodically switched linear
circuit with the input The circuit in phase is formulated

using modified nodal analysis
where is the network variable vector consisting of nodal voltages,

some branch currents, the charge of nonlinear capacitors, and the flux
of nonlinear inductors; and are the conductance and capacitance
matrices, respectively, containing linear elements and the first-order term
of the Taylor series expansion of the nonlinear elements. The higher
order terms are embedded in the nonlinear function and is a
constant vector specifying the nodes to which the input is connected
in phase Representing the network variable vector of the circuit using
Volterra series expansion
where is the term of the Volterra series expansion of

Evaluating the above expression at yields Volterra
series expansion of the initial condition of the circuit
Substituting these results into (7.9) yields,
with the initial condition where

and is a nonlinear function derived from the characteristics of the

nonlinear elements. The preceding development reveals that :
The periodically switched nonlinear circuit can be characterized equiv-

alently by a set of periodically switched linear circuits of the same
topology but distinct inputs. These periodically switched linear cir-
cuits are called Volterra circuits. The effect of the nonlinearities is
accounted for by the embedded nonlinear excitations of high-
order Volterra circuits.
The input of the Volterra circuit is a nonlinear function

of lower-order Volterra circuits only. To solve the Volterra
circuits, the response of Volterra circuits of orders must
be available.
The time domain solution of the nonlinear circuit is obtained by

summing up that of the corresponding Volterra circuits, as shown
graphically in Fig.7.3.
3. Sampled-Data Simulation of
Periodically Switched Nonlinear Circuits
The response of the first-order Volterra circuits in phase is obtained
using sampled-data simulation directly
To solve the second-order Volterra circuits, we use an interpolating

function that interpolates to approximate
There are many interpolation techniques available. Polynomial-based in-

terpolation, such as, Lagrange interpolation and Newton finite difference
interpolation [62], are effective for low-order interpolation and become
unstable once the order is high [63]. Exponential interpolation [64] is
effective only if the exponents are known. Fourier series interpolation is
an efficient interpolation method [63, 65]. The order of the interpola-
tion can be well above 1000 while still preserving the numerical stability.
An important advantage of high-order Fourier series interpolation is the
high accuracy of approximation.
To minimize the cost of computation, a simulation window of width
as shown in Fig.7.4, is employed. in the window is approxi-
mated using an interpolating Fourier series
where is given by [64, 66]

and is the interpolation error. The coefficients and

are determined from
where
Neglecting the interpolation error, the behavior of the second-order

Volterra circuits in the simulation window is depicted by
where is a constant vector specifying the nodes to which the input of

the second-order Volterra circuit is connected. Eq.(7.24) is solved using
the sampled-data simulation and the principle of superposition
where
For a different order of Volterra circuit, only a new set of coefficients

and need to be computed. They are obtained from
The response of higher-order Volterra circuits in the simulation window

can be computed in a similar manner
The response of the nonlinear circuit at time points in the window is

obtained by summing up that of the corresponding Volterra circuits
Because and are

constant, the only computation required for each simulation window is
to obtain and

Similar to periodically switched linear circuits, inconsistent initial con-
ditions may occur at switching instants in periodically switched nonlin-
ear circuits. In this section, we extend the two-step algorithm for com-
puting from of periodically switched linear circuits to
periodically switched nonlinear circuits.
Suppose a switching occurs at and the initial conditions of the
Volterra circuit immediately before the switching instant are
given by The forward step from to
yields
and
The step size must be properly chosen such that

A backward step from to is then
taken to yield
and
where
Finally the consistent initial conditions are obtained from
5. Sensitivity of Periodically Switched Nonlinear

Circuits
The time domain sensitivity of periodically switched nonlinear cir-
cuits to a circuit parameter is obtained by differentiating with
respect to
The above result reveals that the sensitivity of a periodically switched

nonlinear circuits can be obtained by summing up that of the corre-
sponding Volterra circuits.
The sensitivity of the first-order Volterra circuit is obtained from dif-
ferentiating (7.15) with respect to
To get the sensitivity of the order Volterra circuit, we differentiate

(7.28) with respect to
To calculate and we differentiate (7.27) with respect to
Since is a function of is a func-

tion of and and can
be computed once the response and sensitivity of the lower-order Volterra
circuits are available.
At the switching instants, the two-step algorithm is applied to ob-

tain the consistent initial conditions of sensitivity networks. Assume a
switching occurs at In the forward step, the sensitivity of the
Volterra circuits at is calculated using (7.36) and (7.37). In
the backward step, we calculate the sensitivity of the Volterra circuits
at is obtained by differentiating (7.32) and (7.33) with respect
to
and
Finally, the sensitivity immediately after switching is obtained by

summing up that of all Volterra circuits
6. Discussion
In this section we examine factors that affect the efficiency and ac-
curacy of sampled-data simulation of periodically switched nonlinear
circuits.
6.1 Stability
The stability of the method can be examined from that of the inter-
polating Fourier series and that of the sampled-data simulation of linear
circuits. Interpolating Fourier series has superior numerical stability
over polynomial-based interpolation schemes, as demonstrated in [63].
It was shown in [18] that sampled-data analysis for linear circuits is an
A-stable numerical integration algorithm. For a stable linear circuit it
guarantees a stable numerical solution.
6.2 The Maximum Step Size

The upper bound of the step size is subject to the constraint set by
Nyquist theorem. Specifically, because the highest frequency of the input
signal of the Volterra circuits is the frequency of the highest-order term
of the interpolating Fourier series given by
the lower bound of the sampling frequency is therefore given by
from which the maximum step size is obtained
The actual step size is determined from both the simulation accuracy
and CPU time and is usually much smaller than
6.3 Accuracy
The accuracy of the method depends upon the following factors :
The order of Taylor series expansion in representation of the charac-
teristics of nonlinear elements.
The order of Volterra series expansion in depicting nonlinear circuits.

The order of interpolating Fourier series in approximation of the input
of high-order Volterra circuits.
Simulation window.
Error propagation.
We examine each of them in detail.
6.3.1 The Order of Taylor Series Expansion

The order of the Taylor series expansion of nonlinear elements depends
upon the characteristics of the nonlinearities, the amplitude of the input
signal, and the tolerance of the error of approximation. When the
Taylor series expansion is employed to characterize the nonlinear
element, the truncation error is given by
where is the displacement from the operating point and

As an example, consider a forward biased diode characterized by
where and are the forward biasing voltage and current of the diode,
respectively, is the saturation current, and is the thermal voltage.
Let where and are the DC and AC components of
respectively. Expanding in Taylor series at the DC operating
point gives
where is the AC component of If the 4th-order Taylor series

expansion is used, the truncation error is estimated from
6.3.2 The Order of Volterra Series Expansion

The order of Volterra series expansion in depicting the nonlinear cir-
cuits depends upon the nonlinear characteristics of the circuits and the
error of approximation. Consider a nonlinear resistor characterized by
where and are the voltage and current of the resistor in phase
respectively, and are constants. Representing and in
their Volterra series expansions to the order of 3 and substituting the
results into (7.50) yields
Eq.(7.51) reveals that the nonlinear resistor can be represented by three

linear resistors, together with added voltage sources quantifying the non-
linear effect. If the 4th-order Volterra series expansion is considered, we
will have
The difference is the last equation in (7.52) that accounts for the effect
of the 4th-order nonlinear characteristic. Eq.(7.51) will be considered
adequate if the difference between the response of the circuit with the
3rd-order Volterra series expansions and that with the 4th-order Volterra
series expansions considered is negligible.
6.3.3 The Order of Interpolating Fourier Series

The solution of the first-order Volterra series is accurate provided that
and are computed to high precision. The error in solving
the second-order Volterra circuit is dominated by the interpolation error

To estimate this error, the input of the second-order Volterra
circuit is derived with the step sizes T and respectively. The order
of interpolation is determined from the normalized mean square error
(NMSE) [67]
where and are the response of the circuit with the

step sizes of T and respectively. In order to compute and
and are
needed. The relationship
and
can be employed to reduce computational cost.
6.3.4 Simulation Window

When a simulation window is employed it is assumed that the data
series sampled by the window is periodic. The rate of convergence of the
interpolating Fourier series depends upon the boundary condition of the
data series. It was shown in [67, 68] that a large error will exist if the
data series is discontinuous at the boundary, known as Gibb effect. The
error will be further increased if the derivatives of the function are also
discontinuous [69]. To minimize the error due to the discontinuity of the
function value at the boundary, the window should be chosen such that
the input of Volterra circuits is periodic with respect to the simulation
window. For circuits with only one sinusoidal input, the window size that
is the same as the period of the sinusoidal input meets this requirement
because the frequency components in the circuits consist of the frequency

of the input and its harmonics only. For circuits with non-sinusoidal
inputs or multiple sinusoidal inputs, this does not hold.
Consider the input of the second-order Volterra circuit
as shown in Fig.7.5. To reduce Gibb effect, we introduce
a new function
where is a constant, and impose The value of

is therefore given by
Because is periodic, interpolating Fourier

series can be employed to derive without introducing a large error.
Once is available, can be obtained from the inverse of the
transform
Using this technique the second-order Volterra circuit is depicted by
where and are the coefficients of the interpolating Fourier series

that interpolates The response of the
circuit in the window is obtained from
This approach can be further developed to minimize the error due to

the discontinuity of the derivatives of the function [69].
6.3.5 Error Propagation

Because the error due to the truncation of Taylor series and that of
Volterra series are usually insignificant for mildly nonlinear circuits. In
what follows only the interpolation error is considered. The interpolation
error in deriving the input of the second-order Volterra circuit, denoted
by as shown in Fig.7.6, gives rise to the error of the response of
the second-order Volterra circuit, is given by
where The sampled-data value of the input of the

third-order Volterra circuit is computed from
from which the input is approximated using interpolating Fourier series
The response of the third-order Volterra circuit is given by

where
and and are Laplace transform of and

respectively. The total error is obtained by summing up that of the
second and third-order Volterra circuits
7. Examples
In this section, the response and sensitivity of several periodically
switched nonlinear circuits are analyzed using the algorithms presented
in this chapter .
7.1 Time-Invariant Nonlinear Circuits

The first example considered is the current-mirror amplifier shown
in Fig.7.7 with the value of the circuit parameters given in Table 7.7.
The amplifier is a building block for continuous-time current-mode cir-
cuits [70]. Neglecting channel-length modulation and other second-order
effects, we obtain the AC component of the channel current
where
is the linear transconductance and
is the second-order nonlinear transconductance, is the surface mobil-

ity of free electrons, is the gate capacitance per unit area, W and L
are the width and length of the transistors, respectively, and are
the biasing voltage and the threshold voltage, respectively. The AC cir-
cuit of the amplifier is shown in Fig.7.7 where only intrinsic capacitances
are considered. The output current is computed using both sampled-
data simulation and LSS-PC. The results are shown in Fig.7.8 with and
without the gate-to-source capacitance and gate-to-drain capacitance
considered. It is seen that when the capacitance is not considered, the
amplifier realizes When the capacitance is considered, the
output current is reduced. The results from sampled-data simulation
are in a good agreement with those from LSS-PC analysis.
The second example of time-invariant nonlinear circuit is shown in

Fig.7.9 with the value of the circuit parameters given in Table 7.9. The
nonlinear conductor is characterized by
The voltage across is computed using both sampled-data simulation

and LSS-PC algorithms. The number of steps per simulation window for
sampled-data simulation and LSS-PC is 20 and 100, respectively. It was
observed that if the number of steps per simulation window in LSS-PC
is lower than 100, a significant error exists. The results are shown in
Fig.7.10 for various input amplitudes. The difference between sampled-
data simulation and LSS-PC is plotted in Fig.7.11. It is seen that the

maximum normalized difference is nearly 1%.
The error due to the order of the interpolating Fourier series is shown
in Fig.7.12 with the input amplitude 0.5A, It is observed that an increase
in the order of the interpolating Fourier series lowers the error.
The computational efficiency is demonstrated in Fig.7.13 where the
CPU time is plotted as a function of the number of simulation windows.
The CPU time is measured for both sampled-data simulation and LSS-
PC programs coded in Matlab, an interactive mathematical language
that runs in an interpretive mode [71]. The program was executed on
Sun Ultra 1 workstation with 450 MHz CPU and 256MB RAM. It is seen
the initial cost of computation of sampled-data simulation is higher than
that of LSS-PC, mainly due to the cost of the pre-processing step. The
CPU time of LSS-PC analysis arises rapidly with the number of simu-
lation windows, whereas that of sampled-data simulation arises slowly,
indicating that the computational cost of sampled-data simulation is

nearly independent of the number of simulation windows.
7.2 Switched Capacitor Integrator

with Nonlinear Op Amp
Consider the switched capacitor integrator shown in Fig. 7.14.
The nonlinear gain of the operational amplifier is
modeled as The clock frequency
is 100 kHz and the input is a cosine wave. The output response and its
sensitivity to are obtained using sampled-data simulation and the
results are shown in Fig.7.15.
The sensitivity results are computed using sampled-data simulation
and brute-force approach with 1% parameter variation. The results are
as plotted in Fig.7.16. A good agreement is observed.
7.3 General Periodically Switched Nonlinear

Circuits
Consider the circuit shown in Fig.7.17 that contains two externally
clocked switches. The clock phases are non-overlapping. The voltages
of the two capacitors are well defined inside either clock phases but
discontinue at switching instants. The clock frequency of the circuit is
5 Hz. Each clock period has two phases of equal width. Zero initial
conditions were assumed for all capacitors. The nonlinear conductor
was modeled as
where are constants and their values are given by

The input was a unit step current source. To simplify
the simulation, the width of the simulation window was set to be the
same as that of the clock phase. The number of samples per window
was 20. The voltages at all nodes were solved using sampled-data simu-
lation and the voltage at node 3 are plotted in Fig.7.18. As shown in the
figure, the voltage at node 3 is discontinuous at
where inconsistent initial conditions are encountered and continuous at
where only consistent initial conditions are en-
countered. This observation demonstrates that sampled-data simulation
can handle both the inconsistent and consistent initial conditions at the
switching instants. The results from PSPICE analysis are also plotted
in the figure for comparison.
The normalized difference between the results from sampled-data sim-
ulation and those from PSPICE are measured. Two different situations
are considered. Inside each clock phase where no discontinuity in the
response, the normalized difference for time points except switching in-
stants is defined as
where and are the response of sampled-data simulation and

PSPICB, respectively. It can be obtained directly from the responses,
and is shown in Fig.7.19. It is seen that the maximum normalized dif-
ference is below 0.5%.
At the switching instants, a direct comparison of the results from
sampled-data simulation and PSPICE is difficult. The reason is as fol-
lows: If a switching action causes response discontinuity at al-
though the inconsistent initial conditions immediately before and after
switching and can be obtained from sampled-data simula-
tion, they can not be obtained from PSPICE. For traditional integration
methods, such as those used in PSPICE, the continuity of network vari-
ables is required. In order to handle a rapid change in the response,
very small time steps must be taken to ensure the accuracy of integra-
tion. No time point can be clearly defined as a switching instant. At the
switching instants, the initial conditions from sampled-data simulation
are verified by checking the charge conservation before and after switch-
ing. The total charge on capacitors and immediately before and

after switching is computed and plotted in Fig.7.20.
The sensitivities of the output voltage with respect to conductor
and capacitor were calculated using sampled-data simulation with
the same settings as those used in response simulation. They were also
calculated using the brute-force method as follows
1% variation in the nominal value of conductor and capacitor was

used to calculate the sensitivity in the brute-force. The results are shown
in Fig. 7.21 for the sensitivity to and Fig. 7.22 for the sensitivity to
It is seen that the results from the sampled-data simulation and the
brute-force match well.
8. Summary
Sampled-data simulation of the response and sensitivity of periodi-
cally switched circuits with weak nonlinearities has been presented. The
method characterizes the behavior of these circuits using a set of period-
ically switched linear circuits called Volterra circuits that have identical
topology but distinct inputs. The input of high-order Volterra circuits
is a nonlinear function of the response of lower order Volterra circuits
only. The analytical expression of the input of high-order Volterra cir-
cuits is approximated using interpolating Fourier series that interpolates

the value of the input of the Volterra circuits at time points of a fixed in-
terval. The sampled-data simulation algorithm for linear circuits is used
to solve the Volterra circuits. In addition, the two-step algorithm for
periodically switched linear circuits is utilized to compute the consistent
initial condition of the Volterra circuits, subsequently, that of periodi-
cally switched nonlinear circuits. Both the response and sensitivity of
periodically switched nonlinear circuits are obtained at equally spaced
intervals of time.
The method achieves superior computational efficiency by avoiding
costly Newton-Raphson iterations. Also, high numerical accuracy is
achieved by employing high-order interpolating Fourier series.
The method is most effective and computationally efficient for periodi-
cally switched nonlinear circuits with mild nonlinearities whose behavior
can be characterized sufficiently using the low-order Volterra series ex-
pansion. For circuits with harsh nonlinearities, such as comparators and
Schmitt triggers, other methods such as those that are based on behavior
modeling [18], can be used instead. The method is a general computer-
oriented formulation method that can be applied to mildly nonlinear
circuits with externally clocked switches including switched capacitor
networks and switched current networks.
Chapter 8
CIRCUITS WITH INTERNALLY
CONTROLLED SWITCHES
Internally controlled switches are switches whose state (ON or OFF) is

controlled by the internal network variables associated with the switches.
The switching time at which internally controlled switches change their
state is not known at the start of simulation. This differs fundamen-
tally from circuits with externally clocked switches where the state of
switches in these circuits is solely determined by the state of external
clocks and is known a priori. More importantly, the topology of circuits
with internally controlled switches may change at any time, depending
upon the value of the switching variable of internally controlled switches
that controls the state of these switches. Moreover, the switching of
one internally controlled switch may trigger other internally controlled
switches in the circuits, subsequently further altering the topology of
the circuits. As compared with the analysis of circuits with externally
clocked switches, the evaluation of the switching variable of internally
controlled switches must be carried out in each time step of simulation
and at each time instant at which an internally controlled switch changes
its state in order to detect any change in the topology of the circuits.
This significantly complicates the analysis.
This chapter is concerned with the analysis of circuits with internally
controlled switches. In Section 1, the switching variable of internally
controlled switches typically encountered in mixed-mode switching cir-
cuits is defined. We show that the switching variable of each internally
controlled switch must be evaluated in each step of simulation in or-

der to determine the state of the switch. In Section 2, methods that
compute the time instant at which internally controlled switches change
their state are developed. Section 3 examines the generation of impulsive
network variables at switching instants and its complication in analysis
of circuits with internally controlled switches. We show that impulses
generated at switching instants not only give rise to inconsistent initial
conditions, they may also initiate a sequence of switching activities of
other internally controlled switches in the circuits. In Section 4, a lin-
ear voltage regulator is used as an example to illustrate the analysis
of circuits with internally controlled switches in detail. The chapter is
summarized in Section 5 with concluding remarks.
1. Internally Controlled Switches and Switching

Variables
Unlike circuits with externally clocked switches, the time instants at
which the topology of circuits with internally controlled switches changes
are determined by the state of the switching variable of the switches in
the circuits only. The switching variable of an internally controlled
switch controls the state (ON or OFF) of the switch in accordance with
the following criterion
In what follows we examine internally controlled switches typically

encountered in mixed-mode switching circuits and the switching variable
characterizing the state of these switches.
1.1 Diodes
Ideal diodes are the simplest internally controlled switches. The op-
eration of an ideal diode is controlled by the voltage across the diode, as
shown in Fig.8.1. The switching variable of an ideal diode is the forward
biasing voltage of the diode.
Sampled-Data Simulation of Circuits with Internally Controlled Switches 179
Diodes belong to the category of voltage-controlled switches. The

constitutive equation of the diode is given by
1.2 MOSFETs
MOSFETs switches are controlled by the effective gate-source voltage
of the devices, as shown in Fig.8.2. The switching variable of a NMOS
switch is defined as
where is the threshold voltage of the NMOS switch. The constitu-

tive equation of the NMOS switch is given by
MOSFET switches also fall into the category of voltage-controlled

switches.
1.3 Static CMOS Inverters

The switching variable of the complementary static CMOS inverter
shown in Fig.8.3 is defined as
where is the threshold voltage of the inverter. For most applications,

and is achieved by the appropriate sizing of the NMOS and
PMOS transistors. The output of the inverter is solely controlled by its
input in accordance with
1.4 Comparators
Comparators are used extensively in sigma-delta modulators as quan-
tizers. Both voltage-mode and current-mode comparators are available,
as shown in Fig.8.4. The output of clocked comparators updates itself
at the clocking instants only and remains unchanged during clocking
phases, whereas the output of unclocked comparator is transparent to
the inputs.
The switching variable of an ideal voltage-mode comparators is defined
as
and the constitutive equation of the comparator is given by
where is a user-defined voltage. It is evident that a voltage-mode

comparator is a voltage-controlled switch.
The switching variable of a current-mode comparator is given by
where is the input current to the comparator. The constitutive

equation of the current-mode comparator is given by
Current-mode comparators are current-controlled switches.

The switching variable of other types of internally controlled switches,
such as thyristors, can also be defined in a similar way.
2. Switching Instants
It was seen in the preceding section that a change in the polarity of
the switching variable of an internally controlled switch indicates a
change in the state of the switch. At the switching instant, the following
equation holds [14, 15]
The switching time is obtained by solving (8.12) using iterative algo-

rithms, such as Newton-Raphson [14].

It was shown in Chapter 5 that when a switching occurs at
the value of network variables immediately after the switching can be
written as
where denotes the consistent initial condition and denotes

the inconsistent initial condition. Note both and are finite and
can be stored. Also, only makes its appearance at the switching
instant. If no impulsive network variables will exist in the
circuit. Otherwise, inconsistent initial conditions will be encountered.
together with are used to test each internally controlled
switch at switching instants to determine whether a violation of the
switching condition occurs. Because the switching of one internally con-
trolled switch may trigger the switching of other internally controlled
switches, either due to or the evaluation of the switching
condition of all internally controlled switches must continue until there
is no switching condition violation. It is only after no switching condi-

tion violations exist, the final topology of the circuit at the switching
instant can be established, and the two-step algorithms introduced
in Chapter 5 can be employed to compute from Once
is available, simulation proceeds forward in time.
It should be emphasized that at the switching instant of each
internally controlled switch, not only the detection of whether impulsive
network variables may be generated at the switching instant must be
conducted, the value of the network variables at the time instant imme-
diately after the switching, i.e must also be carried out to update
the initial condition of the circuit so that the detection of the switching
of other internally controlled switches at the same time instant can be
carried out.
4. Examples
In this section we use the linear voltage regulator shown in Fig.8.5
as an example to demonstrate the analysis of circuits with internally
controlled switches.
The basic operation of the voltage regulator is as follows : The MOS-
FET switch is controlled by an external clock with variable duty cycle.
When the supply voltage E supplies a current to the series induc-
tor L and the load resistor R. Because the output is current, the value
of the load resistor R is small. The functionality of the shunt capacitor
C is to sustain the output voltage, whereas that of the series inductor
L is to sustain the output current in the absence of E. The value of L
and that of C must, therefore, be sufficiently large so that the ripple of
the output current and that of the output voltage during the absence of
E are small. When E is disconnected from the load. The output
current is sustained by the magnetic energy stored in the series inductor
and the electric energy stored in the shunt capacitor. By adjusting the
duty cycle of the switching MOSFET given by the average
output current can be controlled and is given by
Since The voltage regulator is also known as step-down

chopper.
For a detailed analysis of the operation of the regulator, we examine

the operation of the regulator in the following four different time regions:
i) The MOSFET switch is ON.
ii) The MOSFET switch is turning OFF.
iii) The MOSFET switch is OFF.

iv) The MOSFET switch is turning ON.
The regulator exhibits distinct characteristics in these four different

regions.
Assume during the clock phase The schematic

of the voltage regulator when is shown in Fig.8.6. Reset the
time origin from to The circuit at is depicted
by
or symbolically
where
and
Note that because for the diode is OFF during

the clock phase. The time domain response of the circuit can be
computed conveniently using the sampled-data simulation of linear
circuits given in Chapter 6.
where M(T) and U(T) were defined earlier.
When the MOSFET switch turns OFF at the circuit

schematic is shown in Fig.8.7. Reset the time origin from
to Note that the inductor carries an initial current
and the capacitor has an initial voltage The behavior of the
circuit at the switching instant is depicted by
The state of the diode can be determined by evaluating

If the diode will turn ON. Otherwise, it re-
mains OFF. Due to the effect of Dirac impulse,
holds for any value of and The diode will turn

ON immediately after the MOSFET switch turns OFF. The voltage
regulator will have a new topology after the diode is ON.
Numerically, the determination of whether the circuit change its
topology at the switching instant is achieved by first exam-
ining whether the switching variable of the diode contains a Dirac
impulse function. This is achieved by using the method given in

Chapter 5, specifically, by evaluating the following integral
Because
and
If the switching variable of the diode contains a Dirac im-

pulse. Otherwise, only consistent initial conditions will be encoun-
tered at the switching instant. The consistent initial condition
is obtained by employing the two-step algorithms given in Chapter
5. Once and are available, the switching variable of the
diode given by is evaluated at In this case,
since and is non-zero, an impulsive
forward biasing voltage exists across the diode and the diode turns
ON at
When the MOSFET switch is open for
Again, we reset the time origin from to The circuit
at is depicted by
or symbolically
The response of the regulator with can be obtained from
When the MOSFET switch turns ON at we reset the

time origin from to It can be shown that
No impulsive network variables will be encountered at the switching

instant. Only the consistent initial conditions exist. The initial con-
ditions can then be updated easily and simulation proceeds forward
to the next clock cycle.
The preceding example exemplifies the procedures of the analysis of

circuits with internally controlled switches, which can be summarized as
follows :
Step 1 At the start of simulation, an initial state is assigned to each inter-

nally controlled switch in the circuit. Simulation starts with a given
initial condition
Step 2 is computed using the sampled-data simulation, along with

the evaluation of the switching variable vector
Step 3 When a sign change of is detected, revealing the switching of an

internally controlled switch in the time interval iteration
algorithms are employed to allocate the exact switching instant
The solution of the circuit at is saved.
Step 4 Determine whether impulsive network variables are generated at the

switching instant by evaluating the integral Also,
the two-step algorithms given in Chapter 5 are employed to compute
Step 5 Re-evaluate the switching variable vector with the newly obtained
initial condition. If experiences a sign change from the time step
immediately before switching and go to Step 4. Otherwise,
go to Step 6.
Step 6 Sampled-data simulation proceeds.
5. Summary
The analysis of circuits with internally controlled switches has been
presented. The definition of the switching variable of internally con-
trolled switches typically encountered in mixed-mode switching circuits
has been presented. We have shown that the switching variable of each
internally controlled switch must be evaluated in each step of simulation
in order to determine the state of the switch. We have also shown that
impulses generated at switching instants may lead to the violation of
switching conditions of other internally controlled switches in the cir-
cuits and trigger the switching of these switches. This process continues
until there are no more violations of the switching condition of internally
controlled switches. The final topology of the circuit at the switching
instant can then be determined and the consistent initial can be deter-
mined.
The method presented in this chapter does not involve any approxi-
mation, nor does it require the storage of the numerical value of Dirac
impulse function. The sampled-data simulation algorithms, together
with the methods of this chapter can be integrated to analyze linear cir-
cuits with both internally controlled and externally clocked switches. For
nonlinear circuits with both internally controlled and externally clocked
switches, the method allows us to determine the topology of the circuit
at switching instants and the consistent initial conditions of the new cir-
cuit so that algorithms for nonlinear circuits, such as Newton-Raphson
and the method presented in Chapter 7, can be employed to analyze
these circuits effectively.
Chapter 9
OVER-SAMPLED SIGMA-DELTA
MODULATORS
This chapter applies the sampled-data simulation algorithm for peri-

odically switched linear circuits presented in Chapter 6 to a special class
of nonlinear circuits - over-sampled sigma-delta modulators. Section
1 presents the characteristics of over-sampled sigma-delta modulators
and the difficulties encountered in analysis of these circuits. In Section
2, the behavior modeling of clocked quantizers of over-sampled sigma-
delta modulators that convert analog signals into a sequence of digital
bits is investigated. Unclocked quantizers are addressed in Section 3.
We show that by utilizing the methods for circuits with internally con-
trolled switches, sigma-delta modulators with unclocked quantizers can
be analyzed. Section 4 investigates the modeling of single-bit digital-
to-analog data converters. The modeling of other blocks of sigma-delta
modulators are dealt with in Section 5. In Section 6, the simulation
methods that utilizing both the behavioral modeling of the quantizers
and the sampled-data simulation of periodically switched linear circuits
are addressed in detail. In Section 7, both continuous-time and switched
capacitor over-sampled sigma-delta modulators are analyzed using the
method developed in this chapter and the results are presented. Con-
cluding remarks are given in Section 8.
1. Introduction
Over-sampled sigma-delta modulators are widely encountered in analog-
to-digital data conversion[72]. These modulators trade off speed for ac-
curacy, and can achieve a high precision resolution without requiring
precisely matched analog components. In addition, they can be fabri-
cated on the same substrate with other digital circuitry using standard
digital fabrication technologies. A typical configuration of a clocked first-
order over-sampled sigma-delta modulator is shown in Fig.9.1. The key
element of over-sampled sigma-delta modulators is the quantizers, imple-
mented using comparators with one input from the output of the integra-
tor and the other the ground, that quantizes the incoming analog signal
and outputs a stream of digital data. These serial digital data stream
is then converted to parallel data using a decimator. The main function
of the integrator in the forward path is to sense the difference between
the incoming analog signal and the output of digital-to-analog converter
and drive the difference to zero in an integrating manner. Single-bit
oversampled sigma-delta modulators are the most widely used, owing to
their intrinsic advantages of the ease in implementation and insensitivity
to non-idealities of integrators.
Sampled-Data Simulation of Over-Sampled Sigma-Delta Modulators 193
Due to the over-sampling nature of over-sampled sigma-delta modula-

tors, switched capacitor networks or switched current networks with the
clock frequency that is much higher than that of the frequency of input
signals are the circuit techniques for the realization of these modulators.
The over-sampling ratio, defined as the ratio of the clock frequency to the
frequency of the input signals, is usually in the range of 16~64. Although
over-sampled sigma-delta modulators are relatively simple circuits, sim-
ulation of these circuits is rather difficult, mainly due to the following
reasons :
Comparators are harsh nonlinear elements, as shown in Fig.9.2. The

output-input relation of the quantizers can not be characterized us-
ing Taylor series expansion. As a result, methods for linear circuits
and those introduced in Chapter 7 for circuits with mildly nonlinear
elements can not be used to analyze these circuits.
Sigma-delta modulators are dual-time circuits. They contain a high-

frequency clock and a slowly varying input signal. The circuit has to
be simulated over a large number of clock cycles with fine time steps
in order to obtain the performance characteristics, such as signal-to-
noise ratio and dynamic range, of these circuits reliably, resulting in
excessive simulation time.
High simulation accuracy requirement. For example, the resolution of

a 16-bit analog-to-digital data converter with a 1V constant voltage
input is only The accuracy of numerical algo-

rithms must be sufficiently higher than this limit in order to analyze
these circuits.
2. Modeling of Clocked Quantizers

Quantizers are the key element of over-sampled sigma-delta modula-
tors. For a reliable operation, switched capacitor and switched current
networks are designed in such a way that the network variables of these
circuits reach their steady value of the clock phase before reaching the
end of the clock phase. The quantizer of over-sampled sigma-delta mod-
ulators implemented using switched capacitor or switched current tech-
niques thereby also operates in a clocked manner, i.e. the output of the
quantizer changes only at the clocking instants, and remains unchanged
during the clock phase, as shown in Fig.9.3. This observation suggests
that a clocked quantizer can be modeled effectively using the following
behavioral model:
where and are the input and output of the quantizer at

respectively, and are two constant reference voltages.
One of the main advantages of modeling quantizers using behavioral
models is the elimination of the difficulties encountered in circuit-level
modeling of quantizers.
3. Modeling of Unclocked Quantizers

The analysis of preceding sigma-delta modulators with clocked quan-
tizers is significantly simplified as we only need to worry the output of
the quantizers at clocking instants. For sigma-delta modulators with un-
clocked quantizers, the exact time instants at which the quantizers flip
must be determined with high precision. As pointed out in Chapter 1
that sigma-delta modulators with unclocked quantizers fall into the cat-
egory of circuits with both externally clocked and internally controlled
switches. Unclocked quantizers behave as an internally controlled switch

with the switching variable given by
where and are the voltages at the inverting and non-inverting

input terminals of voltage comparators in phase The switching vari-
able of current-mode quantizers can also be defined in a similar manner.
The time instant at which the quantizer changes its output can be
determined as follows : If and have distinct signs, a
change in the polarity of the output of the quantizer occurs in the time
interval The exact time instant at which the output of
the quantizer varies is obtained by solving numerically using
iteration approaches, such as Newton Raphson. Once is allocated,
the step size is determined and is determined.
Note that this process requires the computation of and
using numerical Laplace inversion. Once is available, the two-step
algorithm introduced in Chapter 5 is employed to compute from
Once is available, simulation proceeds in a sampled-data

manner. As compared with the analysis of sigma-delta modulators with
clocked quantizes, the following additional computation in the analysis
of sigma-delta modulators with unclocked quantizers is required :
i) Evaluation of the switching variable of the quantizer in each integra-

tion step.
ii) If a change in the sign of the switching variable is detected, the exact
switching time is allocated by solving
iii) Computation of and subsequently using the

sampled-data simulation for periodically switched linear circuits.
iv) Computation of the consistent initial condition at time instants im-

mediately after switching using the two-step algorithms presented in
Chapter 5.
4. Modeling of Digital-to-Analog Data Converters

The function of a digital-to-analog converter (DAC) in a single-bit
sigma-delta modulator is to select two distinct reference voltages (or
currents), based on the output of the quantizers. Fig.9.4 shows the
typical configurations of DACs in single-bit sigma-delta modulators. The
single-bit DAC is a switched linear circuit with the controlling signal
be the output of the quantizer of the sigma-delta modulator and two
voltage inputs with constant voltages for voltage-mode DACs or two
current inputs with constant currents for current-mode DACs.
5. Modeling of Other Blocks

When the input to the integrators is small, the integrators can be
treated as a linear element, and can be modeled at the circuit level us-
ing linear elements such as resistors, inductors, capacitors, dependent
and independent sources, and ideal switches. The non-idealities of inte-
grators, such as finite bandwidth, finite input impedance, and non-zero
output impedance of the operational amplifier of the integrators, can
also be modeled conveniently using circuit-level models.
6. Simulation Methods
Sigma-delta modulators are partitioned into (i) a linear block con-
sisting of the integrators, digital-to-analog converters, and other linear
components, and (ii) a nonlinear block composed of the quantizer. The
linear block is modeled at the circuit level and formulated using modified
nodal analysis while the nonlinear part is modeled using the behavioral
model given earlier and incorporated in simulation without using con-
ventional matrix approaches. Such a partition allows us to analyze the
behavior of these circuits in the time domain effectively in the following
way :
The linear part can be formulated and analyzed effectively using the
sampled-data simulation method for periodically switched linear cir-
cuits presented in Chapter 6. There are two inputs to the linear
blocks : the input signal of the sigma-delta modulator and the out-
put of the quantizer. The input signal of the sigma-delta modulators
varies with time continuously. The output of the clocked quantizer
changes with time in a piecewise constant manner and is treated as
a step input for each clock phase. Because the output of the clocked
quantizer is transparent to its input only at switching instants, the
output of the linear block is needed only at the clocking instants
when the quantizer updates its output. For sigma-delta modulators
with an unclocked quantizer, the output of the linear block must be

evaluated in every time step.
The output of the linear block is fed to the quantizer. For sigma-delta
modulators with a clocked quantizer, the output of the quantizer
changes only at the edge of the clock phases and remains unchanged
until the arrival of the edge of the next clock phase. Simulation pro-
ceeds by calculating the output of the linear block after each clocking
instant, updating the state of the quantizer based on the output of
the linear block, and repeating the process for the next clock phase.
For sigma-delta modulators with an unclocked quantizer, the exact
time instant at which the output of the quantizer changes must be
determined and the consistent initial conditions of the modulators
after the quantizer changes its state must be calculated. Simulation
then proceeds from the consistent initial conditions.
Because sampled-data simulation yields the exact time-domain re-

sponse of linear circuits regardless of the step size, also because
clocked quantizers update their output only at the clocking instants,
over-sampled sigma-delta modulators with clocked quantizers can
therefore be analyzed effectively using the sampled-data simulation
of periodically switched linear circuits presented in Chapter 6. The
step size of sampled-data simulation can be set to the width of clock
phases to speed up simulation.
7. Examples
The first example is the single-bit second-order continuous-time over-
sampled sigma-delta modulator shown in Fig.9.5. The comparator is
clocked at 1.024kHz. The operational amplifiers are considered to be
ideal. The input signal is a 1kHz sinusoid of amplitude 2V. The time-
domain response of the modulator is shown in Fig.9.6 and the out-
put spectrum of the modulator obtained from transient-FFT analysis is
shown in Fig.9.7. The noise shaping characteristics of the second-order
sigma-delta modulator are evident.
The second example is a single-bit second-order switched capacitor
over-sampled sigma-delta modulator shown in Fig.9.8 [73, 74]. It is
actually a switched capacitor implementation of the preceding single-

bit second-order continuous-time over-sampled sigma-delta modulator.
Note that the resistors in the preceding continuous-time over-sampled
sigma-delta modulator are implemented using stray-insensitive switched

capacitor technique with the resistance value given by [5]
where is the equivalent resistance of the switched capacitor network,

is the clock frequency and C is the value of the switched capacitor.
Again, the operational amplifiers are considered to be ideal. The spec-
trum of the modulator is shown in Fig.9.9. These results were obtained
by simulating the circuit for 74k clock cycles, discarding the first 10k
data points to remove any transients, and performing a post FFT anal-
ysis on the remaining 64k data points.
The signal-to-noise ratio of the modulator is obtained by performing
the preceding simulation with variable input amplitude. For each in-
put amplitude, the output of the modulator is obtained by performing
transient-FFT analyses and the signal-to-noise ratio (SNR) is calculated.
The result is shown in Fig.9.10. The frequency of the input is 1kHz and
a 4kHz bandwidth was assumed in SNR calculation.
8. Summary
In this chapter, we have first reviewed the characteristics of over-
sampled sigma-delta modulators and the difficulties encountered in anal-
ysis of these special circuits. We have shown that the difficulties encoun-
tered in modeling quantizers at the circuit level can be overcome using
behavior modeling. Other blocks of sigma-delta modulators, however,
can be dealt with conveniently using conventional circuit-level formu-
lation techniques. The simulation methods that incorporate both the
behavioral modeling of the quantizers and the sampled-data simulation
for linear circuits have been detailed. A continuous-time over-sampled
sigma-delta modulators and its switched capacitor counterpart have been
analyzed and comparable results have been obtained.
III
FREQUENCY DOMAIN ANALYSIS

Chapter 10
ADJOINT NETWORK OF PERIODICALLY

SWITCHED LINEAR CIRCUITS
This chapter extends Tellegen’s theorem for linear time-invariant cir-

cuits and that for ideal switched capacitor networks to general period-
ically switched linear circuits and derives the adjoint network of these
circuits using a phasor-domain approach. We show that by using this
approach the derivation of the adjoint network of periodically switched
linear circuits becomes straightforward and bears a strong resemblance
to that of linear time-invariant circuits [75]. We further show that the
transfer functions from multiple inputs to the output of a periodically
switched linear circuit can be obtained efficiently by solving the adjoint
network. More importantly, we reveal that the aliasing transfer func-
tions from inputs at the side band frequencies of wideband inputs, such
as white noise sources, to the output in the base band of a given pe-
riodically switched linear circuit can be obtained efficiently from the
corresponding aliasing transfer function of the adjoint network with the
input at the base band frequency and the output at the corresponding
sideband frequencies.
The chapter is organized as follows: Section 1 introduces Tellegen’s
theorem for periodically switched linear circuits in the phasor domain.
The inter-reciprocity and the adjoint network of periodically switched
linear circuits are developed in Sections 2 and 3, respectively. In Section
4, the transfer function theorem of periodically switched linear circuits
is derived and its usefulness is exploited. Section 5 introduces the fre-
quency reversal theorem of periodically switched linear circuits with a

rigorous proof. Both theorems are assessed using example circuits in
Section 6. The chapter concludes in Section 7.
1. Tellegen’s Theorem
Tellegen’s theorem, introduced by B. Tellegen half a century ago, is a
fundamental law for lumped electrical networks [76, 77, 78]. In the time
domain, it is given by
where and denote the branch voltages and currents of the

circuit, respectively, and B is the total number of branches in the net-
work. Eq.(10.1) also holds for any two circuits N and having the
same incidence matrix
and
where and denote respectively the branch currents and volt-

ages of and are the time variables of N and respectively.
Eqs.(10.2) and (10.3) are called the strong form of Tellegen’s theorem.
It is intuitive to show that following weak form of Tellegen’s theorem
also holds
The weak form of Tellegen’s theorem is of particular usefulness because it

incorporates the branch voltages and currents of two separate networks
N and in a single and closed expression.
Adjoint Network of Periodically Switched Linear Circuits 209
Periodically switched circuits differ from time-invariant networks by

including externally clocked switches. For a given periodically switched
circuit N, we can construct another periodically switched network
of the same topology as that of N irrespective of switching. To find
out the relationship between the phasor of the network variables of N
and that of let the clock frequency of be identical to that of N.
Representing each variable in (10.4) using its phasors
where and are respectively the phasors of

and at the frequency and are
the phasors of and at the frequency respectively.
To extract the relationship between the phasor of the network variables
of N and that of we first eliminate by imposing the constraint
on and then integrate (10.5) with respect to from 0 to
Because
where is Kronecker delta function defined as

we arrive at
Following the similar procedures, one can show that
and
THEOREM 10.1 In the steady state, for a given lumped periodically switched
linear circuit, there exists another lumped periodically switched linear cir-
cuit having the same topology, switching frequency, and reversed time.
The weak and strong forms of Tellegen’s theorem for periodically switched
linear circuits in the phasor domain are given by (10.10), (10.11) and
(10.12), respectively.
Note that :
The phasor of the branch voltages and currents of both N and that
of are evaluated at the same frequency.
The constraint imposed on the time variable of in (10.6) reveals
that the switching clock sequence of is reversed as compared with
that of N, as shown in Fig. 10.1. This time reversal property of the
adjoint network of periodically switched linear circuits is similar to
that of linear time-invariant circuits [75] and ideal switched capacitor
networks [11, 79].
The difference between Tellegen’s theorem for periodically switched

linear circuits and that of linear time-invariant circuits is the sum-
mation operator representing the fundamental characteristics of pe-
riodically switched linear circuits.
2. Inter-reciprocity
Consider a periodically switched linear circuit N. The independent
sources and output branches are separated from the remaining branches,
which are called internal branches. The weak form of Tellegen’s theorem
for periodically switched linear circuits becomes
where and denote the number of input/output ports and that

of internal branches, respectively. To find out the relation between the
inputs and outputs of N, it is desirable to construct in such a way that
the second summation in the above equation, i.e. the term associated
with the internal branches, vanishes. To achieve this, for each internal
element in N, we construct its counterpart in such that the voltages
and currents of the elements satisfy
or equivalently in the time domain
For elements with more than one branch, such as, controlled sources,
the network variables of all the branches of the element should be in-
cluded in (10.14) and (10.15). Elements that satisfy (10.14) or (10.15)
are said to be inter-reciprocal. The circuit constructed in this way is
called the adjoint network of N.
3. Adjoint Network
Adjoint network is a powerful tool for efficient noise and sensitivity
analysis of linear time-invariant circuits [75] and ideal switched capacitor
networks[79]. In this section we make use of Tellegen’s theorem for
periodically switched linear circuits in the phasor domain to derive the
adjoint network of periodically switched linear circuits.
3.1 Ideal Switches

An ideal switch has at most two distinct states : OPEN and CLOSED.
An OPEN switch is characterized by Substituting these con-
ditions into (10.15), we obtain So an OPEN switch in .N is
also an OPEN switch in In the CLOSED state, the switch is char-
acterized by Substituting these conditions into (10.15) yields
A CLOSED switch in N maps to a CLOSED switch in
3.2 Resistors
Representing the voltage and current of a resistor in a periodically
switched linear circuit in the phasor form and submitting them into
Ohm’s law give
Using the property of the orthogonality of exponential series, it can be

shown that the phasors of the voltage and current of the resistor are
related by Substituting this relation into
(10.14) we obtain
where and are the phasors of the voltage and

current of the resistor in the adjoint network, respectively. In order to
have (10.17) hold for arbitrary we set
Eq.(10.18) reveals that the resistor R in N maps to a resistor in with

the same resistance.
3.3 Capacitors and Inductors

Following the similar procedures as those for resistors one can show that
the phasors of the voltage and current of a capacitor in periodically
switched linear circuits is related to each other by
where C is the capacitance. Substituting (10.19) into (10.14)
To validate (10.20) for arbitrary we impose

Eq.(10.21) indicates that the capacitor in N maps to a capacitor of the

same capacitance in the adjoint network.
In a very like manner as that for capacitors, one can show that an
inductor in periodically switched linear circuits is also an inductor of
the same inductance in the adjoint network and is characterized by
3.4 Controlled Sources

The derivation of the adjoint network of controlled sources is illus-
trated using a voltage-controlled voltage source with the voltage of the
controlling branch be denoted by and that of the controlled branch
be denoted by where A is the voltage gain. Note the
current of the controlling branch is zero whereas that of the con-
trolled branch is determined by the circuit in which the controlled
branch resides. Writing (10.14) for the controlled source
To have the above expression hold for arbitrary and

we impose
Clearly the element governed by (10.24) is a current-controlled current

source. Note the magnitude of the current gain is the same as the voltage
gain. The controlling and controlled branches are interchanged. The
adjoint network of other controlled sources can be derived in a similar
manner. The results are the same as those for linear time-invariant
circuits.
3.5 Operational Amplifiers

Operational amplifiers are usually modeled using macro models [5,
80] to minimize the simulation cost and yet to preserve the essential
characteristics of these devices. For linear operational amplifiers, these
macro models are essentially linear time-invariant circuits consisting of
resistors, capacitors, and controlled sources that quantify the essential
characteristics of operational amplifiers, such as bandwidth and output
impedance. The adjoint network of operational amplifiers can therefore
be constructed on an element-by-element basis. Fig.10.2 shows a single-
pole macro model linear operational amplifiers and its adjoint network.
The pole is determined by R and C.
4. Transfer Function Theorem

Having derived the adjoint network of periodically switched linear
circuits, in this section we make use of this theory to develop an efficient
method to compute transfer functions from multiple inputs to one output
of periodically switched linear circuits.
Consider a periodically switched linear circuit N having current
sources and voltage sources. Both current and voltage sources are
single-tones at frequency as shown in Figs.10.4 and 10.5. Let the input

of the adjoint network be a current source applied to
the port corresponding to the output port of N. Further, let the outputs
of be the voltage across and current through the ports corresponding
to the input ports of N. Due to inter-reciprocity, the second summation
in (10.13) vanishes and the expression becomes
Because
and
we obtain
where and Consequently, (10.25)

becomes
Because the inputs of N are single tones at frequency we have
and
Also, since the input of is a single-tone of unity strength at frequency

we obtain
Incorporating these conditions in (10.29) and noting that

and
where and are the transfer functions

from the current input to the current output and the voltage
output of respectively, we arrive at
The output of N can also be obtained using superposition
where and are the transfer functions

from the voltage input and the current input to the voltage
output of N, respectively. Comparing (10.35) and (10.36) we obtain
and
So the amplitude of the transfer functions of N at frequency is the

same as that of the corresponding transfer functions of at the same
frequency. Transfer functions of other input and output configurations
have also been derived and the results are summarized in Table 10.1.
THEOREM 10.2 (TRANSFER FUNCTION THEOREM) The magnitude of

the transfer functions from the multiple input sources to the single output
of a periodically switched linear circuit N at frequency is equal to that
of the transfer functions of the adjoint network from the single input at
the output port of N to the multiple outputs located at the input ports of
N at frequency
With the transfer function theorem, we need to solve the adjoint net-
work at the frequency at which the transfer functions from multiple
inputs to the single output of the original circuit are to be evaluated
only once to yield all the transfer functions of the original circuit.
5. Frequency Reversal Theorem

Consider a single-input single-output periodically switched linear cir-

cuit N shown in Fig. 10.6. Its adjoint network is also shown in the
figure. Write (10.25) in the time domain
where the subscripts and identify the network variables of the output
and input branches, respectively. Because and
Eq.(10.39) becomes
Representing the responses of N and using (3.5), substituting the

inputs of N and into (10.40), and making use of the time reversal
characteristic of we obtain
Because
the output of N at frequency is given by
where is the aliasing transfer function from the volt-

age input at frequency to the voltage output at frequency
Further utilizing the relationship between and
gives
Similarly, since
we have
where denotes the aliasing transfer function from the

current input at frequency to the current output at frequency
Using the time reversal characteristic of we can further simplify
(10.45) as
Summing up (10.47) and (10.44) and making use of (10.41) yield
Consequently
Eq.(10.49) reveals that the magnitude of the aliasing transfer function

of N from the input at frequency to the output at frequency
is equal to that of from the input at frequency to the output at
frequency Similar results were also obtained for circuits with
other input/output configurations and are tabulated in Table 10.2.
THEOREM 10.3 (FREQUENCY REVERSAL THEOREM) The magnitude of

the aliasing transfer functions from multiple inputs at frequency
to the single output at frequency of a periodically switched linear cir-

cuit is equal to that of the aliasing transfer functions of the adjoint net-
work from the single input at frequency to the multiple output at
frequency
The significance of the frequency reversal theorem is that the compu-

tation of the aliasing transfer functions from inputs at frequency
to the output at of N requires solving the circuit at multiple frequen-
cies With the frequency reversal theorem,
these aliasing transfer functions can be obtained by solving the adjoint
network at only.
6. Examples
Two switched capacitor networks are used as examples in this sec-
tion to assess both the transfer function theorem and frequency reversal
theorem.
Consider the bi-phase stray-insensitive switched capacitor integrator
in Fig.10.7 and its adjoint network shown in Fig.10.8 [81]. The value of
the circuit parameters is given in Table 10.3.
All MOSFET switches are modeled as an ideal switch in series with
a noisy resistor. The operational amplifiers are considered to be ideal.
The transfer and aliasing transfer functions of the circuits are solved
using Watsnap, an interactive computer program for general switched
linear circuits [8] and the results are presented in Tables 10.4 and 10.5.
As can be seen that (i) the magnitude of the transfer function from
to of N is the same as that from to of

(ii) The magnitude of the aliasing transfer functions of N match the
corresponding frequency components of the output of
The second example is the second-order band pass filter shown in

Fig.10.9 [81] with the value of the circuit parameters given in Table 10.6.
Its adjoint network is shown in Fig.10.10. The base band frequency con-
sidered is 1000 Hz. The transfer functions and aliasing transfer functions
of the band pass filter and its adjoint network are solved using Watsnap
and the results are presented in Table 10.7. The numerical resolution
is set to 10 digits to capture the difference between the responses of
the two circuits. It is observed that the magnitude of both the transfer
and aliasing transfer functions of the band pass filter match those of its
adjoint network to seven digits. The difference after the seven digits is
mainly attributed to numerical noise.
7. Summary
Tellegen’s theorem for periodically switched linear circuits in the pha-
sor domain has been introduced and a general theory of the adjoint
network of multi-phase periodically switched linear circuits has been de-
veloped. Two new theorems, namely, frequency reversal theorem and

transfer function theorem, have been introduced with rigorous proof.
The application of these theorems allow us to derive transfer functions
and aliasing transfer functions from the multiple input sources to the sin-
gle output at the base band frequency of a given periodically switched

linear circuit by solving its adjoint network at the base band only once.
As to be seen in Chapter 11, the cost of computation in both noise and
sensitivity analyses of periodically switched linear circuits can be reduced
significantly by employing these theorems. Several switched capacitor
networks have been solved to validate these theorems.
Chapter 11
FREQUENCY DOMAIN ANALYSIS OF

LINEAR CIRCUITS
Frequency domain analysis is generally more efficient as compared

with time domain analysis, particularly for linear circuits. In this chap-
ter, we investigate the frequency analysis of periodically switched linear
circuits. In Section 1, an exact frequency analysis method for multi-
phase periodically switched linear circuits is presented. Sensitivity anal-
ysis of these circuits using direct sensitivity analysis, adjoint network,
and sensitivity network is investigated in detail in Section 2. Group
delay of periodically switched linear circuits is studied in Section 3. In
Section 4, noise sources encountered in periodically switched linear cir-
cuits and their characterization in the frequency domain are investigated.
The noise equivalent circuits of semiconductor devices typically encoun-
tered in periodically switched linear circuits are presented. The behavior
of linear periodically time-varying systems in the presence of noise in-
puts is studied in detail and the average power of the response of linear
periodically time-varying systems to stationary noise inputs is derived.
An adjoint network-based noise analysis algorithm is developed and its
effectiveness and efficiency are assessed using practical examples. Statis-
tical analysis of periodically switched linear circuits using the first-order
second-moment is presented in Section 5. The chapter is summarized in
Section 6.
1. Frequency Response
The frequency response of ideal linear switched capacitor networks is
obtained from of algebraic equations obtained from charge
conservation at switching instants [34]. Because switched capacitor net-
works are a subset of general periodically switched circuits, they can
be handled by methods for general periodically switched circuits. For
this reason, frequency analysis of ideal switched capacitor networks will
not be presented here. Interested readers are referred to references at
the end of the book, such as [5], for the details on the analysis of ideal
switched capacitor networks. Unlike ideal switched capacitor networks,
the incomplete charge transfer characteristics of periodically switched
linear circuits, due to the inclusion of resistors, inductors, and non-ideal
operational amplifiers in the configuration of these circuits, requires that
the circuits be depicted by differential equations. The state of the net-
work variables at the end of each clock phase be determined by solving
these differential equations using numerical integration.
It was shown in Chapter 2 that the behavior of a periodically switched
linear circuit in the time domain with input and a total of
K clock phases can be depicted by
for The two Dirac delta functions represent the injection

of the initial conditions of elements with memory at the beginning of the
clock phase accounting for the effect of the initial charge
of capacitors and the initial flux of inductors, and the extraction of the
final conditions of these elements at so that vanishes
outside the clock phase Eq.(11.1) is thus valid for The
frequency domain response of the circuit is obtained by applying Fourier
transform
Frequency Domain Analysis of Periodically Switched Linear Circuits 231
where denotes Fourier transform operator,
for continuous inputs and It is seen that to obtain the

frequency domain response of the circuit, the Fourier transform of the
network variables at the end of each clock phase is needed. To obtain
the Fourier transform of we notice that the sub-circuit
associated with the clock phase is essentially a linear time-invariant
circuit with the initial conditions given by To
analyze this circuit, we reset the time origin to The
input of the circuit becomes and the circuit is
depicted by
and for
Its response at the end of the clock phase is obtained

from the sampled-data simulation with the time step
where
Eq.(11.6) quantifies the time domain behavior of the circuit at the

time instants at which switching occurs. The numerical algorithms for
accurately computing and were given in Appendix 6.B of Chapter
6. Applying Fourier transform to (11.6) and defining
we arrive at
where
and I denotes an identity matrix of appropriate dimensions. Note that

because (11.9) holds for M is frequency
dependent. P, on the other hand, is only related to the input frequency.
Once is available, can be obtained from (11.2) and the
complete response is obtained from
Let us now examine the properties of the preceding frequency analysis

algorithm in detail :
The infinite summation of Dirac impulse function terms in (11.9)

reveals that the frequency response of periodically switched linear
circuits to a single-tone input at frequency contains an infinite
number of frequency components at frequencies
The frequency component at frequency is called the
baseband component and that at frequency is called the
sideband component.
The method is exact. No approximation is made in the derivation

of the method. To obtain the accurate frequency response numeri-
cally, both and must be computed to high precision. They
can be computed using the multi-step numerical Laplace inversion
algorithms given in Chapter 4.
Compared with the analysis of ideal switched capacitor networks, the

following additional computation is required in the frequency analysis
of periodically switched liner circuits
Computation of and
Computation of
LU-decomposition of and subsequent forward and
backward substitutions in solving
Frequency analysis of periodically switched linear circuits is thereby

more costly.
To minimize the cost of computation, it is observed that all entries

of M matrix on the right hand side of (11.9) except the one at the
bottom right corner is independent of frequency. This observation
suggests that it is possible to transfer most of the computation into
a preprocessing stage of the algorithm so that computation per fre-
quency point is minimized. To achieve this, we wish to reduce the
system matrix to the upper block diagonal form by making all blocks
below the main diagonal identically zero. This is accomplished by
the following block elimination technique. Pre-multiply the first row
of M by and add the result to the second row. A zero is created
in the position (2,1), position (2,K) becomes and the prod-
uct is added to the second row of the right hand side vector.
Next, Pre-multiply the second row by and add to the third row.
A zero block is created in position (3,2), the position (3,K) is filled
with and the third row of the right hand side vector be-
comes Continuing this process,
we arrive at
where
Note that both E and are independent of frequency. They can be

pre-computed and stored in a pre-processing step prior to the start of
simulation. Once is available, can be obtained from
In applications where clock frequency is much higher than signal fre-

quency, the variation of network variables within each clock phase
is usually small and can be considered constant approximately. As

a result, for and
The following advantages are gained from
this approximation:
LU-decomposition of and subsequent forward and

backward substitutions are no longer needed. This significantly
lowers simulation cost.
The conventional adjoint network approach, similar to that of
ideal switched capacitor networks [79], can be employed conve-
niently to efficiently compute parameter sensitivity and noise, as
will be seen in the following section of the chapter.
A similar approach was proposed in [82, 83] where circuit equation is

discretized in the time domain using backward difference formulae,
usually backward Euler, with the step size equal to the width of
clock phases or smaller. The resultant discrete network equations
are analyzed in Note that both approaches will give a
large error if the clock frequency is comparable to that of the signal
frequency.
As an example, consider the fifth-order elliptic switched capacitor low

pass filter shown in Fig.11.1. The clock frequency is 32 kHz with two
clock phases of equal width. The circuit parameters are tabulated in
Table 11.1. The frequency response of the low pass is shown in Fig.11.2
with its passband shown in Fig.11.3. 0.28 dB ripple in the passband is
observed.
2. Sensitivity Analysis
The importance of small-signal sensitivity analysis was stated earlier
in Chapter 6 when the time domain sensitivity analysis of periodically
switched linear circuits was investigated. This section deals with sen-
sitivity analysis of periodically switched linear circuits in the frequency
domain. The normalized small-change sensitivity is defined as [5]
where is the frequency response, or other design objectives, such

as the zeros or poles of the transfer function of a given circuit, is usually
a circuit element to which the sensitivity is evaluated. Sensitivity to
parasitic elements can also be defined in a similar manner
In practice, particularly in filter design, the normalized sensitivity of

the magnitude of the response to circuit elements is often needed. This
sensitivity is computed from
where
To determine the quality of a designed circuit, the sensitivities of one

variable with respect to a large number of the elements are usually re-
quired. An issue essential to sensitivity analysis is how to compute these
sensitivities both accurately and efficiently.
2.1 Direct Sensitivity Analysis

It was shown in Chapter 6 that sensitivity to the circuit parameter
that is independent of frequency is obtained from differentiating (11.1)
with respect to
One can see that the network depicted by (11.20) has the same topol-
ogy as that of the original circuit. The only difference is the input given
by the terms in the brackets on the right hand side of (11.20). Fourier
transform of the above equation gives the frequency domain sensitivity
To obtain the Fourier transform of the last two terms on the right
hand side of (11.21), we differentiate (11.9) with respect to
where
and
Once is available, can be solved from (11.21). An no-

table advantage of this approach is that no approximation is made in
the derivation of the method. The method is therefore exact. It yields
accurate results provided that M, P and their derivatives are computed
to high precision. The main drawback is that one analysis of the net-
work only yields the sensitivity to one element. If the sensitivities of the
response with respect to a large number of elements are needed, the cost
of computation becomes excessive.
2.2 Sensitivity Analysis Using Adjoint Network

Sensitivity analysis of ideal switched capacitor networks using adjoint
network offers superior computational efficiency as it yields the sensi-
tivities to all circuit parameters in one network analysis of the original
network and one network analysis of the corresponding adjoint network
[7, 79, 84, 85]. The adjoint network approach for ideal switched capacitor
networks can be applied to sensitivity analysis of periodically switched
linear circuits directly when the clock frequency of these circuits is much
higher than the signal frequency. We detail this in the followings.
It was shown in the preceding section that when the clock frequency
is much higher than the signal frequency, the frequency response
of the circuit can be approximated by The sensitivity of the

response of the circuit N obtained from
where d is a contact vector specifying the nodes at which the output is

taken and the subscript T denotes matrix transpose, is obtained from
By defining the adjoint network of the circuit N as
where is the Fourier transform of the network variable vector of

the adjoint network at switching instants, we have
It is seen that because for different and can be obtained

conveniently, the sensitivity of the response to all circuit elements can
be computed in one analysis of the original circuit for and one
analysis of the adjoint network for It should be noted that
when the clock frequency is comparable to that of the signal frequency,
a large error exists if is approximated from as shown
graphically in Fig.11.4. This limits the applications of this approach.
To investigate Tellegen’s theorem in the presence of perturbations,
let the original circuit N be made of the following types of elements
: resistors, capacitors, inductors, four types of controlled sources, ideal
switches, and independent voltage sources, as shown in Fig.11.5. Further

let the change in the response of N due to the changes in the value of the
elements of the circuit be denoted by Approximating
using Taylor series expansion to the first order yields
where and denote the voltage gain, transconductance, cur-

rent gain, and transimpedance of voltage-controlled voltage sources,
voltage-controlled current sources, current-controlled current sources,
and current-controlled voltage sources, respectively.
It was shown in Chapter 3 that the weak form of the Tellegen’s theo-
rem for periodically switched linear circuits is given by
Also, we showed that the network variable of a periodically time-

varying linear system can be written as
where is the phasor of at frequency The

variation of of N due to a perturbation in element values is therefore
given by
where is the variation of the phasor of at

Writing (11.31) using (11.33) gives
Eq.(11.34) characterizes the relationship between the variation of the

branch voltages and currents of the original circuit N and those of its
adjoint network It is termed the incremental weak form of Tellegen’s
theorem for periodically switched linear circuits in the phasor domain. It
is particularly useful in deriving the sensitivity of periodically switched
linear circuits, as will be seen shortly. Also note that the perturbation of
circuit element value only occurs in N. In what follows we apply (11.34)
to the elements of the periodically switched linear circuit of Fig.11.5 and
derive the sensitivity of the response of the circuit.
Resistors : A linear resistor in N and its counterpart in are char-

acterized by
Let there be a perturbation in the resistor value. Representing

the voltage and current of the resistor using Taylor series expansion
to the first-order and substitute the results into (11.31)
Capacitors : The behavior of a linear capacitor of periodically switched

linear circuits in the phasor domain is characterized by
The first-order approximation of the variation of capacitor current

due to a perturbation gives
Inductors : In a like manner as that for capacitors, one can show that
for linear inductors
Controlled Sources : Consider a voltage-controlled voltage source

with voltage gain in N. Its counterpart in is a current-controlled
current source with controlling and controlled branches interchanged
and gain as shown in Chapter 3. Let the controlling and con-
trolled branches be identified with the subscripts 1 and 2, respectively.
Because
we have in the phasor domain

As a result,
Expressions for other types of dependent sources can be derived in a

similar manner and are left as an exercise to readers.
Ideal Switches : Let there be a perturbation in the element values of

N such that the voltage and current of an ideal switch vary from
and respectively. If
the switch is CLOSED at then, and
Moreover, since its counterpart in is also a CLOSED switch at
then As a result
where and are the voltage and current of the switch in

respectively. Similarly, one can show that (11.43) also holds if the
switch is OPEN. Writing (11.43) in the phasor domain gives
Inputs : Because the input of N is an ideal voltage source and the

corresponding branch in is a short-circuit, we have
or equivalently in the phasor domain
As a result
Output : The output branch of N is an open-circuit, This

results in Because the input of is a single tone
of unity strength at frequency we have
Thus
Substituting the preceding results into (11.34) yields

By comparing (11.50) with (11.30), we obtain the sensitivities of the

response of the circuit with respect to the elements. The results are
given in Table 11.2.
Several comments are made with respect to the preceding develop-
ment:
Once the frequency responses of N and are available, the sensitivity
of the output of N with respect to any element of N can be computed
conveniently by substituting appropriate network variables. Only
two network analyses, one for N and the other for are needed in
computing all sensitivities.
Both the baseband and sideband components of the response of the
original circuit and its adjoint network contribute to sensitivities of
the original circuit in the baseband, as shown in Fig.11.6. This is a
unique characteristic of periodically switched linear circuits.
If there is no switching, i.e. is always zero, Table 11.2 will simplify
to the well-known sensitivity of linear time-invariant circuits [75].
For practical periodically switched linear circuits, the convergence of
sensitivity is ensured by the low-pass characteristics of RC networks
formed by the channel resistance of MOSFET switches and their par-
asitic shunt capacitances at high frequencies because the amplitude of
network variables decreases asymptotically with frequency and even-
tually dies off. The rate of convergence of sensitivity, however, de-
pends upon the frequency characteristics of the network variables
with which sensitivities are associated.
The cost of sensitivity analysis of periodically switched linear circuits

is mainly the computation needed for solving N and at the input
frequency. In Appendix 11.A of this chapter we show that the ad-
joint network can be solved efficiently by utilizing the intrinsic
relationship between N and
2.3 Sensitivity Analysis Using Sensitivity

Network
In the preceding section, the adjoint network based sensitivity analysis
method for periodically switched linear circuits was developed rigorously.
In this section, we show that the same results can also be obtained
in a more illustrative manner using a technique known as sensitivity
network initially developed by T. Trick for linear time-invariant circuits
[75] and R. Davis for ideal switched-capacitor networks [86]. The essence
of the sensitivity network approach is as follows : The fundamental laws
governing a lumped circuit N are KCL and KVL [5]
where A is the incidence matrix, and are the branch current

and voltage vectors, respectively, and is the nodal voltage vector.
Differentiating (11.51) with respect to a circuit element gives
Eqs.(11.52) are the governing equations of a derived network whose

network variables are the derivatives of those of N with respect to
is called the sensitivity network of Clearly, the solution of
gives the sensitivity of N with respect to Note that by changing the
element to we obtain the sensitivity network of Continuing
this process, one can derive all sensitivity networks. Important to note
that these sensitivity networks have the same topology as that of N.
As an illustration, consider a capacitor C. Since to
derive the sensitivity network of the capacitor, we differentiate the above
expression with respect to C
The variables associated with the capacitor in the corresponding sensi-

tivity network are the sensitivity current and sensitivity voltage
The capacitance remains the same. The constitutive equation

of the capacitor in the sensitivity network is the same as that in the
original circuit. An ideal current source is added in parallel with
the capacitor. It is the input of the sensitivity network. The substitu-
tion for the capacitor in the corresponding sensitivity network is given
in Fig.11.7. Similarly, one can derive the substitutions for other basic
elements in corresponding sensitivity networks. The results are shown
in Fig.11.7.
To compute the sensitivity of the response of a periodically switched
linear circuit N with respect to capacitor C, the corresponding sensitiv-
ity network is needed. The input of is a current source connected
in parallel with C of current Because
therefore
This is equivalent to have an infinite number of current sources of value

connected in parallel
with the capacitor, as depicted in Fig.11.8. Each of these current sources
generates an output that also contains an infinite number of frequency
components. The complete output of at frequency is obtained
by summing up the contributions of all the added current sources at
frequency
where is the aliasing transfer functions from the current

source at frequency to the output of at frequency A care-
ful inspection shows that there exist two difficulties in solving (11.56).
First, to obtain has to be solved at frequency
Secondly, if the sensitivities of the response
with respect to M elements are required, then a total of M sensitivity

networks have to be constructed and solved. This amounts to excessive
computation.
To avert these difficulties, we notice that these sensitivity networks are
topologically identical. This observation suggests that only one common
adjoint network needs to be constructed for all sensitivity networks.
In the above capacitor case, the magnitude of is equal
to that of the frequency component of the capacitor voltage
in the adjoint network provided that the input of is of unity
strength. Because the adjoint network of is the same as that of N,
we have
where is the frequency component of the voltage

of the capacitor in Substituting (11.57) into (11.56) gives
Note (11.58) is identical to the result given in Table 11.2. The above
analysis reveals that the sensitivities of periodically switched linear cir-
cuits developed using the adjoint network approach can also be derived
using the sensitivity network technique. The differences between the
sensitivity networks of linear time-invariant and periodically switched
linear circuits also become apparent. For each element of a linear time-
invariant circuit, there is only one corresponding sensitivity network.
However, for each element of a periodically switched linear circuit, there
are an infinite number of sensitivity networks.
2.4 Numerical Examples

In this section, two periodically switched linear circuits are used to
demonstrate the effectiveness of adjoint network based sensitivity analy-
sis method. The first example is the stray-insensitive switched capacitor
integrator shown in Fig.11.9 with circuit parameters given in Table 11.4
The operational amplifier is modeled as a single-pole device with unity
gain frequency 700 kHz. Its equivalent circuit and the adjoint network
are shown in Fig.10.2. The sensitivity of the output with respect to at
1 kHz was computed using the adjoint network approach and the results
are plotted in Fig.11.10 for the real part and Fig.11.11 for the imaginary
part. The normalized sensitivity of the magnitude of the response to
is shown in Fig.11.12.
For the purpose of comparison, the same sensitivity was computed
using Watsnap, a commercial CAD tool for periodically switched linear
circuits [8] that calculates sensitivity using the direct sensitivity analysis
approach presented earlier in this chapter. The result is :
To assist in analysis, the relative difference defined as
where is the number of sidebands considered in adjoint network based

sensitivity analysis is employed to quantify the rate of convergence of
sensitivity. In this example, and

The rapid convergence of the sensitivity is due to the fast decaying profile
of the voltages of in both the integrator and those of its adjoint
network, as shown in Fig.11.13.
The second example is the switched capacitor band-pass filter shown
in Fig.11.14 with the value of circuit parameters given in Table 11.5. The
sensitivity of the response with respect to at 1 kHz was computed
using the proposed method and the results are plotted in Fig.11.15 for
the real part and Fig.11.16 for the imaginary part. It is seen that both
the real and imaginary parts of the sensitivity converge with the increase
in the number of sidebands. The rate of convergence is clearly slower
as compared with the previous example. The normalized sensitivity of
the magnitude of the response to is shown in Fig.11.17. The relative
difference versus the number of sidebands in sensitivity analysis
is plotted in Fig. 11.18. It is seen that the relative difference decreases
with an increase in the number of sidebands monotonically. The voltage
of of the band-pass filter and that of its adjoint network are shown in
Fig.11.19 (100 sidebands). The voltage across in the adjoint network

is shifted down by 100 dB in order to fit the two voltages in the same
figure. As observed, both voltages decrease slowly with frequency. As a
result, more sidebands are needed to yield a converged value.
3. Group Delay Analysis

Group delay an essential design parameter for precision switched
capacitor and switched current filters, characterizes the dependence of
the phase of the response of a given circuit on the frequency of
the input of the filters
Making use of we obtain

Because the response of periodically switched linear circuits to the

input contains an infinite number of frequency components
at frequencies the derivative of the response
to frequency can be obtained by differentiating (11.2) with respect to
rather than leading to the group delay network depicted
by
The final conditions of the group delay network are obtained from
with obtained from
Because the state transition matrix is independent of the input, we

have
can be computed in a similar manner as given earlier. The

group delay network can be solved using the same approach as that for
sensitivity networks.
As an example, consider the fifth-order switched capacitor low pass
filter shown in Fig.11.20. The parameters of the circuit are tabulated in
Table 3. The group delay is obtained using the preceding method and
is shown in Fig.11.21. It is seen that the group delay has a peak of 660
ms at 3.55 kHz approximately.
4. Noise Analysis
The most commonly encountered types of noise in silicon integrated
circuits are thermal noise, shot noise, and flicker noise [2]. These noise
sources are inherent to silicon devices. In this section, the power spec-
tral density of the output of linear periodically time-varying systems to
random inputs is derived using the theorems of linear periodically time-
varying systems presented in Chapter 3. Such an analysis provides much
needed theoretical foundation for noise analysis of periodically switched

linear circuits. Noise sources encountered in integrated circuits and their
power spectral density are investigated in this section. Noise analysis of
periodically switched liner circuits using adjoint network is presented
and the output noise power of several no-ideal switched capacitor net-
works is analyzed using the method and the results are compared with
both measurement results and the results from other computer-aided
design tools.
4.1 Noise Characterization

Noise is a random signal with zero mean. The behavior of a noise
signal in the time domain is characterized by its autocorrelation func-
tion and in the frequency domain by its power spectral density. The
autocorrelation function of a noise signal denoted by is

the joint moment of and [87]
where the asterisk denotes complex conjugation, and denote two dis-
tinct time instants. quantifies the connection between
and statistically. If the
is the mean-square value or the average power of The autocovari-

ance of denoted by is defined as the joint moment of
and and it relates to the autocorrela-
tion function by
and are said to be uncorrelated if A stochastic

process is said to be stationary in the strict sense if all of its statistical
properties are time-invariant. It is stationary in the wide sense if its
mean is constant and its autocorrelation function satisfies
where Note that the wide-sense stationarity involves only

the first and second-order moments. Because it is generally difficult
to evaluate the high-order moments of a given stochastic process, the
wide-sense stationarity is widely used in practice. If both the mean
and autocorrelation function of a wide-sense stationary noise signal are
periodic in time, the noise signal is said to be cyclo-stationary in the
wide sense.
In the frequency domain, the power spectral density of a noise signal
denoted by depicts the spectrum of the power of the noise
signal. It is defined as the Fourier transform of the autocorrelation
function of
Eq.(11.71) is also known as Wiener-Khintchine theorem [56]. If

where A is a constant, then Processes of such
characteristics are said to be white. For a wide-sense process if
i.e. then
Eq.(11.72) reveals that the area under specifies the mean-

square value of
The power spectral density of noise sources encountered in integrated
devices has been investigated extensively and is readily computable.
Noise analysis is thereby a task of how to compute the output noise

power of a given circuit containing a large number of noise sources effi-
ciently and accurately.
In was shown in Chapter 3 that the frequency response of a linear
periodically time-varying system is given by
If the input of a linear periodically time-varying system is a

stochastic process, then the response of the system is also a stochas-
tic process. The autocorrelation function of the response is given by [87]
The two-dimensional power spectral density of denoted by

is defined as the two-dimensional Fourier transform of the autocorrela-
tion function of [87]
where and are the Fourier transform of and

respectively. Substituting (11.75) into (11.74) gives
Eq.(11.76) is further simplified to

Thus
Because
and
therefore
Eq.(11.81) is valid for general linear periodically time-varying systems.

If is wide-sense stationary, then Conse-
quently
Let then
Consequently
Substituting (11.84) into (11.81) yields
The time-varying power spectral density of the response is ob-

tained by taking the inverse transform of the two-dimensional power
spectral density with respect to the frequency variable cor-
responding to the excitation time
Therefore
Define
we arrive at
As can be seen that is periodic in with period Fig.11.22

illustrates the sampling of a stationary random input using a sample-
and-hold mechanism.
The average power spectral density of the response over a period, de-
noted by is computed from
Because
we obtain
Eq.(11.92) characterizes the average power spectral density of the re-

sponse of liner periodically time-varying systems with stationary inputs.
It can be used to compute the average output noise power of periodically
switched linear circuits. A few comments are made :
If the power spectrum of the input noise is broad-band, Nyquist the-

orem is violated. As a result, the sideband components of the input
noise are folded back to the base band. A pictorial illustration is given
in Fig.11.23 where the band width of the input noise is assumed to
be i.e.
The band width of the circuit is assumed to be infinite and its gain is
unity. Due to aliasing effect, the output noise power is 5 times that
of the input noise, i.e.
The contribution of the sideband components of the input noise

source clearly dominates the total output noise power.
For practical circuits with white noise sources, the total output noise
is computed from
where the maximum number of sidebands considered, N, is deter-

mined by the equivalent noise bandwidth of the circuits.
If there is no switching in the circuits, i.e. Eq.(11.92) simplifies

to the familiar expression for linear time-invariant circuits.
It is evident that even though in this case the input noise is broad-
band, the side band components of the input noise, however, do not
affect the output noise power in the base band.
If there are a total of M uncorrelated noise sources in a periodically
switched linear circuit, the output noise power is obtained from
where N is the maximum number of sidebands considered. It is seen

that the computational cost in noise analysis of periodically switched
linear circuits arises from (i) a large number of noise sources and (ii)
the aliasing effect. Methods that compute the output noise power di-
rectly from (11.97) is often referred to as the brute-force method be-
cause in this approach not only the contribution of each noise source
is computed separately, the contribution of every sideband compo-
nent of the same noise source is also calculated individually.
4.2 Noise Sources

Thermal noise : Thermal noise, also known as Johnson noise, in recog-
nition of the first observation of the phenomenon by J. B. Johnson
[88], is generated by the random thermal agitation of mobile carri-
ers. It is due to the random departure and return of mobile charges
in thermal equilibrium. The power of thermal noise is directly pro-
portional to temperature. The band width of thermal noise at room
temperature is around 6000 GHz and time samples separated by 0.17
ps are considered to be uncorrelated [89]. In almost all cases, thermal
noise is treated as a stationary process. The distribution of thermal
noise is Gaussian. The power spectral density of the thermal noise
generated by a resistor is given by
where R is the resistance of the resistor, is

Boltzmann constant, and T is the absolute temperature in degrees
Kelvin. Eq.(11.98) was first derived by Nyquist [90] from thermo-
dynamics and the exchange of energy between resistive elements in
thermal equilibrium and is known as Nyquist law.
Shot noise : Shot noise of semiconductor devices is caused by the ran-

dom combination of electron-hole pairs and the random diffusion of
minority carriers across depletion region [91]. This phenomenon is
depicted by a stochastic process representing the sum of a large
number of independent events occurring at random time instants with
an average rate
where is a pulse shape function and is the time at which the

pulse occurs. Note is causal. The distribution of is Poisson.
The power spectral density of is given by Curson’s theorem
[92, 93]
where is the Fourier transform of The band width of shot

noise is inversely proportional to the transit time required by the
carriers to cross the depletion regions, and is in high gigahertz ranges
[89]. Shot noise is often treated as a stationary white process. In the
extreme case where is approximated by Dirac impulse function
because we have the following Schottky’s theorem
for the power spectral density of the shot noise of pn-junctions [56]
where is the average forward biasing current of the pn-junction

and is the charge of an electron. It should be noted
that the above result is only valid for where is the
time for mobile carriers to cross the potential barriers.
Flicker noise : Flicker noise, also known as noise, exists in both

active devices and passive resistors. The mechanism of noise
in semiconductor devices has been studied extensively and tends to
converge to two basic noise theories :
Carrier mobility fluctuation model of flicker noise [94] - Flicker

noise is generated by the scattering of mobile carriers due to the
collision with the crystal lattice of silicon and impurities.
Carrier density fluctuation model of flicker noise [95] - Flicker
noise is caused by the trapping and de-trapping of the mobile
carriers in the traps located at the surface of gate oxide.
For MOSFET transistors, it was found that the mobility fluctuation

model only holds when the devices are operated in the triode region
where the inverse layer can be approximated by a homogeneous re-
sistor. The density fluctuation theory, on the other hand, predicts
noise accurately in all regions of MOSFET transistors.
Flicker noise is always associated with a direct current and is often
modeled as a stationary process with power spectral density given by
[2]
where I is the average current, is a process and temperature

dependent constant, and are constants whose values are in the
ranges of and and is frequency. For most
electronic devices, flicker noise surpasses thermal and shot noise at
low frequencies. Extensive experiments show that there is no change
in the shape of the power spectral density of flicker noise even at
extremely low frequencies [96]. The upper frequency limit of flicker
noise is difficult to detect as it is usually masked by the floor of ther-
mal noise. The corner frequency, defined as the frequency at which
the power spectral density of thermal/shot noise and that of flicker
noise intercept, is often used as the upper bound of the frequency of
flicker noise for MOSFETs and is in the range of several MHz.
4.3 Noise Equivalent Circuits

The equivalent circuits of integrated devices with noise sources in-
cluded are used in noise analysis of electronic circuits.
Resistors : Physical resistors such as diffusion resistors and polysilicon

resistors, generate thermal noise. At low frequencies, a resistor can be
modeled as a hypothetical noise-free resistor in series with a random
voltage generator or a noise-free conductor in parallel with a random
current generator, as shown in Fig.11.24. At high frequencies, the
parasitic capacitances associated with the resistors must also be taken
into account.
Bipolar Junction Transistors : Bipolar junction transistors (BJTs)

are widely used for high-frequency and high-speed applications due to
their large intrinsic There are four main noise sources associated
with a BJT : (1) thermal noise generated by the base resistance, (2)
shot noise in the base current, (3) flicker noise in the base current, and
(4) shot noise in the collector current. Flicker noise of BJTs arises
mainly due to the generation/recombination process in the emitter-
base depletion region and the trap/de-trap of carriers by the oxide
located above the emitter-base junction. The former usually predom-
inates over the later [97]. As compared with MOSFET transistors,
noise of BJTs is much smaller and manifests itself in frequency
regions several decades lower [98]. The base resistance consists of the
intrinsic base resistance and extrinsic base resistance. The intrinsic
base resistance is usually larger than the extrinsic [97]. However, due
to the effect of current crowding [2], the intrinsic resistance and the
associated thermal noise can be reduced by a large collector current.
The extrinsic base resistance is made up of the bulk and contact re-
sistances. It can be reduced by increasing the number of contacts in
the base and reducing the lateral distance between the emitter and
base contacts. The thermal noise generated by other parasitic resis-
tances of bipolar junction transistors, such as emitter and collector
bulk resistances, also constitute the overall noise of the device. How-
ever, because the emitter is heavily doped, the associated thermal
noise is small [99]. The thermal noise originating from the collector
resistance is often surpassed by the noise of collector loads. The noise
equivalent circuit of BJTs in the forward active region is given in Fig.
11.25. When a BJT is operated in an ON/OFF mode, its equivalent
circuit can also be obtained by including the above identified noise
sources in the large-signal equivalent circuit of BJTs.
MOSFET Transistors : MOSFET transistors are building elements

of switched capacitor and switched current circuits. Recent advance
in CMOS technology has also made CMOS a viable technology choice
for high-speed and RF applications. Noise generated by the intrinsic
part of a MOSFET transistor consists of (1) shot noise in the gate
leakage current, (2) thermal noise due to the random thermal motion
of mobile carriers in the inversion layer and (3) flicker noise due to
channel charge density fluctuation caused by the traps at the oxide-
silicon interface [100]. The shot noise of the gate leakage current is
usually negligible. To ensure a stable operation, MOSFET transistors
are usually biased in strong inversion where is the

surface potential and is the Fermi potential [40]. The power of
the flicker noise originated in the channel is given by [98]
where is the drain-source quiescent current. W and L are the

width and length of the channel, respectively, is the gate transcon-
ductance, is the gate capacitance per unit area, and is the sur-
face mobility of charge carriers in the channel. MOSFET transistors
exhibit the highest noise among all active integrated devices [98].
As compared with BJTs, the corner frequency of the flicker noise of
MOSFET transistors could extend to mega Hertz ranges [2].
The thermal noise generated by a MOSFET transistor in saturation
is mainly due to the fluctuation in the drift current in the channel
[40]. The fluctuation in the diffusion current is negligible as the drift
current predominates over the diffusion current when the device is in
the strong inversion. The thermal noise of the drift current is given
by [101]
where and are the gate transconductance and substrate transcon-

ductance, respectively.
Eq.(l 1.104) is valid only in the saturation region. It gives erroneous
results if the device is in the triode region because in this region
and zero thermal noise is predicted. In [102], the
channel conductance, is added to (11.104) to represent the thermal
noise generated by the device in ohmic region.
where
is the pinch-off voltage. Note varies with

linearly from 1 at (where to at
(where is small). The validity of (11.105) was questioned in
[103] because it differs from the theoretical results given in [104, 40].
Moreover, the noise power predicated by (11.105) deviates notably
from SPICE simulation when different levels of MOSFET models are
used. It was shown in [40] that under the quasi-static condition, the
power of the thermal noise originating from the drift current in the
channel of a strongly inverted MOSFET transistor is given by [40]
where
Here
and is the channel conductance when When the

first-order approximation [105] is used, it is obtained from
It should be noted that (11.107) is only valid for long channel devices.
In [106], the modulation of the channel length and the degradation
of surface mobility due to the high lateral field were also included in
modeling the noise of MOSFET transistors and more complex results
were obtained.
Switches in periodically switched linear circuits are realized using
NMOS transistors operated in the triode region to minimize and
the sub-threshold regions. CMOS pass-transistor gates with comple-
mentary clocks are also used extensively to maximize signal dynamic
range and to minimize the ON-resistance [107, 81], however, at the
expense of complex layout. In the triode region, because is small,
the channel can be approximated by a homogeneous conductor with
conductance given by
The thermal noise generated by the channel is computed in the same

way as that of resistors. When the transistor is in the sub-threshold
region, we follow the same treatment as that in CSIM [105] and BSIM
[108], and set Consequently, the noise is zero. A low-
frequency noise equivalent circuit of MOSFET switches is given in
Fig.11.26. This model has been used widely due to its simplicity
[109, 57, 110, 111].
Noise generated by the extrinsic part of the device includes the ther-
mal noise originating from the source and drain bulk resistances, and
polysilicon gate series resistance. Among them, the thermal noise
of the polysilicon gate series resistance predominates. To analyze
the noise behavior of MOSFET transistors at high frequencies, both

the intrinsic and parasitic capacitances must be included. A noise
equivalent circuit of MOSFET transistors in saturation is given in
Fig.11.27. At very high frequencies, the thermal noise generated by
the substrate resistance should also be taken into consideration as it
contributes nearly 20% of the total noise of MOS transistors [112].
It is also worth noting that the so-called gate-current fluctuation
[56, 100, 113] is due to the thermal noise originating in the channel
and coupled via the gate-channel capacitance at high frequencies. It
should not be considered as an independent nor a correlated noise
source.
Operational Amplifiers : Noise generated by an operational ampli-

fier is mainly due to the noise generated in the differential input
stage. The contribution of the noise generated in the following stages
is usually negligible. To model the noise of the differential input stage
in either open- or short-circuited cases, two pairs of noise-current
generator and noise-voltage generator are needed at each input ter-
minal of the operational amplifier and the operational amplifier is
thereby treated as a hypothetical noise-free device, as shown in Fig.
11.28(a) in which and are current-noise generators, and
are voltage-noise generators [114]. Because and represent
common-mode signals, they produce virtually no differential output
if the common-mode rejection ratio of the operational amplifier is
high. Also, for MOSFET input stages, is negligible. They can be
removed from the equivalent circuit without introducing large errors
[2]. Also, because the two voltage-noise generators are in series with
the input, they can be combined into a single voltage-noise generator,

i.e. provided that the correlation is small. This leads
to a simplified noise equivalent circuit of the operational amplifier
shown in Fig. 11.28(b) [115, 116, 117]. If the operational amplifier is
realized using BJTs, then consists of the thermal noise of the base
resistances, shot noise in base current and the input-referred noise
originating in the collector currents of appropriate transistors in the
differential stage. If the input stage is realized using MOSFET tran-
sistors, then is made of the input-referred thermal and flicker noise
originating in the inversion layer of the appropriate MOS transistors
in the stage. It should be noted that when the operational amplifier
is operated at low frequencies, is independent of frequency. How-
ever, at high frequencies, since the gain of the differential input stage
varies with frequency, the input-referred noise source also changes
with frequency. Consequently, is frequency-dependent.
4.4 The Algorithm

The equivalent noise band width of periodically switched linear cir-
cuits usually exceeds the clock frequency by orders of magnitude. The
under-sampling of the wide band noise results in a strong aliasing effect.
The noise power folded over from the side band components of the noise
sources dominates the output noise power. In the preceding section, we
have shown that the response of periodically switched linear circuits with
stationary inputs is cyclo-stationary. Its average power spectral density

is time-independent and is computed from
where is the power spectral density of the noise at the

frequency is the aliasing transfer function from
the noise source at the frequency to the output at the
frequency M is the number of noise sources, and N is the maximum
number of sidebands considered. Both the transfer and aliasing transfer
functions from the noise sources to the output are needed in computing
the output noise power.
It was shown in Chapter 10 that the transfer functions and aliasing
transfer functions of periodically switched linear circuits can be com-
puted efficiently by using the adjoint network. For a given periodically
switched linear circuit N,
i) Replace all noisy elements in the circuit with their corresponding

equivalent circuits.
ii) Define a set of constant vectors to specify the

nodes to which these noise sources are connected.
iii) Further, the output of N is specified by a constant vector d, i.e.
where is the response of N.
iv) The adjoint network of N is constructed and the system matrices

of are obtained as per details given in Appendix 11.A.
v) Using transfer function theorem of this chapter, the transfer function

from the noise source to the output of N at denoted by
is obtained from
where is the response of at the frequency with an input of

unity amplitude at the frequency The location of the input of
is specified by d.
vi) Further from frequency reversal theorem, the aliasing transfer func-
tion from the noise source at the frequency to the output
at the frequency denoted by is obtained from
where is the order frequency component of the re-

sponse of
vii) The transfer and aliasing transfer functions from other noise sources
to the same output of N can be obtained by substituting appropriate
vectors into (11.114) and (11.115), respectively. Since all noise
sources are assumed to be uncorrelated, the total output noise power
of N is obtained by summing up the contributions of all noise sources.
Eq.(11.116) reveals that for a given periodically switched linear cir-

cuit, once the location and type of the noise sources are known, the
power spectral density of the output of the circuit at a given base band
frequency can be computed efficiently by solving the adjoint network.
4.5 Numerical Examples

The first example is the the switched capacitor low pass filter shown in
Fig.11.29 with the value of the circuit elements given in Table 11.7. Only
the thermal noise of MOSFET switches is considered. Five different
input noise band widths, 250 kHz, 500 kHz, 1 MHz, 5 MHz, and 10
MHz were considered in analysis. This corresponds to the foldover of
50, 100, 200, 1000, and 2000 sidebands. The output noise power was
calculated using the method presented in this section and the results
are plotted in Fig.11.30, together with the measurement data extracted
from [109]. It is seen that the output noise power increases with the
increase in the number of sidebands folded over. It eventually converges
to a finite power irrespective of any further increase in the number of
sidebands. This observation reveals the existence of a finite equivalent
noise bandwidth of this circuit. The finite noise bandwidth of the circuit
is due to the low-pass mechanism formed by the channel resistance of
the MOSFET switches and the shunt capacitances. It is the finite noise
bandwidth of the circuit that results in a finite output noise power. It is
also seen that simulation results agree very well with the measurements.
The second example investigated is a switched capacitor integrator
with four non-overlapping phases of equal width [57]. The schematic
of the integrator and its noise equivalent circuit are shown in Fig.11.31
with the value of its elements given in Table 11.8. The thermal and shot
noise of the operational amplifier are represented by an equivalent noise-
voltage generator The flicker noise of the operational
amplifier and that of the MOSFET switches were not considered in the
analysis. The model of the noise-free operational amplifier is the same
as that given in Chapter 10. The output noise power was calculated
with input noise band width of 250 kHz, 500 kHz, 1 MHz, 5 MHz,
and 10 MHz. This corresponds to the foldover of 25, 50, 100, 500,
and 1000 sidebands. The results are plotted in Fig.11.32, together with
the measurement data extracted from [57]. It is seen that with the
increase in the number of sidebands folded over, the total output noise
power increases monotonically. It eventually converges to a finite power
irrespective of any further increase in the number of sidebands. The
simulation results are in a very good agreement with the measurement
data.
The efficiency of the adjoint network algorithm is demonstrated by
comparing the CPU time of the algorithm with that of the brute-force
method. Fig.11.33 shows the CPU time of the proposed algorithm on
computing the output noise power of the switched capacitor integrator
with (a) only the noise of M1 considered and (b) all noise sources, i.e.
the noise of and operational amplifier, considered. As can be
seen that the amount of time spent in both cases is nearly the same. This
observation validates our earlier statements on the advantages of using
the transfer function theorem in noise analysis. Also observed that the
cost of computation is linearly proportional to the number of sidebands
folded over.
To investigate the efficiency gained from using the frequency reversal

theorem over the brute-force method, the noise source of and that
of the operational amplifier are turned off, and only the noise source
of is activated. The output noise power of the integrator was com-
puted using both methods. Fig.11.34 gives the ratio of the CPU time
of the adjoint network method to that of the brute-force with various
step sizes used in computing and It is seen that the speedup
obtained using the frequency reversal theorem is significant. Also, the
speedup is step size dependent. It increases with the decrease in the step
size. These results are expected since the lack of efficiency of the brute-
force method is due to the repetitive calculation of at both the base
band and sideband frequencies. Also, the accuracy of the computation
of is inversely proportional to the step size whereas the computa-
tional cost is directly proportional to the step size. The deficiencies of
the brute-force method are eliminated once the frequency reversal the-
orem is employed. For every base band frequency, the adjoint network
is solved only once at the frequency. In other words, one calculation
of of the adjoint network per base band frequency is required. The
corresponding high-order frequency components are obtained using LU-
factorization and forward/backward substitutions. The computation re-

quired for LU-factorization is much less than that of a significant
speedup is therefore achieved. For instance, at step size and with
100 sidebands considered, the adjoint network-based method is nearly
15 times faster than the brute-force method when only one noise source
is considered.
Also observed is that with the increase in the number of sidebands to
be folded over to the baseband, the speed up plot in Fig.11.34 becomes
flat. This is because the cost of LU-decomposition of start
to dominate the total cost of computation.
The third example is switched capacitor band pass filter shown in

Fig.11.14 [118] with the value of the circuit parameters given in Table
11.5 except the unit gain frequency of the operational amplifier. The
unit-gain frequency of the operational amplifier is set to be 10 GHz
such that the noise band width is mainly determined by the channel
resistance of the MOSFET switches and shunt capacitances. The input-
referred white noise of the operational amplifiers is The
flicker noise of the operational amplifiers is at 10 Hz. Note

that we have used the same parameters as those in [118] for the purpose
of direct comparison. There are sixteen white noise sources associated
with MOSFET switches, two white noise sources and two flicker noise
sources related to the operational amplifiers. The output noise power
of the band-pass filter is computed and the results are plotted in Fig.
11.36, together with the simulation results extracted from [118]. The
number of sidebands folded over are 3000, 10000, 30000, 50000, 60000,
and 70000, which correspond to noise band width of 0.384 GHz, 1.28
GHz, 3.84 GHz, 6.4 GHz, 7.68 GHz, and 8.96 GHz, respectively. The
large equivalent noise band width is mainly due to the small channel
resistance of MOSFET switches, small shunt capacitances, and large
unit-gain frequency of the operational amplifiers used in the simulation.
It is seen that our results agree well with those from [118].
The effect of flicker noise is investigated by computing the output
noise power due to the flicker noise sources of the operational amplifiers
only. The output noise power in the base band with 0, 2 and 5 sidebands
folded over, are computed and the results are shown in Fig.11.37. It is
seen that the effect of the flicker noise dominates at frequencies less
than 500 Hz. The output noise power due to the flicker noise sources
saturates when 5 sidebands are considered, indicating that only a few
sidebands are needed. For the purpose of comparison, the output noise
power due to the thermal noise sources with no fold-over is also plotted
in Fig.11.37. It is seen that the contribution of the flicker noise sources
is negligible as compared with that of the thermal noise sources at high
frequencies. This is the reason why flicker noise is generally neglected in
noise analysis of switched analog circuits.
5. Statistical Analysis
Similar to the first-order second-moment method for statistical analy-
sis of periodically switched linear circuits in the time domain, the mean
and variance of these circuits in frequency domain can also be analyzed
using this approach and the results are given by (11.117) for the mean
and (11.118) for the variance.
Incorporating these results into frequency analysis of periodically switched

linear circuits with the derivatives computed using the method given in
the sensitivity analysis, we are able to compute the mean and variance
of these circuit in the frequency domain [119].
Consider the switched capacitor band pass filter shown in Fig.11.14.
No correlation is assumed among the circuit elements. Further, a uni-
form coefficient of variance, denoted by is used for all circuit parame-
ters. The dependence of the response of the circuit at on the
coefficient of variance of the circuit parameters is plotted in Fig.11.38.
Monte Carlo analysis is also carried out. Specifically, the value of circuit
parameter is generated from
where N(0,1) is a normally distributed random variable with zero mean

and unity standard deviation. The value of each circuit parameter is
generated in this way and the circuit is solved for each set of random
circuit parameters. The number of samples used in Monte Carlo analysis
is 500. The results of Monte Carlo analysis are also plotted in Fig.11.38.
It is seen that the results from the first-order second-moment compare
well with those of Monte Carlo analysis when the coefficient of variance
of the circuit parameters is small. The variance of the response for vari-
ous coefficient of variance of the circuit elements is plotted in Fig.11.39,
together with those of Monte Carlo analysis with 500 samples. Again,
they agree well when the coefficient of variance of the elements is low.
Deviation, however, becomes noticeable once is large. This obser-
vation agrees well with our earlier statements that the error of FOSM
method grows if the coefficient of variance of circuit parameters is large.

Also observed is that of the response exhibits a nonlinear characteris-
tic when of the circuit parameters is large, revealing the limitations
of FOSM method.
6. Summary
Frequency analysis of periodically switched linear circuits has been
presented in this chapter. We have shown that the exact response of
multi-phase periodically switched linear circuits can be obtained by us-
ing a time domain analysis for the value of network variables at the
switching instants and a frequency domain analysis of the circuit equa-
tion depicting the circuits. The cost of computation is much higher as
compared with that of ideal switched capacitor networks. The method
handles both ideal switched capacitor networks and general periodically
switched linear circuits consisting of all linear elements and switches.
In sensitivity analysis of these circuits, direct sensitivity analysis, ad-
joint network approach, and sensitivity network approach have been
presented and their effectiveness has been compared using example cir-
cuits. We have shown that direct sensitivity analysis approach yields the
exact sensitivity of periodically switched linear circuits but at the cost of
computation because each network analysis only yields sensitivity to one
circuit parameter. To compute the sensitivity of the response to multiple
circuit elements efficiently, adjoint network approach is preferred. We
have shown that the sensitivity of the response of periodically switched
linear circuits at a frequency in the base band consists of the contribu-
tion of the network variables both at the frequency in the base band
and those at corresponding sidebands. Similar approaches have been
extended to group delay analysis of periodically switched linear circuits.
To analyze the output noise power of periodically switched linear cir-
cuits, noise sources encountered in periodically switched linear circuits
and their characterization in the frequency domain have been investi-
gated in detail. Noise equivalent circuits of semiconductor devices typi-
cally encountered in periodically switched linear circuits have also been
APPENDIX 11.A 299
derived. The behavior of linear periodically time-varying systems in the

presence of noise inputs has been studied using autocorrelation function
and the network functions derived in Chapter 3. We have shown that al-
though the power spectral density of the output of periodically switched
linear circuits with stationary noise sources is periodically time-varying,
its average value is time-invariant and is determined from the aliasing
transfer functions from the noise sources to the output of the circuits.
An adjoint network-based noise analysis algorithm has been developed.
The effectiveness and efficiency of the method have been assessed using
practical examples with measurement results.
Finally, statistical analysis of periodically switched linear circuits in
the frequency domain using the first-order second-moment has been de-
veloped. We have shown that the method is computationally efficient
and gives accurate results when the coefficient of variance of circuit ele-
ments is low.
APPENDIX 11.A: Solution of Adjoint Network of

Periodically Switched Linear Circuits
In this appendix, we show that the adjoint network of a given periodically switched
linear circuit can be solved efficiently by utilizing the intrinsic relationship of these
two circuits.
When taking into account the time reversal characteristic of the adjoint network,
it can be shown that and of N relate to those of by
where and are the conductance and capacitance matrices of

The superscript T denotes matrix transpose. Since
where A is a non-singular square matrix, also because we
have
Therefore, the LU-factorization of can be obtained directly from that of

without additional computation. Also, because
The state transition matrix of can also be obtained from that of N without nu-
merical integration.
The zero-state response is input-dependent. It is the solution of the circuit at
when the input is applied at and the initial condition is
zero. Using numerical Laplace inversion with {N, M} = {8,10} [120, 121], it can be
shown that is computed from
where
Because
we obtain
Consequently
where is a constant vector specifying the nodes to which the input of is con-
nected. It is obtained from where is a constant vector specifying the
output location of N. The above analysis shows that the zero-state response of
can be obtained efficiently from that of N without numerical integration.
In summary, the adjoint network of N can be solved with little extra computa-
tion given that the solution of N is available. The intrinsic relationship between N
and is summarized in Table 11.A.1
APPENDIX 11.A 301
Chapter 12
FREQUENCY DOMAIN ANALYSIS OF

NONLINEAR CIRCUITS
The steady-state response of a nonlinear time-invariant circuit to a

sinusoidal input contains both the frequency of the sinusoidal input and
its harmonics. When two sinusoids of different frequencies are applied
to the circuit simultaneously, intermodulation frequency components are
generated. It was shown in Chapter 11 that due to the periodic switch-
ing, the response of periodically switched linear circuits to a single-tone
input at contains frequency components at both the baseband fre-
quency and the sideband frequencies When
the nonlinear characteristics of the devices of these circuits are consid-
ered, these circuits are subject to the effects of both the nonlinearities,
which give rise to harmonic and intermodulation components, and pe-
riodic switching, which generates sideband frequency components. This
substantially increases both the number of the frequency components in
the response of these circuits and the complexity of the analysis of these
circuits.
Distortion can be analyzed in either the time domain or frequency
domain, depending upon the characteristics of the nonlinearities of cir-
cuits. The time domain approach first computes the steady state re-
sponse of the circuits to sinusoidal inputs. The frequency components of
the response of these circuits are then computed by a post fast Fourier
transform analysis. Although this approach is universal, a major draw-
back of the approach is that the time domain response of the circuits
must be computed until a steady state is reached. The results of the

computation in the transient portion, however, must be discarded. Only
those in the steady-state is used in FFT analysis to yields distortion.
This process could be very time consuming, especially for periodically
switched nonlinear circuits because the time-domain analysis of these
circuits is costly, as detailed in Chapter 7. To speed up time-domain
analysis, trigonometric polynomial [122] and envelope-following integra-
tion algorithms [123] have been proposed. Finite difference method [124]
and shooting methods [125, 126, 127, 128], which compute the steady-
state response directly, have also been investigated extensively.
As compared with the time domain approaches, frequency domain
methods compute the distortion directly. These methods are more ef-
ficient computationally for circuits containing mild nonlinearities, i.e.
the characteristics of the nonlinear elements can be depicted adequately
using a finite number of the terms of their Taylor series expansion at
the operating point. Analytical approaches [129, 130, 131] for distortion
analysis are pen-and-paper approaches. They are effective for circuits of
small size only. Harmonic balance approach [132, 133, 134] obtains the
distortion components by solving the determining equations derived from
balancing the harmonics of the response of circuits to a sinusoidal input
numerically. This approach is computationally expensive because the
determining equations are nonlinear algebraic equations and the num-
ber of unknowns is directly proportional to the characteristics of the
nonlinearities in the circuits, i.e. the order of harmonics K considered
in approximation of the response of the circuit
where is the frequency of the sinusoidal input. is then plugged

into the nonlinear equations depicting the circuits and a power series
in is obtained. Making use of the identity of power series that
a power series is zero if and only if all the coefficients of the power
series are identically zero, a set of nonlinear algebraic equations with
the unknowns are derived. These nonlinear alge-
braic equations are called determining equations. They are solved using
Frequency Domain Analysis of Periodically Switched Nonlinear Circuits 305
Newton-Raphson iterations for To reduce the cost

of computation, the piecewise harmonic balance method [133, 135] and
substitution methods [136] were proposed to accelerate the computation
by partitioning a nonlinear circuit into linear and nonlinear sub-circuits.
The linear sub-circuit can be solved efficiently in the frequency domain
while the nonlinear sub-circuit is solved using conventional harmonic
balance approach. The solutions of both circuits are matched at the
boundary of the two sub-circuits. Because the size of the nonlinear sub-
circuit is usually much smaller, a significant reduction in computation is
achieved.
As compared with harmonic balance methods that derive distortion
from solving determining equations numerically using Newton-Raphson
iterations, Volterra series based approaches [137, 138, 43] compute dis-
tortion in the frequency domain directly and are computationally effi-
cient. They have been applied for distortion analysis of nonlinear time-
invariant circuits and ideal switched capacitor networks [86, 139]. To
investigate the distortion of nonlinear switched current networks, non-
linear switched capacitor networks with parasitics and non-idealities, and
general switched nonlinear circuits, it becomes indispensable to include
other types of elements, such as resistors, inductors, controlled sources,
and current sources in both the modeling of the nonlinear elements of
these circuits and the analysis of these circuits.
This chapter is concerned with distortion analysis of multi-phase pe-
riodically switched nonlinear circuits in the frequency domain. The ap-
proach presented in the chapter is based upon time-varying Volterra
functional series, Schetzen’s multi-linear theory [140], and time-varying
network functions and multi-frequency transfer functions of nonlinear
periodically time-varying systems introduced in Chapter 3. The chapter
is organized as follows: Section 1 reviews the basics of the frequency
domain characteristics of nonlinear circuits. Section 2 investigates the
representation of the network variables of periodically switched nonlinear
circuits using Volterra functional series. It also develops an algorithm for
frequency analysis of periodically switched nonlinear circuits. In Section
3, the harmonic distortion of periodically switched nonlinear circuits is
derived whereas the intermodulation distortion of these circuits is ob-
tained in Section 4. In assessment of the effectiveness of the method, the

distortion of several periodically switched nonlinear circuits is computed
using the method presented in the chapter and the results are compared
with those obtained from transient-FFT analysis using SPICE in Section
5. The chapter is summarized in Section 6.
1. Fundamentals
1.1 Harmonic Distortion
The harmonic distortion of nonlinear circuits is obtained by applying
a sinusoid to the input of the circuits and computing the harmonics of
the response of the circuits. Consider a nonlinear time-invariant circuit
with the input-output relationship given by
where and are constants, and are the input and output
of the circuit, respectively. To obtain the harmonic distortion, let
we have
The second-order harmonic distortion is obtained from
For circuits with mildly nonlinearities and when the amplitude of the
input is small, we have Eq.(12.4) is simplified to
In a very like manner, one can show that
The total harmonic distortion, a measure of how closely the output

waveform resembles a pure sinusoid, is obtained from
1.2 Intermodulation Distortion

Intermodulation occurs when two sinusoids of different frequencies are
applied to nonlinear circuits. Consider the same nonlinear circuit. Let
the input be
It is trivial to show that the response of the circuit contains the fre-
quency components tabulated in Table 1.2
The second-order intermodulation is obtained from
Note that was assumed. The third-order inter-

modulation is computed from
It is seen that :
Harmonic and intermodulation distortion is intrinsically related to

each other by
Both harmonic distortion and intermodulation distortion are propor-

tional to (i) the characteristics of the nonlinearities, which are quan-
tified by and and (ii) the amplitude of the input signal.
Third-order intermodulation components at and are

of critical concern, particularly for RF applications. This is because
for these applications, and are usually very close (adjacent
channels), the beats of the third-order intermodulation components
are very close to that of the wanted channel.
The preceding power series based distortion analysis is valid for cir-
cuits consisting of elements without memory or circuits at low fre-
quencies where the effect of the past information is negligible. For
circuits at high frequencies, the effect of the past information must
be taken into account when analyzing the behavior of the circuits. In
this case, and become frequency-dependent. Volterra func-
tional series should be used to characterize the behavior of nonlinear
circuits.
2. Distortion Analysis of Periodically Switched

Nonlinear Circuits
Periodically switched nonlinear circuits are nonlinear periodically time-
varying systems. It was shown in Chapter 3 that the network variable
of a periodically switched nonlinear circuit can be represented by a
time-varying Volterra series
where is the term of the Volterra series expansion of

A finite number of terms are usually sufficiently if the characteristics of
the nonlinear elements are mild. Multiplying (12.12) by the window

function defined in (2.4), we obtain
where
and
Further multiplying (12.12) by the Dirac delta function

gives
where is the network variable at

is the term of the Volterra series expansion of
Fourier transform of (12.13) gives
Writing (12.17) for all clock phases and summing up the results give the
complete response of the periodically switched nonlinear circuit in the
frequency domain
Eq.(12.18) reveals that the frequency response of periodically switched

nonlinear circuits can be obtained by summing up that of corresponding
Volterra circuits.
It was shown in Chapter 11 that in the analysis of periodically switched
linear circuits, the difficulties associated with periodically time-varying
topology are handled by decomposing the circuits into a set of linear
time-invariant sub-circuits connected via the initial conditions of the
network variables [8]. Analogously, in distortion analysis of periodically
switched nonlinear circuits, a periodically switched nonlinear circuit can
be considered as a set of nonlinear time-invariant sub-circuits connected
via the initial conditions of the network variables of the circuits.
To simplify presentation, we assume that the characteristics of the
nonlinear elements are mild and their behavior can be depicted ade-
quately using the third-order Taylor series expansion of the nonlinear
characteristics. Further assume that the network variables of periodi-
cally switched nonlinear circuits can also be represented by their third-
order Volterra series expansion. Using modified nodal analysis, the non-
linear time-invariant circuit in phase is characterized by
where and are constant matrices depicting respectively the second

and third-order nonlinear characteristics of the circuits. The elements of
the vectors and are the square and cube of the correspond-
ing elements of respectively. Note that we have used scalar-like
notations for the purpose of their self-explanation.
If the input is changed from to where is a nonzero
constant, Eq.(12.19) becomes
Eq.(12.20) is essentially a power series in Making use of the identity

of power series that a power series equals to zero if and only if all the
coefficients of the power series are identically zero, and
we arrive
where
and are the response of the periodically switched linear cir-

cuits characterized by (12.23) and (12.24), respectively. Note
and are vectors whose dimensions are the same as The
elements of are the products of the corresponding elements of
and whereas those of are the cube of the correspond-
ing elements of
Fourier transform of (12.22)-(12.24) gives
Eqs.(12.26)–(12.28) reveal that :
The behavior of a periodically switched nonlinear circuit can be char-

acterized by a set of intrinsically related periodically switched linear
circuits. The circuits characterized by (12.26)–(12.28) are termed re-
spectively as the first-, second-, and third-order Volterra circuits of
the periodically switched nonlinear circuit. They are denoted by
and respectively. These Volterra circuits have the same in-

cidence matrix but different inputs. This observation reveals that in
solving these circuits, the transit matrix for all Volterra circuits
are the same and need to be computed only once. The zero-state
vectors, however, differ and must be computed separately.
The input of the circuit characterized by (12.27) is obtained from the

solution of (12.26) whereas that of the circuit depicted by (12.28) is
from the solution of (12.26) and that of (12.27). Volterra circuits
must be solved in a sequential order with the lower-order Volterra
circuits solved first.
Although the topology of and are identical, the frequency

components of and differ from each other due to their
distinct inputs. As a result, LU-decomposition of must
be performed separately.
3. Harmonic Distortion
In this section, the frequency response of a periodically switched non-
linear circuits to a sinusoidal input is obtained using the method pre-
sented in the preceding sections.
3.1 The First-Order Volterra Circuit

Let the input of a periodically switched nonlinear circuit be
The sinusoidal input contains two distinct frequency components at

and Using the principle of superposition, it can be shown that
the complete response of denoted by contains the frequency
components and can be written as
where and denote the phasors of the

frequency component of at frequencies and
respectively. The contribution of to the fundamental component at
is given by
3.2 The Second-Order Volterra Circuit

The input of denoted by is given by (12.25) and can be
written as
where and are the phasors

of and respectively. Among the
frequency components of only those at contribute to
the second-order harmonic. In saying so, we have assumed that
and will not be the multiples of for any This is often
the case in reality as is usually much higher than The second-
order harmonic of the output is obtained by summing up the
response of at frequency with an input at frequencies
where is the aliasing transfer function of with the

input at the frequency and the output at the frequency
The complete solution of in the time domain, denoted by with
the input given by (12.31), is given by
where and are the phasors

of at frequencies and respectively.
These phasor quantities are needed in solving as to be shown in the
following section.
3.3 The Third-Order Volterra Circuit

The input of contains two components. The first component
contains frequency components and
Among them, only those at contributes
to the third-order harmonic at The input at however,
affects the fundamental. Note that it was assumed that and
will not be multiples of either or for any Based
on these observations, we conclude that
needs to be solved with the input at frequencies

and the output at the frequency for its contribution
to the third-order harmonic at
needs to be solved with the input at frequencies

and the output at the frequency for its contribution
to the fundamental at
In computing the input of the solutions of at and

at are needed. and therefore need to be solved at all
relevant side band frequencies with the output at these frequencies.
however, needs only to be solved with the input at specific fre-
quencies because only the response at the fundamental frequency
and that at the third-order harmonic frequency are of interest.
The output of at due to is obtained from

where is the aliasing transfer function of with the

input at the frequency and the output at the frequency
is computed from
The third-order harmonic component generated by is obtained

from
where
and is the aliasing transfer function of with the

input at the frequency and output at the frequency
The other input of also contributes to both the funda-
mental and third-order harmonics. Its contribution can be computed
in a similar manner as that of Let its contribution to the
base band and the third-order harmonic be denoted by and
respectively. In conclusion :
The fundamental component of the response of the periodically switched

nonlinear circuit is obtained by summing up the contribution of the
first-order Volterra circuit with the input at frequencies
and the output at the frequency and that of the third-order
Volterra circuit with the input at frequencies and the
output at the frequency
The second-order harmonic component of the response of the peri-

odically switched nonlinear circuit is determined from the response
of the second-order Volterra circuit with the input at frequencies
and the output at the frequency
The third-order harmonic component of the response of the peri-

odically switched nonlinear circuit is obtained by summing up the
contribution of with inputs and at frequencies
and the output at the frequency
The second-order harmonic distortion of the circuit is computed from
and the third-order harmonic distortion in obtained from
3.4 The Fold-Over Effect

Eqs.(12.32), (12.34) and (12.36) demonstrate that the high-order side
band components of the inputs of and contribute to both the
fundamental and harmonic components of the response in the base band.
This is analogous to the fold-over effect encountered in the noise analysis
of periodically switched linear circuits presented in Chapter 11. The
folding effect in computing is illustrated graphically in Fig. 12.1.
The frequency reversal theorem introduced in Chapter 3 can be employed
to reduce the cost of computation in calculating these aliasing transfer
functions.
4. Intermodulation Distortion
Intermodulation distortion arises when the input of a periodically
switched nonlinear circuit contains two or more sinusoidal signals of
different frequencies. For example, in a RF receiver, the frequency dif-
ference between two adjacent channels at frequencies and denoted
by is usually orders of magnitude smaller as compared

with or Due to the nonlinearities of the receiver, frequency com-
ponents other than those of the carriers are generated. The harmonic
components in the output of the receiver are not of concern because they
will be filtered out by a downstream low-pass filter. The third-order in-
termodulation at frequencies and however, are of a
critical concern because their spectra fall so close to those of the carriers
that the downstream filter can not eliminate them effectively. The anal-
ysis of the third-order intermodulation distortion is therefore of practical
importance. In this section, we compute the third-order intermodulation
of periodically switched nonlinear circuits.
4.1 The First-Order Volterra Circuit

Let the input of a periodically switched nonlinear circuit be
From the principle of superposition, the time-domain response of of

the periodically switched nonlinear network, denoted by contains
the frequency components and
and can be represented by
where and
are the phasors of at frequencies
and respectively.
4.2 The Second-Order Volterra Circuit

The input of contains frequency components
and Conse-
quently, the output of consists of frequency components
and Further analysis
shows that the input of at and do not con-
tribute to the third-order inter-modulation. As a result, the output of
at these frequencies is not required. The output of at other fre-
quencies, however, must be computed. They are computed in a similar
manner as that of harmonic distortion.
4.3 The Third-Order Volterra Circuit

The input of consists of the components and
It can be shown that among the frequency components of
only those at the frequencies and
contribute to the third-order inter-modulation whereas those at the fre-
quencies and contribute to the fundamentals at
and respectively. therefore needs to be solved with
the input at the frequencies and

and outputs at the frequencies and respectively.
the input at the frequencies and and output at the

frequencies and respectively.
Note that the amplitude of the inputs at these frequencies must be cal-
culated prior to solving Similarly, among the frequency components
of only
the input at the frequencies and are

of concern as they contribute to the third-order inter-modulation.
the input at the frequencies and as they contribute

to the fundamentals.
The frequency reversal theorem can be used in both cases to lower

the cost of computation.
The third-order inter-modulation distortion at is computed
from
where and are the contributions of

and at respectively, and
are the contributions of and at respectively.
5. Examples
In this section, both the harmonic distortion and intermodulation
distortion of several periodically switched nonlinear circuits are analyzed
using the algorithms presented in this chapter. The results are compared
with those from transient-FFT analysis of SPICE.
5.1 Modulator
Consider the modulator shown in Fig.12.2 with the parameter values

given in Table 12.2 [141]. The nonlinear resistor is modeled as a
nonlinear current-controlled voltage source
The circuit was solved using the method presented in the preceding
sections and results are shown in Table 12.3, together with those from
transient-FFT SPICE simulation of SPICE. Care was taken in choosing
the step size in the transient analysis, collecting steady-state response
data, and selecting the number of data points and windows in transient-
FFT analyses of the modulator using SPICE [142, 143, 68]. As observed
that the results compare well with those from SPICE.
To demonstrate the fold-over effect in distortion analysis of period-
ically switched nonlinear circuits, the dependence of the second-order
harmonic components at 1 kHz on the number of side bands consid-
ered is plotted in Fig.12.3. It is seen that the second-order harmonic
component of the response of the modulator converges rapidly.
5.2 Stray-Insensitive Switched Capacitor

Integrator
Consider the stray-insensitive switched capacitor integrator shown
in Fig.12.4 with parameters given in Table 12.4. MOSFET switches
and are modeled as a linear resistor of resistance in
series with an ideal switch. is modeled as a nonlinear resistor in
series with an ideal switch. The nonlinear resistor is characterized by

The model of the operational amplifier is the same
as those used in Chapter 11.
The circuit was solved and the results are shown in Table 12.5, to-
gether with SPICE simulation results. To ensure that the second-order
harmonic components are free of numerical errors, several SPICE simula-
tions with different step sizes used in transient analysis were conducted.
The absolute errors between the harmonic components obtained from
using different step sizes in transient analysis are less than 0.2 decibels.
It is seen that the method gives good prediction of both the funda-
mental and the second-order harmonic components. The second-order
harmonic component at 1 kHz is plotted in Fig.12.5 versus the num-

ber of side bands considered. It is seen that the second-order harmonic
converges monotonically with the increase in the number of side bands.
Also observed that the rate of convergence is slower as compared with
that of the modulator.
5.3 Switched Capacitor Integrator With

Nonlinear Op Amp
The third example is the stray-insensitive switched capacitor integra-
tor with a nonlinear operational amplifier shown in Fig.12.6 with its
parameters given in Table 12.6. The only nonlinearity is the operational
amplifier characterized by
The harmonic components of the output were computed and the re-
sults are tabulated in Table 12.7 for and Table
12.8 for SPICE simulation results are also
shown in the tables. It is seen that the results are in good agreement
with those from SPICE simulation. Also, in Table 12.7, since
zero second-order harmonic is predicted by the method as both the first-
and third-order periodically switched linear circuits do not contribute to
the second-order harmonic. This agrees with SPICE simulation. SPICE

results for are plotted in Figs. 12.8 and 12.7.
1
By comparing these plots with Fig.3.2, it is evident that the theory
1
The estimated time constant due to the sampling capacitor and channel resistance of MOS-
FET switches is about To ensure the establishment of the steady state, the first 1000
presented in Chapter 3 gives an accurate prediction to the fundamental

frequency component, second-order, and third-order harmonic compo-
nents of the response. Since only up to the third-order Volterra series
expansions were considered, the method is not capable of predicting
high-order harmonics.
The CPU time for computing the distortion at a single frequency is 4.1
minutes on 450MHz, 256MB Sun Sparc stations (Matlab implementa-
tion) while SPICE consumed 2.78 hours. The efficiency gain from using
the proposed method is evident.
To demonstrate the efficiency gain obtained from using the frequency
reversal theorem in the distortion analysis of periodically switched non-
linear circuits, the same circuit was solved with frequency reversal the-
orem implemented and without (brute-force). The results are tabulated
in Table 12.9. It is seen that the results from both methods agree well.
The efficiencies of the two algorithm are also compared in terms of their
samples were discarded from FFT analysis. Also the number of samples used in FFT analysis
was 64k. Rectangular window was employed.
CPU time. It was observed that the method with the frequency rever-
sal theorem implemented is nearly three times that of the brute-force
approach. The speedup is less than those in noise analysis, as shown in
Chapter 11 separately. This is because the frequency reversal theorem

is only employed in solving because needs to be solved at all rel-
evant side band frequencies, which amounts to a significant portion of
the CPU time.
The inter-modulation distortion of the circuit with
was also investigated. The input consists of two sinusoids
of frequencies 1 kHz and 1.1 kHz, respectively. The third-order inter-
modulation components were computed and the results are tabulated in
Table 12.10, together with SPICE simulation results. A good agreement
is observed. SPICE simulation results for and
are plotted in Figs. 12.9 and 12.10. A careful comparison of these
plots with Fig.3.3 reveals that all major beats of the response predicted
by the method given in Chapter 3 match those from SPICE simulation.
To demonstrate the analysis of harmonic distortion due to the exis-

tence of nonlinear capacitors, the circuit in Fig.12.4 is considered. The
only nonlinear element is capacitor modeled by
while remains unchanged. To avoid numerical difficulties, the circuit

is impedance-scaled by and frequency scaled by 100. As a result,
the ON-resistance of MOSFET switches is changed from to
The capacitance of is changed from to
becomes
The clock frequency is changed from 100 kHz to 1000 Hz. The opera-
tional amplifier is modeled as an ideal voltage-controlled voltage source
with gain 1000. The distortion of the output at frequency 100 Hz was
analyzed. For the purpose of comparison, it was also computed using
SPICE. Both results are tabulated in Table 12.11. As can be seen that
the results are in good agreement.
6. Summary
Volterra series based frequency-domain analysis of the distortion of
general periodically switched nonlinear circuits has been presented in
this chapter. We have shown that a periodically switched nonlinear cir-
cuit can be characterized by a set of periodically switched linear circuits
called Volterra circuits. The input of high-order Volterra circuits is a

nonlinear function of the response of lower-order Volterra circuits only.
Distortion of the periodically switched nonlinear circuit is obtained by
solving corresponding Volterra circuits. This result is a generalization of
the multi-linear theory known for nonlinear time-invariant circuits. We
have also shown that the aliasing effect encountered in noise analysis
of periodically switched linear circuits also exists in distortion analy-
sis of periodically switched nonlinear circuits. Computation associated
with the folding effect can be minimized by utilizing the adjoint net-
work theory of periodically switched linear circuits presented in Chapter
10, in particular, the frequency reversal theorem. Distortion of several
periodically switched nonlinear circuits has been analyzed and the re-
sults compare well with those from transient-FFT analysis of SPICE. As
compared with conventional harmonic balance approaches, the method
is more efficient computationally in computing both the harmonic and
intermodulation distortion of periodically switched circuits with mildly

nonlinearities.
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Index
adjoint network, 212 comparators, 173

capacitors, 214 computer oriented formulation methods,
controlled sources, 214 17
ideal switches, 212 equivalent-circuit, 17
inductors, 214 modified nodal analysis, 18
internal branches, 211 signal flow diagram, 17
resistors, 213 state-space, 17
time reversal, 210 switching matrix, 17
aliasing effect, 284 Tableau formulation, 18
transmission matrix, 17
baseband, 35 two-graph, 18
baseband frequency, 301 constitutive equations of nonlinear voltage-
basis functions, 73 controlled voltage source, 22
behavioral modeling, 197 corrector, 55
Boltzmann constant, 275 current crowding, 278
current-mirror amplifier, 162
charge conservation, 170, 230
charge injection, 139 Dirac impulse function, 25, 66, 233, 276
charge of an electron, 276 dual-time circuits, 193
Circuits with internally controlled switches dual-time systems, 10
buck linear voltage regulators, 183
current-mode comparators, 181 envelope-following, 302
diodes, 178 equivalent noise bandwidth, 127
inconsistent initial conditions, 182 equivalent resistance of the switched ca-
internally controlled switches, 177 pacitor, 5
MOSFETS, 179 exponentially decaying function, 66, 86
switching instants, 182 external clocks, 19
switching variables, 177 extraction of final conditions, 230
voltage-mode comparators, 181
clock feed-through, 139 fast Fourier transform (FFT), 301
clock jitter, 131 finite difference method, 302
CMOS pass-transistor gates, 281 Fourier series, 75
coefficient of variance, 125 frequency reversal theorem, 325
group delay, 258 Fourier series interpolation, 147
fifth-order switched capacitor low Gibb effect, 158
pass filter, 263 interpolating Fourier series, 147
interpolating function, 147
harmonic balance approach, 302 interpolation error, 148
determining equations, 302 Lagrange interpolation, 147
piecewise harmonic balance method, Newton finite difference interpola-
303 tion, 147
substitution methods, 303 polynomial-based interpolation, 147
harmonic balance approach determining rate of convergence, 158
equations, 302 simulation window, 147
harsh nonlinearities, 173 interval analysis, 123
ideal switched capacitor networks, 16 Kronecker delta function, 209

ideal switching, 11, 16, 139
linear periodically time-varying system,
incomplete charge transfer, 11, 17, 230
35
inconsistent initial conditions, 11, 83, 99
linear periodically time-varying systems,
backward Euler based algorithms,
264
91
aliasing transfer function, 38, 42
consistent initial condition compo-
baseband frequency, 39
nent, 103
Dirichlet-Jordan criterion, 37
consistent initial conditions, 100 phasor representation, 39
derivatives of unit step function
sideband frequencies, 38, 39
91
linear time-invariant systems, 35
Dirac impulses in linear circuits, 104 linear time-varying systems, 35
Dirac impulses in nonlinear circuits, time-varying network function, 36
106 bi-frequency transfer function, 42
error of numerical Laplace inversion, excitation time, 36
86 impulse response, 36
existence of Dirac impulses, 103 observation time, 36
four-step algorithm, 97 time-varying network functions, 41
impulse-free component, 100 linear transconductance, 162
inconsistent initial condition compo- linearly independent, 73
nent, 103 local truncation error (LTE), 140
Taylor series based algorithm, 99 lumped electrical networks, 208
two-forward-step algorithm, 92
two-step algorithm, 83, 88, 96 Matlab, 165
two-step algorithm for linear cir- Matrix stamps
cuits, 98 ideal switches, 22
Volterra functional series based al- inductors, 28
gorithm, 102 linear time-invariant capacitors, 24
initial conditions, 20 memoryless elements, 21
instantaneous charge (flux) distribution, nonlinear capacitors, 25
11 switching variable, 22
inter-reciprocal, 212 matrix stamps, 22
interpolation memoryless elements, 40
boundary conditions, 158 mild nonlinearities, 173
exponential interpolation, 147 modeling of switches
INDEX 349
full-transistor model, 13, 84 average power, 267
ideal switch model, 14, 84 average power spectral density, 272
voltage-modulated resistor model, bipolar junction transistors, 277
14, 84 base resistance, 278
modeling of white noise extrinsic base resistance, 278
using a set of sinusoids, 126 intrinsic base resistance, 278
using random pulses, 126 brute-force method, 288
modified nodal analysis, 197 corner frequency of flicker noise, 125
modulator, 320 Curson’s theorem, 275
Monte Carlo analysis, 119, 123 cyclo-stationary in the wide sense,
MOSFET 268
diffusion current, 280 diffusion resistors, 277
drift current, 280 flicker noise, 125, 264, 276
Fermi potential, 279 carrier density fluctuation model
gate capacitance per unit area, 280 of flicker noise, 276
gate leakage current, 279 carrier mobility fluctuation model
gate transconductance, 280 of flicker noise, 276
gate-current fluctuation, 282 corner frequency, 277
saturation region, 280 fold-over effect, 12
strong inversion, 279 Johnson noise, 275
sub-threshold region, 282 mean-square value, 267
substrate transconductance, 280 noise-current generator, 283
surface mobility of charge carriers, noise-voltage generator, 283
280 Nyquist law, 275
surface potential, 279 Nyquist theorem, 128
triode region, 280 polysilicon resistors, 277
multi-frequency network functions, 35 power spectral density, 125, 264,
multi-frequency transfer functions, 303 266, 268
multi-linear model of nonlinear elements, power spectral density of the ther-
140 mal noise, 275
multi-linear model of nonlinear elements Schottky’s theorem for pn-junctions,
with memory, 143 276
multi-linear theory, 303 shot noise, 125, 264, 275
multi-step numerical Laplace inversion al- stationary, 267
gorithms, 233 stationary in the wide sense, 267
multi-step predictor-corrector algorithms, thermal equilibrium, 275
139 thermal noise, 125, 264, 275
thermal noise of the drift current,
Newton-Raphson iterations, 59, 139 280
nodal charge conservation law, 18 Wiener-Khintchine theorem, 268
noise nonlinear capacitor, 143
noise, 276 nonlinear conductor, 163
aliasing effect, 273 nonlinear periodically time-varying, 46,
autocorrelation function, 266 47
autocovariance, 267 nonlinear periodically time-varying sys-
average output noise power of pe- tems, 303
riodically switched linear cir- nonlinear resistor, 157
cuits, 272 nonlinear time-varying systems, 35
fundamental component, 45 Padé fraction, 60
harmonic components, 45 Padé polynomials of 62
harmonic frequency components, 42 parasitic resistances of BJTs, 278
intermodulation distortion, 47 periodically switched circuits, 17
multi-frequency transfer function, periodically switched linear circuits
43 baseband component, 233
nonlinear voltage-controlled voltage source, frequency reversal theorem, 290
141 initial conditions, 231
Numerical Laplace inversion sideband components, 233
accuracy of numerical Laplace inver- single-tone input, 233
sion, 64 sub-circuits, 231
Laplace inversion, 62 periodically switched nonlinear circuits,
residue theorem, 63 140
residues, 63 fold-over effect, 316
residues of Pade polynomial frequency reversal theorem, 316
64 fundamental component, 313
residues of Pade polynomial intermodulation distortion, 316
65 second-order harmonic, 313
zeros of Pade polynomial 64 third-order harmonic, 314, 315
zeros of Pade polynomial third-order intermodulation compo-
65 nents, 317
numerical Laplace inversion, 53 Volterra circuits, 311
stepping algorithm, 72 periodically time-varying linear systems,
Nyquist theorem, 155, 273 242
phasors, 209
operational amplifier piecewise-linear input waveform, 74
finite bandwidth, 197 power series, 40
finite input impedance, 197 predictor-corrector algorithm
macro models, 215 linear single-step predictor-corrector
non-zero output impedance, 197 (LSS-PC), 53
slew rate of operational amplifiers, predictor-corrector algorithms
139 first-order predictor, 54
order of interpolating Fourier series, 156 forward Euler formula, 54, 55
order of Taylor series expansion, 156 linear multi-step predictor-corrector
order of Volterra series expansion, 156 (LMS-PC), 53
orthogonality of exponential series, 213 linear multi-step predictor-corrector
over-sampled sigma-delta modulators, 192 (LMS-PC) algorithms, 58
noise shaping, 198 linear single-step predictor-corrector
over-sampling ratio, 193 (LSS-PC) algorithm, 55
single-bit second-order continuous- truncation error, 54
time over-sampled sigma-delta predictor-corrector numerical integration
modulator, 198 algorithms, 55
single-bit second-order switched ca- principle of superposition, 149, 312
pacitor over-sampled sigma- PSPICE, 139
delta modulator, 198
sampled-data simulation, 109, 197
Padé approximation, 53 sampled-data simulation of linear circuits
Padé approximates, 60 arbitrary inputs, 114
INDEX 351
inconsistent initial conditions, 116 normalized sensitivity, 258
inconsistent initial conditions of sen- normalized sensitivity of the magni-
sitivity networks, 121 tude of the response, 236
normalized sensitivity, 120 normalized small-change sensitivity,
pre-processing step, 121 235
sensitivity analysis, 119 output, 247
sinusoidal inputs, 113 perturbations, 241
step size, 198 resistors, 244
two-step algorithm, 116, 140 sensitivity network, 250
unit step input, 113 stray-insensitive switched capacitor
zero-input response, 111 integrator, 255
zero-state response, 111 voltage-controlled voltage source,
zero-state vector, 111 245
sampled-data simulation of periodically sensitivity network, 120
switched nonlinear circuits sensitivity current, 251
accuracy, 155 sensitivity voltage, 251
error propagation, 156 shooting method, 302
inconsistent initial conditions, 140, sideband, 35
151 sideband frequencies, 301
lower bound of sampling frequency, sideband frequency components, 301
155 signal-to-noise ratio (SNR), 200
maximum step size, 155 simulation window, 156
normalized mean square error (NMSE), sparse matrix, 18
158 Spectre, 139
sensitivity, 152 statistical analysis, 119
sensitivity of periodically switched advanced first-order second-moment
nonlinear circuits, 140 (AFOSM) method, 125
simulation window, 158 first-order second-moment (FOSM)
stability, 155 method, 124
step size, 155 first-order second-moment method,
two-step algorithm, 151 293
two-step algorithm for sensitivity Monte Carlo analysis, 295
analysis, 154 stepping algorithm, 72
Schmitt triggers, 173 stiff systems, 14, 84
second-order nonlinear transconductance, stray-insensitive switched capacitor inte-
162 grator with a nonlinear opera-
sensitivity analysis tional amplifier, 324
adjoint network, 240, 254 sub-circuits, 20
aliasing transfer function, 254 switched capacitor band pass filter, 257,
brute-force, 166 292
capacitors, 244 switched capacitor integrator, 166, 287
controlled sources, 245 switched capacitor low pass filter, 286
current-controlled current source, switched capacitor network
245 fifth-order elliptic switched capaci-
direct sensitivity analysis, 237 tor filter, 235
ideal switches, 246 stray-insensitive switched capacitor
inductors, 245 integrator, 320
inputs, 247 switching instants, 92
Tellegen’s theorem unit ramping function, 75
incidence matrix, 208 unit step function 66
incremental weak form of Telle-
gen’s theorem for periodically voltage-controlled voltage source
switched linear circuits in the behavioral model of quantizers, 194
phasor domain, 244 clocked quantizer, 194
sensitivity analysis, 241 comparators, 192
strong form, 208 decimator, 192
Tellegen’s theorem for periodically quantizer, 192, 194
switched linear circuits in the Volterra circuits, 102, 146
phasor domain, 210 Volterra circuit, 151
time domain - same circuit, 208 first-order Volterra circuit, 146
weak form, 208 second-order Volterra circuit, 147,
Tellegen’s theorem for periodically switched 149
linear circuits, 242 Volterra circuits of periodically switched
nonlinear circuits, 140, 144
Tellegen’s theorems
Volterra functional series, 35, 40
Tellegen’s theorem for periodically
harmonic distortion, 46
switched linear circuits, 210
symmetrical kernels, 46
time-varying network functions, 303
Volterra kernel, 41
time-varying topology, 10
Volterra series expansion, 141
time-varying Volterra functional series,
303
Watsnap, 224, 225, 255
time-varying Volterra series, 307 wavelet, 75
transfer functions, 38 weakly nonlinear, 141
transient-FFT analysis, 198 weakly nonlinearities, 140
transit matrix, 312 window function, 308
transition matrix, 72 worst-case analysis, 123
trigonometric polynomial, 302
truncation error, 156 zero-state vector, 72
two-dimensional Fourier transform, 269 zero-state vectors, 312

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COMPUTER METHODS FOR

KLUWER ACADEMIC PUBLISHERS

©2004 Kluwer Academic Publishers

Print ©2004 Kluwer Academic Publishers

All rights reserved

Created in the United States of America

Visit Kluwer Online at: http://kluweronline.com

Part I The Fundamentals

Part II Time Domain Analysis

Part III Frequency Domain Analysis

3 Group Delay Analysis 260

1.1 Implementation of resistors using switched capacitors. 5

2.4 Clock phases in a clock period represents the

4.6 Dependence of the relative error of the exact solu-

6.5 White noise is represented by a train of pulses with

7.21 Sensitivity of of the circuit of Fig.7.17 with

9.9 Spectrum of the response of the single-bit second-

11.5 Sensitivity analysis of periodically switched linear

11.21 Group delay of the fifth-order switched capacitor

11.34 Ratio of CPU time of the brute-force approach for

12.7 Spectrum of the output of the stray-insensitive switched

4.1 Padé approximates of 62

10.7 Frequency response of the band pass filter of Fig.10.9

12.7 Harmonic distortion of the stray-insensitive switched

Mixed-mode switching circuits distinguish themselves from other cir-

is an attempt to summarize the recent advance in computer methods for

The book comprises of three parts.

Part I is concerned with the issues that are fundamentally important

analyzed. The effectiveness of these methods is assessed using exam-

of a graduate course on computer-aided analysis of mixed-mode switch-

FEI YUAN AND AJOY OPAL

The authors wish to take this opportunity to express their sincere

This chapter presents an overview of mixed-mode switching circuits.

Circuits with externally clocked switches. The switches in these cir-

Circuits with internally controlled switches. The switches in these

Circuits with both internally controlled and externally clocked switches.

2. Switched Capacitor Techniques

Large variation of resistance - Although diffusion resistors have a

Large parasitic capacitance - diffusion resistors have a large parasitic

Strongly nonlinear characteristics - the resistance of diffusion resistors

To overcome these difficulties, switched-capacitor techniques that syn-

C is the capacitance of the capacitor, is the clock period,

This is clearly a big advantage, as compared with active filters realized

3. Switched Current Techniques

blocks using analog or mixed-mode IC technologies, as they are much

4. Characteristics of Mixed-Mode Switching

ear circuits [16], Volterra series-based distortion analysis of periodically

Time-varying topology - The topology of mixed-mode switching cir-

Dual-time systems - Periodically switched circuits are dual-time sys-

Instantaneous charge (flux) distribution - When the loop resistance

Incomplete charge (flux) transfer - When the loop resistance becomes

Inconsistent initial conditions - Because practical switched capacitor

abrupt change in loop currents, resulting in impulsive inductor volt-

This chapter deals with computer-oriented formulation of mixed-mode

1.1 Full-Transistor Models

1.2 Voltage-Modulated Resistor Models

1.3 Ideal Switch Models

The difference between the voltage-modulated resistor models and the

2. Formulation Methods for

Ease in circuit formulation. MNA formulation inherits the intrinsic

Branch voltages and many branch currents are eliminated in MNA

Circuit matrices are sparse. The sparsity of circuit matrices enables

Convenience in calculating parameter sensitivity [5].