PROGRAM-1 Aim: Write down VHDL program for full Adder and full Subtractor System Description: In electronics,

an adder or summer is a digital circuit that performs

addition of binary numbers. In many computers and other kinds of processors, adders are used not only in the arithmetic logic unit(s), but also in other parts of the processor, where they are used to calculate addresses, table indices, and similar operations. The full-subtractor is a combinational circuit which is used to perform subtraction of three bits

Logic Diagram:

Full Adder

A 0 1 0 1 0 1 0 1

Inputs B 0 0 1 1 0 0 1 1

Cin 0 0 0 0 1 1 1 1

Outputs Cout 0 0 0 1 0 1 1 1

S 0 1 1 0 1 0 0 1

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Full Subtractor

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

BorIN 0 1 0 1 0 1 0 1

D 0 1 1 0 1 0 0 1

BorOUT 0 1 1 1 0 0 0 1

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VHDL CODE: Code for Full Adder

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;

ENTITY full_adder IS PORT(A,B,Ci:instd_logic; S,Co:outstd_logic); END ENTITY full_adder; ARCHITECTURE DF OF full_adder IS BEGIN S<= A XOR (B XOR Ci); Co<= (A AND B) OR (Ci AND B) OR (Ci AND A) ; END ARCHITECTURE DF;

Code for Full Subtractor

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY full_subtractor IS PORT(A,B, BorIN:in std_logic; D, BorOUT:out std_logic); END ENTITY full_subtractor; ARCHITECTURE DF OF full_subtractor IS BEGIN D<= A XOR (B XOR BorIN); borout<=((not A)and B)or((not A)and borin)or(B and borin); END ARCHITECTURE DF;
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OUTPUT: FULL ADDER

FULL SUBTRACTOR

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PROGRAM-2

Aim: Write down VHDL program for 4 to 1 Multiplexer using Behavioural Model, Structural
Model and Data Flow Model.

System Description: A digital MUX is a combinational circuit that selects one input out of
several inputs and directs it to a single output. The particular input section is controlled by a set of select inputs.

Logic Diagram:

Truth Table:
Select Inputs S1 0 0 1 1
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Output Y I0 I1 I2 I3

S0 0 1 0 1

VHDL CODE: (a) Behavioural Model

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux_4to1 is Port ( I0 : in std_logic; I1 : in std_logic; I2 : in std_logic;I3 : in std_logic; S0 : in std_logic; S1 : in std_logic; y : out std_logic); end mux_4to1; architecturemux_behavioral of mux_4to1 is begin process(I0,I1,I2,I3,S0,S1) begin if(S1='0' and S0='0') then y<=I0; elsif(S1='0' and S0='1') then y<=I1; elsif(S1='1' and S0='0') then y<=I1; elsif(S1='1' and S0='1') then y<=I1; end if; end process; endmux_behavioral;

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(b) Dataflow Model

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux_4to1 is Port ( I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic; S0 : in std_logic; S1 : in std_logic; y : out std_logic); end mux_4to1; architecturemux_dataflow of mux_4to1 is begin y<=I0 when S1='0' and S0='0' else I1 when S1='0' and S0='1' else I1 when S1='1' and S0='0' else I3; endmux_dataflow;

(c) Sturctural Model

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux_4to1 is Port ( I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic; S0 : in std_logic; S1 : in std_logic; y : out std_logic); end mux_4to1;

architecturemux_structure of mux_4to1 is component and3

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port(in1,in2,in3: in std_logic; out1: out std_logic); end component;

component or4 port(in4,in5,in6,in7: in std_logic; out2: std_logic); end component;

signalS0bar,S1bar,u,v,w,x,z: std_logic;

begin a0: and3 port map(I0,S1bar,S0bar,u); a1: and3 port map(I1,S1bar,S0,v); a2: and3 port map(I2,S1,S0bar,w); a3: and3 port map(I3,S1,S0,x); a4: or4 port map(u,v,w,x,y);

endmux_structure;

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OUTPUT: MUX4X1

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PROGRAM-3

Aim:Write a vhdl code for 2 to 4 decoder using structural , behavioral and Data Flow model System Description:
A decoder is a device which does the reverse operation of an encoder, undoing the encoding so that the original information can be retrieved. The same method used to encode is usually just reversed in order to decode. It is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines. In digital electronics, a decoder can take the form of a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes are different. e.g. n-to-2n, binary-coded decimal decoders. Decoding is necessary in applications such as data multiplexing, 7 segment display and memory address decoding.

Logic Diagram

TRUTH TABLE:

Enable X1 X0 Y0 Y1 Y2 Y3 1 1 1 1 0 0 0 1 1 x 0 1 0 1 x 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0

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VHDL Code: (a) Behavorial

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decoder_2_4 is Port ( X1,X0,Enable:in bit;Y:out bit_vector(0 to 3)); end decoder_2_4; architecture Behavioral of decoder_2_4 is begin process(X1,X0,Enable) variable Abar,Bbar:bit; begin X1bar:=not X1; X0bar:=not X0; if Enable='1' then Y(0)<=X0bar and X1bar; Y(1)<=X1bar and X0; Y(2)<=X1 and X0bar; Y(3)<=X1 and X0; else Y<="0000"; end if; end process; end Behavioral;

(B)Data Flow
library IEEE; use IEEE.STD_LOGIC_1164.ALL;

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use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decoder_2_4 is port (X1,X0 Enable : in std_logic ; Y : out std_logic_vector(3 downto 0) ); end decoder_2_4;

architecture df of decoder_2_4 is begin Y(0) <= Enable and (not X0 and not X1); Y(1) <= Enable and (X0 and not X1); Y(2) <= Enable and (not X0 and X1); Y(3) <= Enable and (X0 and X1); end df;

(C) Structural
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decoder_2_4 is port (X0,X1, en : in bit ; Y : out bit_vector(3 downto 0) ); end decoder_2_4;

architecture str of decoder_2_4 is

component INV
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port (In1 : in bit ; Out1 : out bit ); end component;

component AND3 port (In1, In2 , In3: in bit ; Out1 : out bit ); end component;

signal X1_sig, X0_sig : bit;

begin I0 : INV port map (X0, X0_sig); I1 : INV port map (X1, X1_sig); U3 : AND3 port map (X0_sig, X1_sig,en, Y(0) ); U4 : AND3 port map (X0, X1_sig,en, Y(1) ); U5 : AND3 port map (X0_sig, X1,en, Y(2) ); U6 : AND3 port map (X0, X1 ,en, Y(3) );

end architecture str;

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Output:DECODER2TO4

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PROGRAM-4

AIM:
Write down VHDL program for 1-bit comparator using Behavioural Model and Data Flow Model

SYSTEM DESCRIPTION:
A digital comparator or magnitude comparator is a hardware electronic device that takes two numbers as input in binary form and determine whether one number is greater than, less than or equal to the other number. Comparators are used in a central processing units (CPU) and microcontrollers. Examples of digital comparator include the CMOS 4063 and 4585 and the TTL 7485 and 74682-89. The analog equivalent of digital comparator is the voltage comparator. Many microcontrollers have analog comparators on some of their inputs that can be read or trigger an interrupt.

Logic Diagram:

TRUTH TABLE: A 0 0 1 1
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B 0 1 0 1

RESULT(0) 0 0 1 0

RESULT(1) 1 0 0 1

RESULT(2) 0 1 0 0

VHDL CODE (a)DATA FLOW

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity comparator_1_bit is Port ( A : in STD_LOGIC; B : in STD_LOGIC; RESULT : out STD_LOGIC_VECTOR(2 downto 0)); end comparator_1_bit; architecture dataflow of comparator_1_bit is begin RESULT<="100"when(A>B)else

"010"when(A=B)else

"001";

end dataflow;

(b)BEHAVIORAL
library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity comparator is Port ( A : in STD_LOGIC; B: in STD_LOGIC;

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RESULT : out STD_LOGIC_VECTOR(2 downto 0)); end comparator;

architectureBehavioral of comparator is

begin process(A,B)

begin if A>B then RESULT<=100; elsif A<B then RESULT<=001; elsif A=B then RESULT <=010; end if; end process; endBehavioral;

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OUTPUT: 1 BIT COMPARATOR

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PROGRAM-5 Aim: Write a VHDL programme for a 4bit comparator using behavioural model

System Description:
A digital comparator or magnitude comparator is a hardware circuit that takes two numbers as input in binary form and determines whether one number is equal to , less than or greater than the other number. Comparator are used in CPU and microcontroller. Examples of digital comparator include CMOS 4063 and 4858 and TTL 7485 and 74682-89 The analog equivalent of digital comparator is the voltage comparator. Many microcontrollers have analog comparators on some of their inputs that can be read or trigger an interrupt.

Logic Diagram:

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VHDL CODE:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity comp4 is port ( a,b: in bit_vector(3 downto 0); -- deines a vector of 4 values a3 to a0, b3 to b0 aeqb,agtb,altb: end comp4; out bit);

architecturebehavioral of comp4 is -- the architecture is being described by its behavior begin comp: process (a,b) begin if a=b then aeqb<= '1'; agtb<='0'; altb<='0'; else if a<b then aeqb<= '0'; agtb<='0'; altb<='1'; else aeqb<= '0'; agtb<='1'; altb<='0'; end if; end if; end process comp; endbehavioral; -- comp is an optional label identifying the process

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Output:4 BIT COMPAROTOR

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PROGRAM-6 AIM:
Write down VHDL program for 3-bit Binary to gray Code Converter using Behavioural Model,and Data Flow Model

SYSTEM DESCRIPTION:
The reflected binary code, also known as gray code after frank gray, is a binary numerical system where two successive values differ in only one bit.It is a non-weighted code. The reflected binary system was originally designed to prevent spurious output from electromechanical switches. Today, Gray codes are widely used to facilitate error correction in digital communication such as digital terrestrial and some cable TV systems.

LOGIC DIAGRAM:

TRUTH TABLE: B(2) 0 0 0 0 1 1 1 1 B(1) 0 0 1 1 0 0 1 1 B(0) 0 1 0 1 0 1 0 1 G(2) 0 0 0 0 1 1 1 1 G(1) 0 0 1 1 0 0 1 1 G(0) 0 1 0 1 0 1 0 1

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VHDL CODE

(a) BEHAVIORAL
library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entitybinary_to_gray is Port ( b0 : in STD_LOGIC; b1 : in STD_LOGIC; b2 : in STD_LOGIC; b3 : in STD_LOGIC; g0 : out STD_LOGIC; g1 : out STD_LOGIC; g2 : out STD_LOGIC; g3: out STD_LOGIC ); endbinary_to_gray;

architectureBehavioral of binary_to_gray is begin g3<=b3; g2<=(b3 xor b2); g1<=(b2 xor b1); g0<=(b1 xor b0); endBehavioral;

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(b)DATAFLOW

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entitybinary_to_gray is Port ( B0 : in STD_LOGIC; B1 : in STD_LOGIC; B2: in STD_LOGIC; G0: out STD_LOGIC; G1: out STD_LOGIC; G2: out STD_LOGIC); endbinary_to_gray;

architecture dataflow of binary_to_gray is begin G2<=B2; G1<=B2 XOR B1; G0<=B1 XOR B0; end dataflow;

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OUTPUT: BINARY TO GRAY

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PROGRAM-7

Aim: Write down VHDL program for BCD to Seven Segment Decoder using Behavioral
Model, Structural Model and Data Flow Model.

System Description: A seven segment display is a form of electronic display device for
displaying decimal numerical that is an alternative to the more complex dot matrix displays. Seven-segment displays are widely used in digital clocks, electronic meters, and other electronic devices for displaying numerical information. The idea of the seven segment display is quite old. In 1910, for example, seven segment display illuminated by incandescent bulbs were used on a power plant boiler room signal panel.

Truth Table:
Bcd(3) Bcd(2) Bcd(1) Bcd(0) 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 A 1 0 1 1 0 1 1 1 1 1 B 1 1 1 1 1 0 0 1 1 1 C 1 1 0 1 1 1 1 1 1 1 D 1 0 1 1 0 1 1 0 1 1 E 1 0 1 0 0 0 1 0 1 0 F 1 0 0 0 1 1 1 0 1 1 G 0 0 1 1 1 1 0 0 1 1

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VHDL CODE: (a) Behavioral Model:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity seven_segment_display is Port ( clk : in std_logic; bcd : in std_logic_vector;(3 downto 0); segment7 : out std_logic(6 downto 0) ); end seven_segment_display;

architecture Behavioral of seven_segment_display is begin process (clk,bcd) begin if(clkevent and clk=1) then case bcd is when 0000=>segment7<=1111110; when 0001=>segment7<=0110000; when 0010=>segment7<=1101101; when 0011=>segment7<=1111001; when 0100=>segment7<=0110011; when 0101=>segment7<=1011011;

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when 0110=>segment7<=1011111; when 0111=>segment7<=1110000; when 1000=>segment7<=1111111; when 1001=>segment7<=1111011; when others =>segment7<=0000000; end case; end if; end process; end Behavioral;

(b) Dataflow Model:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

entity seven_seg_decoder is Port( bcd: in std_logic_vector(0 to 3); led: out std_logic_vector(0 to 6)); end seven_seg_decoder;

architecture seven_dataflow of seven_seg_decoder is

begin led<=1111110 when bcd=0000 else 0110000 when bcd=0001 else 1101101 when bcd=0010 else

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1111001 when bcd=0011 else 0110011 when bcd=0100 else 1011011 when bcd=0110 else 1110000 when bcd=0111 else 1111111 when bcd=1000 else 1111011 when bcd=1001 ; end seven_dataflow;

(c) Stuctural Model:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; entity seven_segment_decoder is Port(bcd: in std_logic_vector(0 to 3); led: out std_logic_vector(0 to 6)); end seven_segment_decoder;

architecture seven_structure of seven_segment_decoder is component decoder port(input: in bit_vector (0 to 3); output:out bit_vector(0 to 6)); end component

begin dec1: decoder port map(bcd, led); end seven_structure;

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OUTPUT: SEVEN SEGMENT

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PROGRAM-8

AIM: Write down VHDL program SR flip flop and JK flip flop SYSTEM DESCRIPTION:
In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistablemultivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.

LOGIC CIRCUITS:

JK Flip Flop Timing Diagram

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VHDL Code:

(a)

SR Flip Flop

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;

ENTITY sr_ff IS port(S, R,pr,cr,clk:in std_logic;q,qbar:inoutstd_logic);

END ENTITY sr_ff;

ARCHITECTURE behavi OF sr_ff IS BEGIN

process(pr,clk,cr,s,r) begin if(pr='0') then q<='1'; qbar<='0'; elsif(cr='0')then q<='0'; qbar<='1'; elsif(clk='1' and clk'event) then if(S='0' and R='0') then q<=q; qbar<=qbar; elsif(s='0' and r='1') then q<='0'; qbar<='1';
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elsif(S='1' and R='0') then q<='1'; qbar<='1'; end if; end if; end process; END ARCHITECTURE behavi;

(b). JK Flip Flop

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;

ENTITY jk IS port(J, K,pr,clr,clk: in std_logic; Q, Qbar:outstd_logic); END ENTITY jk; -ARCHITECTURE struct OF jk IS signalqss: std_logic;

BEGIN process(J,K,clk,pr,clr) begin if(clr='0') then qss<='0';

elsif (pr='0') then qss<='1';

elsif(clk='1' and clk'event)then if (J='0' and K='0') then

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qss<=qss; elsif(J='0' and K='1') then qss<='0'; elsif(J='0' and K='1')then qss<='1'; elsif(J='1' and K='1')then qss<=not qss; end if; end if; end process; Q<=qss; Qbar<=not qss;

END ARCHITECTURE struct;

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OUTPUT:

SR Flip Flop

JK Flip Flop

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PROGRAM-9

AIM:
Write down VHDL program for bi-directional Shift Register

SYSTEM DESCRIPTION:
In digital circuits, a shift register is a cascade of flip flops, sharing the same clock, in which the output of each flip-flop is connected to the "data" input of the next flip-flop in the chain, resulting in a circuit that shifts by one position the "bit array" stored in it, shifting in the data present at its input and shifting out the last bit in the array, at each transition of the clock input. More generally, a shift register may be multidimensional, such that its "data in" and stage outputs are themselves bit arrays: this is implemented simply by running several shift registers of the same bit-length in parallel. A bidirectional shift register is one in which the data can be shifted either left or right. It can be implemented by using gate logic that enables the transfer of a data bit from one stage to the next stage to the right or to the left, depending on the level of control line.

LOGIC DIAGRAM:

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VHDL Code:

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;

ENTITY bidirect IS Port(M,dr,pr,clr,clk: in std_logic;y:outstd_logic); END ENTITY bidirect;

-ARCHITECTURE shift OF bidirect IS signal s1,s2,s3:std_logic; BEGIN process (pr,dr,M,clr,clk) begin if (pr='0')then s1<='1'; s2<='1'; s3<='1'; y<='1'; elsif (clr='0') then s1<='0'; s2<='0'; s3<='0'; y<='0'; elsif(clk='1' and clk'event) then if(M='0') then s1<=dr; s2<=s1; s3<=s2;
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y<=s3; elsif(M='1') then s3<=dr; s2<=s3; s1<=s2; y<=s1; end if ; end if; end process;

END ARCHITECTURE shift;

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OUTPUT : Bi -SHIFT REGISTER

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PROGRAM-10

AIM:
Write down VHDL program for 4 bit UP/DOWN Counter

SYSTEM DESCRIPTION:
In digital logic and computing, a counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock signal.
A counter that can change state in either direction, under the control of an up or down selector input, is known as an up/down counter. When the selector is in the up state, the counter increments its value. When the selector is in the down state, the counter decrements the count.

LOGIC DIAGRAM:

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VHDL Code:

Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entityupdowncount is port(reset,c,clk:in std_logic; Q:inoutstd_logic_vector(3 downto 0)); endupdowncount; architectureBehavioral of updowncount is begin process(reset,c,clk,s) begin if reset='1' then Q<="0000"; elsif c='1' and rising_edge(clk) then Q<=Q+1; elsif c='0' and rising_edge(clk) then Q<=Q-1; end if; end process; endBehavioral ;

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OUTPUT: UP/DOWN COUNTER

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