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W H I T E

PA P E R
Naga Chandrashekar,

Engineering Manager, Multicore Voice, Networking & Video Infrastructure

Ted George,
Director, Applications & Platform Software Testing Communications Infrastructure & Multicore

Pekka Varis,
CTO, Multicore and Media Infrastructure Texas Instruments

Network coprocessors are altering the makeup of gateway systems


The evolution of the media gateway
Media gateways, with DSPs as their key processing engines, were instrumental as telecommunications service providers introduced voice over IP (VoIP) services. Typically, these gateways would aggregate voice TDM trafc for transport over ATM or managed IP-based backbones. The DSPs in the media gateways handled the speech codecs (coder/decoders), signal-processing algorithms and various accelerators. Moreover, DSPs performed all of the analog-oriented processing like echo cancellation. The media gateway DSPs processed packetized voice and forwarded this trafc over a memory-mapped host port interface to the host processor where further protocol processing would take place. Furthermore, the gateway would handle network transmit and receive functions. Depending on the type of backbone circuit, packetized data was aggregated over ATM-VC or an IP address. The point of aggregation could be a network processor like a media gateway or some block of hardware logic in a host. Wherever located, this function either aggregated multimedia payloads for transport over larger backbone facilities or distributed received network data to multiple devices/end points. Over time, advancements in media gateways have been driven by increasingly more powerful DSPs, particularly TI DSPs. In addition to accelerating processing speeds, DSP cores have evolved from a 16-bit dual multiply/accumulate (MAC) TMS320C55x core to the

Overview
Digital signal processors (DSPs) have played an integral role in the transition of the telecommunications network from an analogdominated network exclusively dedicated to voice communications to a modern digital multimedia network. In recent years, the networks media gateways and the DSPs that are at their core have taken several new steps in their evolution. This white paper examines the evolution of media gateways, the role that TIs DSP technology has played in this and how the emergence of the network coprocessor (NetCP) is currently altering the makeup of next-generation media gateways. In particular, the integration of previously disparate processing elements such as Ethernet switching, packet and security acceleration subsystems and others into one cohesive processing architecture is explained relative to how this phenomenon is enabling the seamless integration of legacy architectures with newer innovations.

DSPs

DSP Aggregation Ethernet Switch Packet Aggregation Logic

DSP Aggregation

DSPs

Figure 1. Historically, trafc aggregation hardware has been separated from the processing capabilities of media gateways.

Texas Instruments

TMS320C66x core with its eight-way, very long instruction word and 128-bit SIMD MAC processing per clock cycle. Current DSPs are capable of processing eight to ten times the processing load over the previous generation of processing cores. In addition, advanced silicon geometries and system-on-chip (SoC) techniques have made possible the integration of networking aggregation capabilities within a single DSP device. For example, the KeyStone family of multicore DSPs from TI provides aggregation and packet header processing in hardware in a single DSP. Moreover, rst-generation integrated multicore DSPs like the TI C6472 offered improvements by basically integrating multiple single cores in an SoC. Processing advancements were achieved because multiple DSP cores shared program memory and an external memory controller, and by providing a logical instance of external I/O for each core. The KeyStone network coprocessor (NetCP) has taken integration further. Now, memory sharing is not limited to program data and the devices smart I/O can abstract the chips architecture, such as the number of cores, from the board and system level.

Consolidating the aggregation function

Previously, general-purpose processing architectures, such as those based on PowerPC and MIPS cores, also performed aggregation functions. Unfortunately, the costs of such systems would ratchet upward as these system tried to keep up with increasing bandwidth and processing demands. Future-proong was another issue that drove up costs as these systems were forced to adapt to rapidly changing communications protocols. But as the network interface transitioned from a heterogeneous mix of layer 2 protocols that included TDM, ATM, Frame Relay and others to an exclusively IP/Ethernet network, the processing needed for complicated transport interfaces like ATM AAL2 and others was no longer needed. Network transport focused on Ethernet and IP. In addition, the much higher processing capabilities of DSPs like TIs C66x cores along with their NetCP subsystem provides the basis for signicantly accelerating packet processing in hardware. This removes the need for distinct devices to perform aggregation since it can be integrated into a multicore DSP, reducing system costs signicantly.

c66x c66x c66x c66x C66x


NAVIGATOR

NAVIGATOR

c66x c66x c66x c66x C66x

NFUCP

Ethernet Switch NFUCP

c66x c66x c66x c66x C66x

Figure 2. The NetCP facilitates the integration of more functionality and eliminates separate hardware from the system.

Network coprocessors are altering the makeup of gateway systems

NAVIGATOR

NFUCP

November 2011

Texas Instruments 3

What is a NetCP?

NetCP is a hardware-based accelerator that processes data packets. Its specialty is processing Ethernet packets. Within the KeyStone architecture, NetCP features two Gigabit Ethernet processing modules that transmit and receive packets from any IEEE 802.3-compliant network. Complementing NetCP in the KeyStone architecture is the Multicore Navigator, a subsystem consisting of many hardware-assisted queues and a packet-oriented scatter/gather direct memory access (DMA) infrastructure. Multicore Navigator functions as the communication link between the C66x DSP cores and the NetCPs hardware acceleration subsystem with its packet and security accelerators. This architecture abstracts the I/O at the subsystem level so that the number of devices and DSP cores can be more efciently scaled to higher densities or additional applications can be more effectively deployed on the system. That is, the scaling of devices and cores is decoupled from the systems I/O subsystem and vice versa. In addition, scalability is enhanced because NetCP allows the system to route packets among multiple cores based entirely on standard header information such as the UDP port.

NetCP packet accelerator


NetCPs packet accelerator speeds the processing of packets in a number of ways. First, it performs packet classication operations (like header matching) and packet modication operations (like checksum generation) in hardware. In addition, NetCP accelerates packet processing by functioning as a communications bridge. That is, the NetCP can receive packets directly from the Ethernet modules, or from a C66x core or a supported peripheral such as Serial RapidIO by way of the packet DMA. In this way, NetCP bridges two different physical interfaces while network connections are managed by the application running on the C66x DSP. This provides an efcient fast path, zero copy architecture for packet processing while minimizing the need for the C66x DSP to perform header manipulation. NetCP reduces system cost by consolidating functionality into fewer components. It is also able to overcome the challenge of adapting to existing network front end architectures at the chassis level by providing custom packet header processing. Central to the NetCPs programmable packet header processing engine is a universal header processing accelerator that can be easily customized to support various system architectures, including proprietary protocols. The universal nature of the NetCPs packet header processing enables a wide range of applications from media gateways to wireless base stations, radio network controllers, videoon-demand servers and any platform that requires data aggregation and routing based on protocol header information.

NetCP security accelerator


The NetCPs hardware-based security accelerator adds value to gateways that require bearer ciphering by ofoading encryption, decryption and authentication functions for IPSEC, SRTP, 3GPP and wireless air cipher algorithms from the host systems DSP. This accelerates not only the systems security measures but also its overall throughput. In particular, accelerating IPSEC has emerged as a critical need because the ubiquitous

Network coprocessors are altering the makeup of gateway systems

November 2011

Texas Instruments

adoption of IP/Ethernet has made IPSEC practically universal. For example, 3GPP has made IPSEC mandatory in LTE networks between the base station (eNode B) and the core network. The NetCP security accelerator provides excellent scalability to higher density systems and wider applicability across a broad range of applications. NetCPs security accelerator subsystem also includes true random number generation and public key acceleration to assist and speed up the initialization of network connections.

Performance effects

Because the NetCP subsystem is tightly integrated with the programmable hardware queue infrastructure of the Multicore Navigator, the two can be effectively and quickly deployed to implement various types of performance-enhancing functions such as quality of service, data priority, trafc policing and bandwidth management. Moreover, in multimedia applications, NetCP and Multicore Navigator can perform the constant bit rate operations required by video transcoding applications. Figure 3 below illustrates how efciently NetCP is able to ofoad processing from the host systems processors and accelerate the throughput of the system. As the processing load on the system increases, the processing of ofoaded functions by the NetCP increases accordingly. But, at the same time, the processing overhead required by the host processors is kept to a minimum. In this way, the hosts processor capacity is retained for application processing, ensuring high throughput for the system.

Software interfaces

A hardware access library and low-level drivers for NetCP are available through TIs multicore software development kit (MCSDK). These simplify the integration of the NetCP subsystem with various operating systems

100%

Packet throughput/loading at NFUCP Interface. Measured with various packet size, packet rate using typical core network gateway scenario.

50%
CPU cycles for packet transfer and context identification. Packet head processing, checksum calculation offloaded to NFUCP hardware. Close to 90% of CPU cycles with 100% packet loading available for application software.

10%

Figure 3. NetCP allows CPU utilization to stay low even as network throughput hits 100 percent.

Network coprocessors are altering the makeup of gateway systems

November 2011

Texas Instruments 5

Linux Control Application (ARM, C66x Linux_MCSDK) Openssl + OCF engine

OCF SA Glue Driver User Mode NFUCP Drivers

Data Path BIOS C66x MCSDK Application

Linux Kernel
Data Path Multicore Navigator

Control Path

NFUCP
Figure 4. NetCP interfaces to SYS/BIOS and Linux operating systems

(OSs) and rmware implementation, including TI SYS/BIOS, Linux or other user-specic OSs. Figure4 shows how NetCP interacts with the SYS/BIOS and Linux OSs.

Conclusion

The emergence of the network coprocessor such as NetCP, which is integral to the KeyStone architecture for its new DSP cores, marks another transition in the makeup of the gateway systems that funnel trafc across predominantly Ethernet/IP backbone networks. NetCPs are able to reduce the costs associated with gateways by reducing chip counts and consolidating functionality onto fewer devices. At the same time, a gateway with a NetCP will see a boost in its throughput because of the NetCP sophisticated hardware accelerators. These accelerators can also ofoad the processing load from the systems application processors, freeing up processing capabilities to accommodate greater trafc or enhanced functionality. For more information on TIs network coprocessors, the KeyStone architecture, or the C66x DSP cores, visit www.ti.com/c66multicore

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2011 Texas Instruments Incorporated

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