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4 bit Flash ADC with Low Power Operation

Prashuk Jain , Rahul Gawande and Shivam Dubey Indian Institute of Science Bangalore, India
Abstract: In this paper we present a 4 bit Flash type ADC design capable of 2 GSPS sampling speed while dissipating as low as 600 W using the 0.13m CMOS technology. ADC can work with VDD =+1.2V and VSS=-0.4V supply rails. Index Terms High speed comparator, low power ADC, Flash analog-digital convertor, 0.13m CMOS

I. INTRODUCTION HE Flash type ADCs are also known as parallel convertor and are also the fastest, as they use parallel comparators each of them compare the input voltage against the reference quantization voltages. Thus, the Flash type analog to digital convertor can generate the results in a clock cycle. These ADCs find applications where signals with very large bandwidth needs to be digitize such as hard disk, radars, sampling oscilloscope, very large BW communication systems etc. However, owing to large number of comparator requirement i.e. (2n 1) comparators for n-bit flash ADC. Size and the power requirement is very large which limits the maximum resolution of these ADCs. Also, since every comparator adds to the capacitance which has to be driven by the buffer amplifier, at such high speed of operation it also constrains the maximum comparator count, thus the resolution. In this work we have designed a 4 bit Flash ADC to operate at 2GSPS to sample a 1V peak to peak input with respect to . ground while consuming very low power per sample. The low power operation is possible due to low power rail voltage operability of the circuit which is made possible by designing preamplifier circuit with only 3 transistors between VDD and VSS and the track and latch comparator with only 4 transistors between VDD and Gnd. Thus, allowing all transistors to be biased in the saturation for maximum gain even at low supply voltage. Due to all these measure we have reduced the power requirement of the comparators and digital back end till 1-n encoder (section II D) to less than 600-W. .

ladder of 16 similar resistances. The outputs of the comparators are connected to the 1 bit bubble error corrector digital circuit, to give out the proper thermometer code, this thermometer code is then encoded into 1-n code using 1-n encoder digital circuit and finally this 1-n code is encoded to 4 bit PCM output. The comparator is divided into two circuits, first the preamplifier followed by the track and latch circuit. The preamplifier circuit helps reduce the effect of the offset voltage [5] of the latch while also lowering the influence of the kick-back noise [8] due to latching operation of the track and latch.

Fig. 1 ADC architecture B. PREAMPLIFIER CIRCUIT The preamplifier circuit in fig. 2 must have high gain so as to reduce the effect of the offset of the track and latch circuit. In order to achieve this high gain NMOS differential amplifier configuration with PMOS M1 and M4 active loads biased as constant current source is used in the circuit. A common mode feedback circuit formed by transistor M6 M10 is used to generate the bias voltages for these PMOS transistor in order set the common mode voltage of the preamp out near to the voltage given at gate of M9 when Vin is equal to the Vref. This also allows the common mode voltage at the input of all the track and latch in the next stage to be same for all the comparators, thus design of the track and latch circuit dont

II. STRUCTURE AND OPERATION OF THE CIRCUIT A. ARCHITECTURE OF THE ADC The architecture of the ADC in fig. 1 consists of high speed comparator array of 15 comparators each comparing input to the respective reference voltages generated using the resistive

2 have to tackle the much of common mode swing near input of change of voltage at the output as some of the differential current by the latch network will be cancelled by the differential current of the amplifier. This is more problematic for high frequency input signal which can change to large voltages very quickly. After the positive clock cycle is over as n_clk makes transition from high to low the reset clock signal r_clk is made high for small duration turning ON M12 which shorts the von and vop output terminals and brings them to a common voltage very quickly.

voltage Vin and Vref across the comparators. Fig. 2 Preamplifier

The preamplifier requires negative supply of VSS equal to -0.4 in order to keep the M2 and M3 in the saturation when the Vref and Vin are close to ground voltage i.e. for the proper working of preamplifiers comparing the Vref < 0.4V. Fig. 3 Track and latch circuit C. TRACK AND LATCH CIRCUIT The track and latch circuit shown in fig.3 is made by connecting differential amplifier with diode connected PMOS load formed by transistors M1-M4 and M9 in parallel with the regenerative latch circuit formed by transistor M5-M8. The NMOS M10 and PMOS M11 transistors isolate the latch network during the track operation i.e. when the clock signal n_clk is low and complementary clock signal n_nclk is high. The NMOS M12 is for shorting the output nodes vop and von and bring the output to a common voltage. When the clock signal n_clk and r_clk (fig.8) is low the latch network is isolated from the power supply and the output nodes von and vop are driven to differential voltages by the differential amplifier network. When the n_clk goes high the regenerative latch network comes into the circuit and latches the differential output towards VDD or goround. The transistors in the latch network are bigger than the transistors in the differential amplifier network. So, once the latching circuit is ON then even if the input differential voltage (vp vn) in the fig. 3, the direction of the latching at the output is not changed. Therefore, this circuit can work without a track and hold circuit in the ADC. Although if the inversion takes place very quickly after n_clk goes high then it can reduce the initial rate D. DIGITAL BACK END The output of the track and latch taken from the von (shown in fig. 3) only and provided to a inverting CMOS buffer amplifier. This inverting buffer isolated the further digital circuits from the comparator. The output of the comparators Ci is temperature coded i.e. all comparator comparing with the reference voltage below the input signal provides high output while all above provides low output, but due to clock skewness or noise the output may not be proper thermometer coded. This is called bubble error. The logic to correct 1 bit bubble error correction is given by (1). The logic output is low if more than 2 comparators gives high output. = 1 + +1 + 1 +1 (1)

The bubble error corrected output is provided to the 1-n encoder which high output only at i-th output bit position of ith bit of bubble error corrector output is low and (i+1)th bit of bubble error corrector is high. The output logic for each i- th bit position is given by the logic (2). 1 , = . +1 (2)

The CMOS implementation of the above logic (1),(2) are shown in fig. 4, fig. 5 respectively.

Fig. 6 Transfer characteristics of preamplifier

Fig. 4 1-bit bubble error corrector logic

Fig. 7 Output of track and latch circuit when 100MHz sin wave provided as differential input Simulation of track and latch circuit is shown in fig. 7, in the figure waveform portion enclosed by the red circle is shows vop and von output returning to a common mode point when r_clk is high . Just after the r_ckl is made low the output increases differentially according to the magnitude and polarity of differential input. After the n_clk becomes high the differential output latches to Vdd and ground.

Fig. 5 1-n encoder logic cell The final digital 4-bit PCM code output will be generated by the encoder block which is written in verilog-A.

III. SIMULATION RESULTS Simulation of the ADC is performed on the Mentor Graphics ELDO simulation tool. The circuits were designed using 13-m CMOS technology high speed MOS transistors. The transfer characteristics of the preamplifier circuit is show in the fig. 6, in the characteristics plot it can be seen that crossover voltage of the output is equal to the common mode voltage set by voltage vcmo in the common mode feedback network (fig. 2).

Fig. 8 Different Clock signal

4 [3] J.N.Babanehzad and R.Gregorian, A programmable gain/loss circuit,IEEE J. Solid- State Circuits, vol.SC-22, pp. 1082-1090, Dec. 1987. [4] G.Yongheng, C. Wei, L. Tiejun and W.Zongmin, A novel 1GSPS low offset comparator for high speed ADC,Fifth International Joint Conference INC,IMS and IDC, pp. 12511254, 2009. [5] B.Razavi and B.A.Wooley,Design techniques for highspeed, high-resolution comparators, IEEE J. Solid- State Circuits, vol.27, no.12, pp. 1916-1926, Dec. 1992. [6] Y.Jung, S.Lee, J.Chae and G.C.Temes, Low-power and low-offset comparator using latch load,IEEE Electronics Letters, vol.47, pp.167-168, 2011. [7] T.C.Hsiao, N.A.Kistler and J.C.S.Woo,Modeling the I-V characteristics of fully depleted submicrometer SOI MOSFETs,IEEE Electon Device Letters, vol.15,pp.4547,1994. [8] P.M.Figueiredo, J.C.Vital,Kickback noise reduction techniques for CMOS latched comparators,IEEE Trans. On Circuits and Systems, vol.53,pp.541-545,2006. [9] B.Razavi, Design of Analog CMOS Integrated Circuits.McGraw-Hill,2000. [10] V.Srinivas, S.Pavan, A.Lachhwani and N.Sasidhar,A distortion compensating flash analog to digital conversion technique,IEEE J. Solid State Circuits ,vol.41,pp.1959-1969, Sep.2006.

Fig. 9 Showing the 1-Vp-p sin wave of 25 MHz sampled by ADC at 2 GSPS

Fig. 10 Showing the 1-Vp-p sin wave of 500 MHz sampled by ADC at 2 GSPS Complete Flash ADC was simulated successfully up to 2GSPS. To check the output of ADC, the output PCM bits was again converted into analog voltage using 4-bit ideal DAC written using Verilog-A. The output of DAC is plotted with the input sin waves of 25MHz and 500MHz shown in fig. 9, 10 respectively. In fig. 9 the horizontal lines are the 15 reference voltage. IV. CONCLUSION This paper described a high-speed comparator array for Flash-type ADCs operating at a of 1.2V and = -0.4V power supply that can be fabricated with an advanced digital CMOS process technology having power. To verify the capabilities of the comparator array, a 4-bit Flash-type ADC was implemented. The 4-bit ADC with the comparator array achieves 2 GSample/s at a medium supply voltage of 1.2 by using 0.13-um generic CMOS technology. The track and latch circuit which is used has an offset of 100uV.

REFERENCES [1] H.Okada, Y.Hashimoto, K.Sakata, T.Tsukada, and K.Ishibashi,Offset calibrating comparator array for 1.2-V,6bit,4-Gsamples/s flash ADCs using 0.13-um generic CMOS technology, IEEE Solid State Circuits Conference, pp. 711714, 2003. [2] M.J.M Pelgrom, AAD C.J.Duinmaijer and A.P.G.Welbers, Matching properties of MOS transistors, IEEE J. Solid- State Circuits, vol. 24, pp.1433-1439, 1989.