Contemporary Logic Design Finite State Machine Design

Chapter #8: Finite State Machine Design 8.3 Alternative State Machine Representations 8.4 Mealy and Moore Machines Design

R.H. Katz Transparency No. 15-1

8.3 Alternative State Machine Representations Why State Diagrams Are Not Enough

Contemporary Logic Design Finite State Machine Design

Not flexible enough for describing very complex finite state machines Not suitable for gradual refinement of finite state machine Do not obviously describe an algorithm: that is, well specified sequence of actions based on input data algorithm = sequencing + data manipulation separation of control and data

Gradual shift towards program-like representations: Algorithmic State Machine (ASM) Notation Hardware Description Languages (e.g., VHDL)

R.H. Katz Transparency No. 15-2

Alternative State Machine Representations Algorithmic State Machine (ASM) Notation Three Primitive Elements: State Box Decision Box Output Box State Machine in one state block per state time Single Entry Point Unambiguous Exit Path for each combination of inputs Outputs asserted high (.H) or low (.L); Immediate (I) or delayed til next clock
State Entry Path

Contemporary Logic Design Finite State Machine Design

State Code

*
State Name State Output List T

***
State Box

Condition

ASM Block

Condition Box Conditional Output List

Output Box

Exits to other ASM Blocks

R.H. Katz Transparency No. 15-3

Alternative State Machine Representations ASM Notation Condition Boxes: Ordering has no effect on final outcome Equivalent ASM charts: A exits to B on (I0 I1) else exit to C
A 010 A

Contemporary Logic Design Finite State Machine Design

010

I0 T I1 T B

F T

I1

F I0

T C B C

R.H. Katz Transparency No. 15-4

Alternative State Machine Representations Example: Odd Parity Checker Input X, Output Z
Even 0

Contemporary Logic Design Finite State Machine Design

Nothing in output list implies Z not asserted Z asserted in State Odd

X T Odd H.Z F T 1 F

Trace Tracepaths pathsto toderive derive state transition state transitiontables tables

R.H. Katz Transparency No. 15-5

Alternative State Machine Representations

Contemporary Logic Design Finite State Machine Design

Symbolic State Table: Present Next Input State State Output F Even Even T Even Odd F A Odd Odd T A Odd Even Encoded State Table: Present Next Input State State Output 0 0 0 0 1 0 0 1 0 1 1 1 1 1 1 0

A - asserted

R.H. Katz Transparency No. 15-6

Alternative State Machine Representations ASM Chart for Vending Machine

Contemporary Logic Design Finite State Machine Design

00

10

10

D F F N T

D F

N T

01

15 H.Open

11

N F F D

Reset T

0
R.H. Katz Transparency No. 15-7

8.4 Moore and Mealy Machine Design Procedure Definitions

Contemporary Logic Design Finite State Machine Design

Mealy Machine
Xi Inputs Combinational Logic for Outputs and Next State Zk Outputs

Outputs depend on state AND inputs Input change causes an immediate output change Asynchronous outputs

State Register

Clock

State Feedback

State Register Xi Inputs Combinational Logic for Next State (Flip-flop Inputs) Clock Comb. Logic for Outputs Zk Outputs

Moore Machine Outputs are function solely of the current state Outputs change synchronously with state changes
R.H. Katz Transparency No. 15-8

state feedback

Moore and Mealy Machines

Contemporary Logic Design Finite State Machine Design

State Diagram Equivalents for Vending Machine FSM Moore Machine

N D + Reset Reset 0 [0] Reset 5 ND [0] N 10 D [0] N+D 15 15 [1] Reset Reset/1 ND D/1 N D/0 N+D/1 N/0 10 D N D/0 5 D/0 N Reset/0 N/0 Reset/0 0 (N D + Reset)/0

Mealy Machine

Outputs are associated with State

Outputs are associated with Transitions

R.H. Katz Transparency No. 15-9

Moore and Mealy Machines Ex. FSM asserts the single output whenever its input string has at least two 1s in sequence.
Moore
0

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States vs. Transitions

Mealy
0 0/0

Same I/O behavior Different # of states Equivalent ASM Charts

S0 00 S0 0

0 [0] 0 1 [0] 1 2 [1] 1 1 0 0/0

1/0 1 1/1

IN S1 01

F
S1

IN

F
1

Mealy Machine typically has fewer states than Moore Machine for same output sequence

IN

F
10

IN

T
S2 H.OUT

T
H.OUT

IN

T MEALY R.H. Katz Transparency No. 15-10

MOORE

Moore and Mealy Machines Timing Behavior of Moore Machines Ex. 1 -- Reverse engineer the Moore Machine
X X \B J Q C KR Q FFa Clk \Reset A \A

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Input X Output Z State A, B Z=B Master-Slave J-K Flip Flops

X X \A

J Q C KR Q FFb \Reset

Z \B

Two Techniques for Reverse Engineering: Ad Hoc: Try input combinations to derive transition table Formal: Derive transition by analyzing the circuit
R.H. Katz Transparency No. 15-11

Moore and Mealy Machines Ad Hoc Reverse Engineering

Contemporary Logic Design Finite State Machine Design

Behavior in response to input sequence 1 0 1 0 1 0:

100 X Clk A B/Z \Reset Reset X = 1 X=0 X=1 X=0 X=1 X=0 X=0 AB = 00 AB = 00 AB = 11 AB = 11 AB = 10 AB = 10 AB = 01 AB = 00

Partially Derived State Transition Table

A B 0 0 0 1 1 0 1 1

Signal tracing is acceptable for small FSM, but becomes untraceble for more complex FSM.

X 0 1 0 1 0 1 0 1

A+ ? 1 0 ? 1 0 1 1

B+ ? 1 0 ? 0 1 1 0

Z 0 0 1 1 0 0 1 1

R.H. Katz Transparency No. 15-12

Moore and Mealy Machines Formal Reverse Engineering

Contemporary Logic Design Finite State Machine Design

Derive transition table from next state and output combinational functions presented to the flipflops! Ja = X Jb = X Ka = X B Kb = X xor A Z=B

FF excitation equations for J-K flipflop: Q+ = JQ + KQ A+ = Ja A + Ka A = X A + (X + B) A B+ = Jb B + Kb B = X B + (X A + X A) B Next State K-Maps:

A+

State 00, Input 0 -> State 00 State 01, Input 1 -> State 11

B+

R.H. Katz Transparency No. 15-13

Moore and Mealy Machines Finite State Machine Design Complete ASM Chart for the Mystery Moore Machine

Contemporary Logic Design

S0

00

S3 H.Z

11

X S1 H.Z 01

1 1 S2

X 10

Note: All Outputs Associated With State Boxes No Separate Output Boxes Intrinsic in Moore Machines

R.H. Katz Transparency No. 15-14

Moore and Mealy Machines Ex. 2 -- Reverse Engineering a Mealy Machine One D flip-flop and one master/slave J-K flip flop
Clk A \A R Q \Reset \A X

Contemporary Logic Design Finite State Machine Design

D DA C

\X

J C K

Q R Q \Reset

B \B

A X B \X

DA

\X B Z X A

Input X, Output Z, State A, B State register consists of D FF and J-K FF

R.H. Katz Transparency No. 15-15

Moore and Mealy Machine Ad Hoc Method Signal Trace of Input Sequence 101011:
100 X Clk A B Z \Reset Reset AB =00 Z =0 X =1 AB =00 Z =0 X =0 AB =00 Z =0 X =1 AB =01 Z =0 X =0 AB =11 Z=1 X =1 AB =10 Z =1

Contemporary Logic Design Finite State Machine Design

Note glitches in Z! Outputs valid at following falling clock edge

X =1 AB =01 Z =0

A B 0 0

Partially completed state transition table based on the signal trace

0 1 1 0 1 1

X 0 1 0 1 0 1 0 1

A+ 0 0 ? 1 ? 0 1 ?

B+ 1 0 ? 1 ? 1 0 ?

Z 0 0 ? 0 ? 1 1 ?

R.H. Katz Transparency No. 15-16

Moore and Mealy Machines Formal Method A+ = B (A + X) = A B + B X B+ = Jb B + Kb B = (A xor X) B + X B =ABX + ABX + BX Z =AX + BX

Contemporary Logic Design Finite State Machine Design

A+

Missing Transitions and Outputs: State 01, Input 0 -> State 01, Output 1 State 10, Input 0 -> State 00, Output 0 State 11, Input 1 -> State 11, Output 1

B+

Z
R.H. Katz Transparency No. 15-17

Moore and Mealy Machines ASM Chart for Mystery Mealy Machine S0 = 00, S1 = 01, S2 = 10, S3 = 11

Contemporary Logic Design Finite State Machine Design

S0

00

S2

10

0 X 0 H. Z X 1

H. Z

S1

01

S3 H.Z

11

X 0

NOTE: Some Outputs in Output Boxes as well as State Boxes This is intrinsic in Mealy Machine implementation
R.H. Katz Transparency No. 15-18

Moore and Mealy Machines Synchronous Mealy Machine

Contemporary Logic Design Finite State Machine Design

Breaks the direct connection between inputs and outputs by introducing storage elements. Prevents glitches as seen in Mealy Machine example.

Clock Xi Inputs

Output FFs

Combinational Logic for Outputs and Next State State Register

Zk Outputs

Clock

state feedback

latched state AND outputs avoids glitchy outputs!

R.H. Katz Transparency No. 15-19

HW #15 -- Section 8.3 & 8.4

Contemporary Logic Design Finite State Machine Design

R.H. Katz Transparency No. 15-20