8051 Chap3 Instruction

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The 8051 Microcontroller Chapter 3 Instruction Set
L Ch Thng Ref. I. Scott Mackenzie, The 8051 Microcontroller
Instruction Set
255 instructions, mnemonic code 1-3 byte instructions Opcode(operation code) + 0,1,2 bytes address, data 1-byte instructions 139 2-byte instructions 92 3-byte instructions 24
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FIGURE B1
Opcode map
Jump, call, push, pop
MOV
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Coding format
Opcode (operation code) + operands
Operands addressing modes

Register Direct : address Indirect Immediate : constant Relative : jump, branch, call (change PC) Long : call Indexed : array (base+offset)
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FIGURE 31 8051 Addressing modes. (a) Register addressing (b) Direct addressing (c) Indirect addressing (d) Immediate addressing (e) Relative addressing (f) Absolute addressing (g) Long addressing (h) Indexed addressing
Coding format - Addressing modes
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Addressing Modes
Register Addressing
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Register banks o Bank 0 (default), Bank 1, Bank 2, and Bank 3 o Change register bank by selecting bits RS1 and RS0 the program status word (discussed next slide) o One bank includes 8 registers: R0 through R7 Ex: Read the contents of location 05H into the accumulator MOV A, R5 or MOV A, 05H Write the contents of the accumulator into location 00H MOV R0, A
Program Status Word (PSW)
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Addressing Modes
Register Addressing - 8 registers: R0 ~ R7 Ex: MOV A,R6 ADD A,R7 - 4 banks of registers: Bank 0 (default), Bank 1, Bank 2, and Bank 3 - The active bank is determined by bit PSW.3 & PSW.4 (reviewed in the next 2 slides) Ex: MOV PSW,#00011000B; activates bank 3 Ex: INC DPTR
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Addressing Modes
Direct Addressing
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Internal (on-chip) data memory:
General purpose RAM (30H-7FH)
Using for MUL,DIV
Bit-addressable RAM (20H-2FH)
Register banks (00H-1FH)
DPTR
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Special function registers (80H-FFH)
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Addressing Modes
Direct Addressing - Access internal memory Ex: MOV A,30H ADD A,31H - Access special function registers: can use the mnemonic abbreviation instead of the addresses Ex: MOV P1,A; Accumulator Port 1 MOV 90H,A; same Opcode: F5 90 Ex: MOV R1,ACC MOV R1,0E0H MOV R1,A Same function, but 0000 A9E0 1 MOV R1,ACC
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MOV R1,0E0H MOV R1,A
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Addressing Modes
Immediate Addressing - Source operand is constant - Use # sign Ex: MOV A,#12 MOV A,#0CH MOV R1,#0 ADD A,#11110001B MOV DPTR,#2000H
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Addressing Modes
Indirect Addressing - Address of a memory location is stored in R0 or R1 - Use @sign to access the content of this memory location: @R0, @R1 Ex: MOV R0,#30H MOV A,@R0 Ex: Implementation of array MOV R0, #60H LOOP: MOV @R0, #0 INC R0 CJNE R0, #80H, LOOP
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Addressing Modes
Relative Addressing - Used with SJMP instruction. - A relative address (or offset) is an 8-bit signed value. - It is added to PC to form a new value for PC. - Range: -128 ~ +127 - Usually used with label Ex: SJMP LABEL1 is in memory at locations 0100H and 0101H PC = 0102H - LABEL1 is the label representing an instruction at location 0107H Relative offset is 0107H 0102H = 5 Opcode of SJMP LABEL1 is 80 05
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Addressing Modes
Relative Addressing
FIGURE 32 Calculating the offset for relative addressing. (a) Short jump ahead in memory (b) Short jump back in memory
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Addressing Modes
Absolute Addressing
FIGURE 33 Instruction encoding for absolute addressing. (a) Memory map showing 2K pages (b) Within any 2K page, the upper five address bits are the same for the source and destination addresses. The lower 11 bits of the destination are supplied in the instruction
Addressing Modes
Long Addressing - Used with LCALL and LJMP instruction - Use full 16-bit address - Usually used with label Ex: LCALL SUBPROGRAM1 LJMP LABEL2 Indexed Addressing - Base address (PC or DPTR) + Offset (A) - Used with JMP or MOVC Ex: MOVC A, @A+DPTR JMP @A+DPTR
Effective Address
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Instruction Types
Data transfer Arithmetic Logical Boolean variable Program branching
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8051 Instruction Set Summary

Legend
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Data Transfer
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Data Transfer
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Data Transfer Ex: Write a program to move (write) 40H to location 30H in internal RAM using 2 methods of addressing: direct addressing and indirect addressing. Method 1: Direct addressing ORG 0000H MOV 30H,#40H END Method 2: Indirect addressing ORG 0000H MOV R0,#30H MOV @R0,#40H END
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Data Transfer Ex: Write a program to clear location 31H in internal RAM using 2 methods of addressing: direct addressing and indirect addressing. Hint: to clear means to reset the data to zero. Method 1: Direct addressing ORG 0000H MOV 31H,#0 END Method 2: Indirect addressing ORG 0000H MOV R0,#31H MOV @R0,#0 END
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Data Transfer Ex: Write a program to move (write) the content of A to location 32H in internal RAM using 2 methods of addressing: direct addressing and indirect addressing. Method 1: Direct addressing ORG 0000H MOV 32H,A END Method 2: Indirect addressing ORG 0000H MOV R0,#32H MOV @R0,A END
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Data Transfer Ex: Write a program to move the content of location 33H in internal RAM to register A using 2 methods of addressing: direct addressing and indirect addressing. Method 1: Direct addressing ORG 0000H MOV A,33H END Method 2: Indirect addressing ORG 0000H MOV R0,#33H MOV A,@R0 END
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Data Transfer Ex: Write a program to move the content of location 33H in internal RAM to register A using 2 methods of addressing: direct addressing and indirect addressing. Method 1: Direct addressing ORG 0000H MOV A,33H END Method 2: Indirect addressing ORG 0000H MOV R0,#33H MOV A,@R0 END
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Data Transfer Ex: Write a program to move the content of location 34H in internal RAM to location 35H in internal RAM using 2 methods of addressing: direct addressing and indirect addressing. Method 1: Direct addressing ORG 0000H MOV 35H,34H END Method 2: Indirect addressing ORG 0000H MOV R0,#34H MOV A,@R0 INC R0 MOV @R0,A END
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Data Transfer Ex: Write a program to write 40H to location 0030H in external RAM. ORG 0000H MOV A,#40H MOV DPTR,#0030H MOVX @DPTR,A END
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Data Transfer Ex: Write a program to clear location 0031H in external RAM. ORG 0000H CLR A MOV DPTR,#0031H MOVX @DPTTR,A END
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Data Transfer Ex: Write a program to move the content of location 0032H in external RAM to register A. ORG 0000H MOV DPTR,#0032H MOVX A,@DPTTR END
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Data Transfer Ex: Write a program to move the content of register A to location 0033H in external RAM. ORG 0000H MOV DPTR,#0033H MOVX @DPTTR,A END
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Data Transfer Ex: Write a program to move the content of location 0034H in external RAM to location 0035H in external RAM. ORG 0000H MOV DPTR,#0034H MOVX A,@DPTTR INC DPTR MOVX @DPTR,A END
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Arithmetic Operations
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Flag Effect
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Logic Operations
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Boolean Variable
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Program Branching
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Program Branching
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Arithmetic
Status in PSW : CY (carry/borrow), PSW.7 OV (overflow), PSW.2 AC (Auxiliary carry), PSW.6 Flag 0 (zero), PSW.5 P (Even parity), PSW.0 RS1,0 PSW.4,3 CY for unsigned integer OV for signed integer, (+)+(+)(-), (-)+(-)(+) ADDC, SUBB multi-byte operations DA (decimal adjustment) for BCD
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Examples allowed addressing mode for specified

instructions
; ADD/SUB with C/B MOV A, R7 CLR C ; bit operation, used bit-address SUBB A, R6 ; inc/dec data in data memory MOV A, direct INC A MOV direct, A ; 2-byte data dec DEC DPL MOV R7, DPL CJNE R7, #0FFH, SKIP;compare and jump if DEC DPH SKIP: .
; MUL/DIV MUL AB DIV AB SUBB A, R6 ; BCD addition MOV A, 43H ADD A, 41H DA A MOV 41H, A MOV A, 42H ADD A, 40H DA A MOV 40H, A
;PSW status of A
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Logic
ANL, ORL, XRL CLR A, CPL A (complement) RL, RLC RR, RRC SWAP
MOV LOOP: RLC XCH RRC XCH DJNZ XCH
R7, #8 A A, 0F0H ; register B : 0F0H A A, 0F0H R7, LOOP; dec/jump, R7- counter A, 0F0H
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Data transfer
MOV (internal memory), MOVX (external memory) XCH A, <source> XCHD A,<source> ; exchange digits (lower nibble) PUSH, POP PUSH : sp++; @sp data POP : Ri @sp ; sp--; sp (stack pointer) : 08H-7FH if sp>7FH; no operation
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; LOOK-UP TABLE, TRICKED; usually PC can ; not be accessed directly MOV A, #ENTRY_NUMBER; n+size (RET) CALL LOOK_UP . ; subroutine LOOK_UP: MOVC A, @A+PC ; move constant RET TABLE: ; define byte-data (array for highlevel language) DB data1, data2, data3,
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Time-space consideration ; TABLE LOOKUP - 13 bytes, 5 clocks SQUARE: INC A ; sizeof (RET), 1 clocks MOVC A, @A+PC ; move constant, 2 clocks RET ; 2 clocks TABLE: ; define data (array for high-level language DB 0,1,4,9,16, 25, 36, 49, 64, 81 ; Use multiplication - 8 bytes, 13 clocks SQUARE: PUSH 0F0H ; register B <bit operand>, LABEL, 2 clocks MOV 0F0H, A ; 1 clocks MUL AB ; 4 cycles POP 0F0H ; 2 clocks RET ; 2 clocks
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Boolean
Bit operand, address 0-127
SETB <bit operand> CLR <bit operand> MOV <bit operand>, <bit operand> CLR C (single instruction) compare with CLR CY JC LABEL (jump if CY=1) JB <bit operand>, LABEL (jump if bit==1) JBC <bit operand>, LABEL (jump if bit==1 and clear bit) JNC LABEL JNB <bit operand>, LABEL
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FIGURE 34
Simple implementation of a logic AND operation
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FIGURE 35
Instruction sequence for worst-case propagation delay
LOOP: MOV ANL MOV SJMP
C, P1.0 C, P1.1 P1.2,C LOOP
; XOR MOV JNB CPL SKIP: ..
C, BIT1 BIT2, SKIP C
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Program branching
SJMP : 8-bit offset LJMP : 11-bit address (2KB segment) AJMP : 16-bit LCALL, ACALL
Example MOV MOV RL JMP
DPTR, #JMP_TABLE A, #INDEX_NUMBER A @A+DPTR
; index*2-byte
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Example : ; DJNZ : Dec and jump non-zero ; use as counter MOV R7, #10 LOOP: DJNZ R7, LOOP ; CJNZ : compare and jump non-zero CJNZ A, #03H, SKIP SJMP TERMINATE SKIP:
; 03H : control-C
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Example : bit-wise XOR XRB: MOV ANL MOV MOV ANL ORL
20H, C C, /P 21H, C C, P C,/20H C,21H
Other ways (1) Use byte-wise XOR (2) Use JB, JNB
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FIGURE 38
Interface to a DIP switch and 7-segment LED
Example : BCD to 7-segment decoder
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Some Simple Instructions

MOV dest,source
MOV A,#72H MOV R4,#62H MOV B,0F9H MOV DPTR,#7634H MOV DPL,#34H MOV DPH,#76H MOV P1,A ;mov A to port 1
; dest = source
;A=72H ;R4=62H ;B=the content of F9th byte of RAM
Note 1:
MOV A,#72H MOV A,72H After instruction MOV A,72H the content of 72th byte of RAM will replace in Accumulator.
Note 2:
MOV A,R3
MOV A,3
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ADDA, Source
ADDA,#6 ADDA,R6 ADD ADD A,6 A,0F3H ;A=A+6
;A=A+SOURCE
;A=A+R6 ;A=A+[6] or A=A+R6 ;A=A+[0F3H]
SUBB
SUBB SUBB
A, Source
A,#6 A,R6 ;A=A-6
;A=A-SOURCE-C
;A=A+R6
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MUL & DIV

MUL MOV MOV MUL AB ;B|A = A*B A,#25H B,#65H AB ;25H*65H=0E99 ;B=0EH, A=99H AB ;A = A/B, B = A mod B A,#25 B,#10 L Ch Thng B=5 AB ;A=2,
DIV MOV MOV Ref. I.DIV Scott Mackenzie
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SETB bit CLR bit

SETB SETB SETB SETB SETB
Note:
; bit=1 ; bit=0
; CY=1 ;bit 0 from port 0 =1 ;bit 7 from port 3 =1 ;bit 2 from ACCUMULATOR =1 ;set high D5 of RAM loc. 20h
C P0.0 P3.7 ACC.2 05
CLR instruction is similar to SETB i.e.: CLR C ;CY=0 But following instruction is only for CLR: CLR A ;A=0
DEC INC
INC DEC DEC
byte byte
R7 A 40H
;byte=byte-1 ;byte=byte+1
; [40]=[40]-1
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RR RL RRC RLC A EXAMPLE: RR A RR: RRC: RL: RLC:

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ANL - ORL XRL Bitwise Logical Operations: AND, OR, XOR

EXAMPLE: MOV R5,#89H ANL R5,#08H
CPL
;1s complement
A,#55H ;A=01010101 B A P1,A DELAY L01
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Example: MOV L01: CPL MOV ACALL SJMP

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Stack in the 8051

The register used to access the stack is called SP (stack pointer) register. The stack pointer in the 8051 is only 8 bits wide, which means that it can take value 00 to FFH. When 8051 powered up, the SP register contains value 07.
7FH Scratch pad RAM 30H 2FH Bit-Addressable RAM 20H 1FH 18H 17H 10H 0FH 08H 07H 00H
Register Bank 3 Register Bank 2 (Stack) Register Bank 1 Register Bank 0
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Example: MOV MOV MOV PUSH PUSH PUSH

0BH 0AH 09H 08H Start SP=07H
R6,#25H R1,#12H R4,#0F3H 6 1 4

0BH 0AH 09H 08H 25 0BH 0AH 09H 08H 12 25 0BH 0AH 09H 08H F3 12 25
SP=08H
SP=09H
SP=08H
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LOOP and JUMP Instructions

Conditional Jumps :
JZ JNZ DJNZ CJNE A,byte CJNE reg,#data JC JNC JB JNB JBC Jump if A=0 Jump if A/=0 Decrement and jump if A/=0 Jump if A/=byte Jump if byte/=#data Jump if CY=1 Jump if CY=0 Jump if bit=1 Jump if bit=0 Jump if bit=1 and clear bit
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DJNZ:
Write a program to clear ACC, then add 3 to the accumulator ten time Solution: MOV MOV ADD DJNZ MOV A,#0 R2,#10 A,#03 R2,AGAIN ;repeat until R2=0 (10 times) R5,A
AGAIN:
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LJMP(long jump) LJMP is an unconditional jump. It is a 3-byte instruction. It allows a jump to any memory location from 0000 to FFFFH. AJMP(absolute jump) In this 2-byte instruction, It allows a jump to any memory location within the 2k block of program memory. SJMP(short jump) In this 2-byte instruction. The relative address range of 00FFH is divided into forward and backward jumps, that is , within -128 to +127 bytes of memory relative to the address of the current PC.
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CALL Instructions
Another control transfer instruction is the CALL instruction, which is used to call a subroutine.
LCALL(long call) This 3-byte instruction can be used to call subroutines located anywhere within the 64K byte address space of the 8051. ACALL (absolute call) ACALL is 2-byte instruction. the target address of the subroutine must be within 2K byte range.
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Example: Write a program to copy a block of 10 bytes from RAM location starting at 37h to RAM location starting at 59h. Solution: MOV R0,#37h MOV R1,#59h MOV R2,#10 L1: MOV A,@R0 MOV @R1,A INC R0 INC R1 DJNZ R2,L1
; source pointer ; dest pointer ; counter
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Performing the Addition with 8051

. . + = R1 65536's 256's R6 R4 R2 1's R7 R5 R3
1.Add the low bytes R7 and R5, leave the answer in R3. 2.Add the high bytes R6 and R4, adding any carry from step 1, and leave the answer in R2. 3.Put any carry from step 2 in the final byte, R1.
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Steps 1, 2, 3
MOV A,R7 ;Move the low-byte into the accumulator ADD A,R5 ;Add the second low-byte to the accumulator MOV R3,A ;Move the answer to the low-byte of the result
MOV A,R6 ;Move the high-byte into the accumulator ADDC A,R4 ;Add the second high-byte to the accumulator, plus carry. MOV R2,A ;Move the answer to the high-byte of the result MOV A,#00h ;By default, the highest byte will be zero. ADDC A,#00h ;Add zero, plus carry from step 2. MOV R1,A ;Move the answer to the highest byte of the result
References
I. Scott Mackenzie, The 8051 Microcontroller Cc ti liu trn Internet khng trch dn hoc khng ghi tc gi
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8051 Chap3 Instruction

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8051 Chap3 Instruction

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H Bch Khoa TP.

The 8051 Microcontroller Chapter 3 Instruction Set

L Ch Thng Ref. I. Scott Mackenzie, The 8051 Microcontroller

H Bch Khoa TP.HCM

Jump, call, push, pop

Ref. I. Scott Mackenzie

Operands addressing modes

H Bch Khoa TP.HCM

Coding format - Addressing modes

Ref. I. Scott Mackenzie

Ref. I. Scott Mackenzie

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Program Status Word (PSW)

Ref. I. Scott Mackenzie

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Ref. I. Scott Mackenzie

Ref. I. Scott Mackenzie

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Internal (on-chip) data memory:

General purpose RAM (30H-7FH)

Using for MUL,DIV

Bit-addressable RAM (20H-2FH)

Register banks (00H-1FH)

Ref. I. Scott Mackenzie

Special function registers (80H-FFH)

0002 A9E0 0004 F9 L Ch Thng

MOV R1,0E0H MOV R1,A

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Ref. I. Scott Mackenzie

Ref. I. Scott Mackenzie

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Ref. I. Scott Mackenzie

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Ref. I. Scott Mackenzie

H Bch Khoa TP.HCM

Ref. I. Scott Mackenzie

8051 Instruction Set Summary

Ref. I. Scott Mackenzie

H Bch Khoa TP.HCM

8051 Instruction Set Summary

Ref. I. Scott Mackenzie

8051 Instruction Set Summary

Ref. I. Scott Mackenzie

H Bch Khoa TP.HCM

8051 Instruction Set Summary

Ref. I. Scott Mackenzie

8051 Instruction Set Summary

Ref. I. Scott Mackenzie

H Bch Khoa TP.HCM

8051 Instruction Set Summary

Ref. I. Scott Mackenzie

8051 Instruction Set Summary

Ref. I. Scott Mackenzie

H Bch Khoa TP.HCM

8051 Instruction Set Summary

Ref. I. Scott Mackenzie

8051 Instruction Set Summary

H Bch Khoa TP.HCM

8051 Instruction Set Summary

Ref. I. Scott Mackenzie

8051 Instruction Set Summary

Ref. I. Scott Mackenzie

H Bch Khoa TP.HCM

8051 Instruction Set Summary