Given below are some examples instead of BNF type of +maxdelays, +typdelays(default), +mindelays

definitions. e.g. verilog +maxdelays test.v

„ if (reset == 0) begin
data = 8’b00; 7. Declarations
end {}, {{}} concatenation
® „ case (operator) +-*/ arithmetic
Verilog Quick Reference Card 2’d0 : z = x + y; % modulus
2’d1 : z = x – y; > >= < <= relational
2’d2 : z = x * y; ! logical negation
default : $display (“Invalid Operation”); && logical and
1. Module endcase || logical or
module module_name (list of ports); „ initial begin // 50 MHz clock == logical equality
input / output / inout declarations clock = 0; != logical inequality
net / reg declarations forever #10 clock = ~clock; === case equality
integer declarations end // precission 1 ns !== case inequality
parameter declarations „ repeat (2) @(posedge clk) data; ~ bit-wise negation
„ bus <= repeat (5) @ (posedge clk) data & bit-wise and
gate / switch instatnces // evaluate data when the assignment is | bit-wise inclusive or
hierarchical instances // encountered and assign to bus after 5 ^ bit-wise exclusive or
parallel statements // clocks. ^~ or ~^ bit-wise equivalence
endmodule „ repeat (flag) begin // looping & reduction and
.... action .... ~& reduction nand
2. Parallel Statements „ while (i < 10) begin | reduction or
Following statements start executing simultaneously inside .... action .... ~| reduction nor
module end ^ reduction xor
initial begin „ for (i = 0; i < 9; i = i + 1) begin ~^ or ^~ reduction xnor
{sequential statements} .... action .... << left shift
end end >> right shift
always begin „ wait (!oe) #5 data = d_in; ?: condition
{sequential statements} „ @(negedge clock) q = d; or event or
end „ begin // finishes at time #25
assign wire_name = [expression]}; #10 x = y;
#15 a = b; 8. Attributes
end specify
3. Basic Data Types „ fork // specparam declarations (min:typ:max)
a. Nets #10 x = y; specparam t_setup = 8:9:10, t_hold = 11:12:13;
e.g. wire, wand, tri, wor #15 a = b; // timing constraints checks
„ Continuously driven join $setup (data, posedge clock, t_rise);
„ Gets new value when driver changes $hold (posedge clear, data, t_hold);
„ LHS of continuous assignment // simple pin to pin path delay
tri [15:0] data; 5. Gate Primitives (a => out) = 9; // => means parallel connection
// unconditional and (out, in1, ..., inn); nand (out, in1, ..., inn); // edge sensitive pin to pin path delay
assign data[15:0] = data_in; or (out, in1, ..., inn); nor (out, in1, ..., inn); (posedge clock => (out +: in)) = (10, 8);
// conditional xor (out, in1, ..., inn); xnor (out, in1, ..., inn); // state dependent pin to pin path delay
assign data[15:0] = enable ? data_in : 16’bz; buf (out1, ..., outn, in); not (out1, ..., outn, in); if (state_a == 2’b01) (a, b *> out) = 15;
b. Registers bufif0 (out, in, control); bufif1 (out, in, control); // *> means full connection
e.g. reg notif0 (out, in, control); notif0 (out, in, control); endspecify
„ Represents storage pullup (out); pulldown (out);
„ Always stores last assigned value 9. Memory Instantiation
„ LHS of an assignment in procedural block. 6. Delays module mem_test;
reg signal; Single delay : and #5 my_and (...); reg [7: 0] memory [0: 10]; // memory declaration
@(posedge clock) signal = 1’b1; Rise/ Fall : and #(5, 7) my_and (...); integer i;
// positive edge Rise/ Fall / Transport : bufif1 #(10, 15, 5) my_buf (...); initial begin
@(reset) signal = 1’b0; // event (both edges) All delays as min:typ:max : or #(4:5:6, 6:7:8) my_or (...); // reading the memory content file
$readmemh (“contents.dat”, memory);
4. Sequential Statements Compiler options for delays // display contents of initialized memory
 for (i = 0; i < 9, i = i + 1) „ Tasks do not return with a value, but can pass multiple $stop; // stop for interaction
$display (“Memory [%d] = %h”, i, memory[i]); values through output and inout arguments. #1000 $finish; // come out of simulation
end .... end
endmodule Cycle_read (read_in, oe_in, data, addr);
.... 15. Language Constructs Not Supported By
“contents.dat” contains task Cycle_read;
@02 ab da input read, oe; // notice the order Most Synthesis Tools
@06 00 01 output [7: 0] data; Declarations and Definitions
„ This simple memory model can be used for feeding input [15: 0] address; time declaration
input data values to simulation environment. begin event declaration
„ $readmemb can be used for feeding binary values from #10 read_pin = read; triand, trior, tri1, tri0, and trireg net types
contents file. #05 oe_pin = oe; Ranges and arrays for integers
data = some_funtion (address); primitive definition
end Statements
10. Blocking and Non-blocking Statements initial statement
// These blocking statements exhibit race condition. endtask
delay control
always @(posedge clock) event control
a = b; 12. Commonly Used Compiler Directives wait statement
always @(posedge clock) ‘define word_size 32 repeat statement
b = a; ‘include ../header.v fork statement
// This Non-blocking statement removes above race ‘timescale 100ns/1ns // ref_time_unit / precision deassign statement
// condition and gives true swapping operation ‘ifdef, ‘else, ‘endif force statement
always @(posedge clock) e.g. release statement
a <= b; module and_op (a, b, c); defparam statement
always @(posedge clock) output a; Operators
b <= a; input b, c; Division and modulus operators for variables
‘ifdef behavioral Case equality and inequality operators (=== and !==)
11. Functions and Tasks wire a = b & c; Gate-Level Constructs
Function ‘else pullup, pulldown,
„ A function can enable another function but not another and (a, b, c); tranif0, tranif1, rtran, rtranif0, rtranif1
task. ‘endif Miscellaneous Constructs
„ Functions always execute in 0 simulation time. endmodule Compiler directives like ‘ifdef, ‘endif, and ‘else
„ Functions must not contain any delay, event, or timing Hierarchical names within a module
control statements. 13. Observing Outputs
„ Functions must have at least one input argument. They $display (“Value of variable is %d”, var);
can have more than one input. integer flag;
„ Functions always return a single value. They cannot initial flag = $fopen (“out_file”); Verilog is a trademark of Cadence Design Sysytems, Inc.
have output or inout argument. always @(....); // dump data in text file
e.g. $fdisplay (flag, “%h”, data [7: 0]); Verilog Quick Reference Card is intended for quick reference.
.... ........ Please use Verilog LRM for details.
parity = calc_parity (addr); $fclose (“out_file”);
.... end
function calc_parity; $monitor ($time, “a = %b and b = %b”, clock, reset);
input [31: 0] address; $fmonitor (flag, “value = %h”, add [15: 0]);
begin $monitoron;
calc_parity = ^address; $monitoroff;
end
endfunction 14. Simulation Control
initial begin
Task $dumpfile (“my.dump”); // dump in this file
„ A task can enable other tasks and functions. $dumpvars; // dump all signals
„ Tasks may execute in non-zero simulation time. $dumpvars (1, top);
„ Tasks may contain delay, event, or timing control // dump variables in module instance top
statements. $dumpvars (2, top.m1); // dump 2 levels below top.m1
„ Tasks may have zero or more arguments of type input, #1000 dumpoff; // stop dump
output, or inout. #500 dumpon; // start / restart dump