No 1: Titile:

Abstract:
In this paper, we present a novel compression method and a low-cost decompression architecture that combine the advantages of both symbol-based and linear-based techniques and offer a very attractive unified solution that removes the barriers of existing test data compression techniques. Besides the traditional goals of high compression and short test application time, the proposed method also offers low shift switching activity and high unmodeled defect coverage at the same time. In addition, it favors multi-site testing as requires a very low pin-count interface to the automatic test equipment. Finally, contrary to existing techniques, it provides an integrated solution for testing multi-core system on chips (SoCs) as it is suitable for cores of both known and unknown structures that usually coexist in SoCs. High-Quality Statistical Test Compression With Narrow ATE Interface

Link: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber= 6582565&sortType%3Ddesc_p_Publication_Year%26queryTex t%3Dtest+vector+compression

No 2: Title:
Binary Difference Based Test Data Compression for NoC Based Soc. The scaling of microchip technologies has enabled large scale and

Abstract:

very complex systems-on-chip (SoC). The highperformance, flexible, scalable, simple to design and power efficient interconnection network, called the Network-onchip (NoC), permits the system components to communicate effectively. This communication structure needs to be tested for correctness, which requires handling huge volume of test data. Thus, test data compression has now become essential to reduce test costs. It reduces test data volume which in turn decreases testing time. This work presents a new test data compression method based on binary difference and the corresponding decompression architecture. The major advantages of this compression technique include very high compression ratio, and a low-cost on-chip decoder. The effectiveness of the proposed approach is demonstrated by applying it to the full scan test data set of ISCAS'89 benchmark circuits.

Link: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber= 6296458&sortType%3Ddesc_p_Publication_Year%26pageNum ber%3D2%26queryText%3Dtest+vector+compression

No 3: Title:
Reduction of Test Power and Test Data Volume by Power Aware Compression Scheme

Abstract: This paper presents a new approach to reduce both test power and test
data volume without compromising the target fault coverage. To reduce the shift power during testing we are filling the unspecified bits (X-bits) in the test pattern with 0's or 1's by observing the effect of each X bit on the shift transition. The shift power and compression rate depends on the percentage of X bits present in the pattern. After filling the X-bits for shift power reduction, the patterns are compressed based on shifted alternating frequency directed run-length coding, which is suitable for encoding pre-computed test set of embedded cores in System-on-Chip(SoC). The experimental results on ISCAS'89 benchmark circuits show that our scheme provides better compression efficiency as well as significant reduction in test power.

Link: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber= 6305578&sortType%3Ddesc_p_Publication_Year%26pageNum ber%3D3%26queryText%3Dtest+vector+compression

No 4: Title:
On Utilizing Test Cube Properties to Reduce Test Data Volume Further

Abstract:

Test data compression has become a dominant approach to reduce the

test cost today. Majority of test compression schemes are based on the fact that the generated test cubes have very few specified bits. This paper studies additional test cube properties and utilizes them to reduce the test data volume (TDV) further. Two approaches are proposed in this paper. The first one requires no additional hardware and the second one is based on the new DFT hardware, named background chains. The proposed approaches can be combined with other test compression schemes to achieve additional TDV reduction. The experimental results based on embedded deterministic test (EDT) show the proposed approaches achieve significant TDV reduction for industrial designs.

Link: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber= 6394180&sortType%3Ddesc_p_Publication_Year%26pageNum ber%3D3%26queryText%3Dtest+vector+compression

No 5: Title:
Low power compression utilizing clock-gating Growing test data volume and excessive test power consumption in scan

Abstract:

testing are both serious concerns for the semiconductor industry. This paper presents a method to simultaneously reduce test data volume and test power utilizing clock gating. This is achieved through not clocking a high proportion of scan chains during both scan shift and test response capture. Reducing the number of scan chains shifted during scan load can be expected to permit higher scan shift frequency thus reducing the test time. Reduced test data volume can be expected to permit fewer tester channels for testing which can increase the number of chips tested in parallel. Experimental results presented for industrial circuits demonstrate that on average a factor of 1.98 and 4 reductions in test data volume and test power, respectively is achievable using the proposed method.

Link: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber= 6139145&sortType%3Ddesc_p_Publication_Year%26pageNum ber%3D4%26queryText%3Dtest+vector+compression

No 6: Title: Test-data volume and scan-power reduction with

low ATE interface for multi-core SoCs

Abstract:
Symbol-based and linear-based test-data compression techniques have complementary properties which are very attractive for testing multi-core SoCs. However, only linear-based techniques have been adopted by industry as the symbol-based techniques have not yet revealed their real potential for testing large circuits. We present a novel compression method and a low-cost decompression architecture that combine the advantages of both symbol-based and linear-based techniques under a unified solution for multi-core SoCs. The proposed method offers higher compression than any other method presented so far, very low shift switching activity and very short test sequence length at the same time. Moreover, contrary to existing techniques, it offers a complete solution for testing multi-core SoCs as it is suitable for cores of both known and unknown structure (IP cores) that usually co-exist in modern SoCs. Finally, it supports very low pin-count interface as it needs only one tester channel to download fast the compressed test data on-chip.

Link:
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6105413&sortType%3Ddesc_p_Publicatio n_Year%26pageNumber%3D4%26queryText%3Dtest+vector+compression

No 2: Title: Test data compression based on the reuse of parts

of the dictionary entries

Abstract:

In this paper we show that the test data compression achieved by a dictionary based method can be improved significantly by suitably reusing parts of the dictionary entries. To this end two new algorithms are proposed, suitable for partial and complete dictionary coding respectively. The efficiency of the proposed techniques is supported with extensive simulation results.

Link:
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6122331&sortType%3Ddesc_p_Publicatio n_Year%26pageNumber%3D5%26queryText%3Dtest+vector+compression