Design of CMOS IC Process A1-002-B: Semiconductor Fabrication Process & Device Characterization for CMOS Technology Nabilah Binti

Sk.Abd.Aziz (GIT 0755) MODULE ASSIGNMENT INTRODUCTION The following exercise is to design and simulate MOSFET transistors for a given device specifications using the Silvaco TCAD tools. OBJECTIVES 1.Silvaco Athena and Atlas software familiarization. 2.Design of MOSFET transistors using the given recipe to meet the device specifications. ASSIGNMENT CONTENT PART 1: Silvaco Athena and Atlas software familiarization 1.Refer to the Athena & Atlas software manuals in Module A.1 section. 2.Follow the instructions accordingly. PART 2: MOSFET Design 1.Using Athena, design the NMOS and PMOS transistors with the following specifications. i. Gate length: 0.6um ii. Abs. Threshold voltage: 0.4 V < VTH < 0.5 V iii. Abs. Leakage current: < 0.1 nA iv. NMOS Drain current, ID > 1 mA at VGS = 3.3 V and VDS = 3.3 V v. PMOS Drain Current, ID < 0.5 mA at VGS = -3.3V and VDS = -3.3 V

NMOS (ATHENA CODE)

OUTPUT STRUCTURE

I-V Curve:

The I-V curve above shows the ID when VDS and VGS are equal 3.3 V. The value of ID is larger than 1mA as in the specifications. (ID=1.014 mA).

PMOS (ATHENA CODE)

Output Structure:

I-V CURVE

IV curve above shows the ID when VDS and VGS are equal 3.3 V. ID is less than 0.5mA as in the specifications. (ID=0.105 mA)

QUESTIONS AND DISCUSSION 1.What are the design parameters that affect the threshold voltage of the device? i. Gate oxide thickness ii. Element used and concentration of doping for threshold adjust implant, iii. Type of polysilicon doping and its concentration iv. Concentration of doping for source / drain implant. 2.Explain the trade off in the design in order to meet the specifications. Show with tables of various data points to prove the theoretical assertions. NMOS In order to meet the specifications, there are several parameters and element that have to change. The changes of element for threshold voltage implant with the constant concentration and gate oxide thickness for NMOS are as in the table below:

Gate Oxide Thickness ()

Type of Element

Doping Concentration (cm-3) 3e12 3e12 3e12 3e12 3e12 3e12

Threshold Voltage , VT
(V)

Leakage Current Idoff (A/m) 4.065e-9 1.050e-10 5.039e-11 5.136e-8 1.019e-8 1.423e-10

Drain Current, ID (mA) 1.340 0.758 0.742 1.908 1.404 1.046

43.201

Boron
BF2

0.324 0.405 0.509 0.231 0.250 0.384

Gallium 34.274 Boron

BF2

Gallium

The result above is obtained by using the arsenic as a polysilicon doping with concentration of 5e16 and phosphorus as a source/drain implant with concentration of 5e15. From the table above, when the gate oxide thickness is decrease the threshold voltage is also decrease for each type of element. As for the leakage current, it increase along the type of element when the gate oxide is decrease. The drain current is increase for each element when the gate oxide thickness is decrease. I think the most approximate result that meet the specification is by using gallium. Thus, the doping concentration for gallium and also the concentration of arsenic for the polysilicon doping is adjusted to meet the specification as below:

Gate Oxide Thickness ()

Doping Concentration of Gallium (cm-3 ) 3.25e12 3.25e12

Doping Concentratio n of Arsenic (cm-3)

Threshold Voltage, VT (V)

Leakage Current Idoff (A/m) 3.916e-10 8.324e-11

Drain Current, ID (mA)

43.201 34.274

6e16 6e16

0.490 0.482

1.132 1.014

When the concentration of gallium and arsenic is slightly increase with the same value, the design is meet with all the specifications at gate oxide thickness 34.274 . PMOS The changes for PMOS that affect the specifications are as in the table below:

Based on the table above, it shows that the threshold voltage is increase when the concentration of rhreshold voltage implant is increase with constant doping concentration of polysilicon and source/drain implant. The gate oxide thickness affect both of the threshold voltage and the leakage current. The higher gate oxide thickness gives the higher threshold voltage and lower leakage current. The design meet all the specifications by using higher gate oxide thickness and lower concentration of polysilicon doping.

As for conclusion, the parameters that mostly affect the specifications are the gate oxide thickness and concentration of threshold voltage implant and polysilicon doping. When the gate oxide thickness is increase, VT increase while the leakage current decrease. When the concentration of polysilicon doping is lower, thus it cause the electric field across the channel to decrease. Threshold voltage adjust implant also called backgate doping where backgate doping has a major effect on the threshold voltage. If the backgate is doped more heavily, then it becomes more difficult to invert to create the channel. So a stronger electric field is required to achieve inversion, and the threshold voltage increases. The backgate doping of a MOS transistor can be adjusted by doing a shallow implant under the gate dielectric to dope the channel region. 3. Show Id vs. Vds graphs for various values of Vgs. NMOS

PMOS