Darlington connection.

In circuits where high collector currents are involved, excessive base currents may be
required. The base drive is greatly reduced if the current gain can be increased. This
is achieved with the Darlington connection, as shown in the figure below.

The base current of T2 is the emitter current of T1, so

IC=IC1 + IC2 = β1IB1 + β2IB2 = β1IB1 + β2(β1 + 1)IB1 ≈ β1(1 + β2)IB1

IC ≈ β1β2IB1

Thus, the effective current gain for the composite transistor is equal to the product of
the individual current gains of the two transistors. The small – signal input resistance
of the composite transistor is also significantly increased.

u be u be1 + u be 2 u be1 u
h11 = = = + be 2
ib ib1 ib1 ibe 2
( 2)
h21 +1

h11 = h11(1) + (h21

( 2)
+1)h11( 2 )

The base – emitter voltage and the saturation voltage of the equivalent transistor are,
respectively:

UBE = UBE1 +UBE2 ≈1.4 V

UCE Sat = UBE2 + UCE Sat1 ≈ 1 V

Two pnp transistors can be connected in a similar way. Another beta – boosting
configuration, sometimes referred to as a complementary Darlington is shown below
.
This combination behaves like a pnp transistor, again with large β, but it has only a
single base – emitter drop.

Transistor current sources

Current sources are important electronic circuits. They often provide an excellent way
to bias transistors, e.g. they are used as active loads and emitter sources for
differential amplifiers. They are used in sawtooth and ramp generators and in many
other applications.
The basic concept of a transistor current source is shown in the following figure.

The output current is:

β U − U
I = I = B BE
β >> 1
β + 1
L C
R E
U − U
I L ≅ B BE
R L

as long as the transistor is not saturated.

A current source does not have to have a fixed voltage at the base. By varying UB we
get a voltage programmable (or voltage controlled) current source.
A fixed base voltage can be provided in a number of ways, by using a voltage divider,
a Zener diode or a few forward – biased diodes in series. These three methods of
base biasing are shown in the figures below.
 R2
ECC −U BE U Z −U BE nU F −U BE
R1 + R2 IL = IL =
IL = RE RL
RE
if I R!R 2 >> I B

The circuits with npn transistors sink current,

i.e. the output current flows into the transistor.
The load cannot be grounded at either terminal.

The circuits with pnp transistors source current,

i.e. the output current flows into the load,
of which one terminal can be grounded.
An example curent source with a pnp transistor
is shown in the figure.

A current source can provide constant current to the load only over some finite range
of load voltage / load resistance. The output voltage range over which a current
source behaves well is called its output compliance.
The compliance is set by the requirement that the transistor stays in the active
region.
The current source which is used extensively in integrated circuits is the current
mirror.
In the current mirror two transistors are used:
one acts as the constant current source
while the other establishes the correct
value of UBE. The circuits is show in the following
figure.

The resistor R establishes the current flowing through T1, which operates as a diode.

E −U
I ref = I B1 + I B 2 + IC1 = CC BE
R

Provided that the two transistors are made form the same material, are at the same
temperature and are of the same area (the conditions easy to achieve in integrated
circuits), then the currents flowing in each transistor are the same ( because of the
same UBE).

I = I + I + βI
ref B B B
1
I = I
B β + 2 ref
β
I = β I = I ≈ I if β >> 1
B
β + 2
ref ref

A current mirror can be easily modified to provide multiple current sources, as in the
following figure.
If the areas of individual transistors are different, the current in each transistor is
proportional to the area of the emitter.

If the areas A1 : A2 : A3 : A4 : A5 of the transistors in the figure above are scaled, for
example, 1 : 1 : 2 : 4 : 8, hen the currents Iref, I1, I2, I3, I4 and I5
are also scaled 1 : 1 : 2 : 4 : 8.

Current sources such s this find uses in digital – to – analog converters.

FIELD EFFECT TRANSISTORS (FETs)
The bipolar transistor is a low – impedance current – operated device. The field effect
transistor, on the other hand is a high – impedance voltage operated device. For the
bipolar transistor current flow results from the movement of both holes and electrons
– it is bipolar. Current flow in the field effect transistor only involves one carrier type,
either electrons for n-channel devices, or holes for p-channel devices – it is
sometimes referred to as a unipolar device.
There are two basic types of field effect transistor, one involving a pn junction (JFET)
and the other involving metal – oxide – semiconductor structure (MOSFET). Both
types have very similar current – voltage characteristics. The junction device is more
widely used as a discrete component, while the metal – oxide device is used
extensively in integrated circuits. However, discrete power MOSFETs are used
extensively for power amplifiers.

Physical structure and principle of operation of the JFET

There are two types of device. An n-channel in which current flow takes place in n-
type material, and p-channel device. The symbols for each device are shown below.

A simplified structure of the junction field effect transistor is shown in the following
figures.
The figures represent small bars of semiconductor (silicon), n-type or p-type
depending on the polarity required for the final device. For the n-channel device a p-
type region is formed around the middle of the bar. For normal operation the polarity
of UGS is such that the pn junction is reverse biased and the polarity of UDS. is such
that the majority carriers in the channel ( electrons for n-channel, holes for p-channel)
are attracted from the source to the drain.

To explain the operation of the n-channel JFET let us assume, first, the drain is
shorted with a source. As a result, the voltage along the channel ( with respect to the
source) is zero.

With negative UGS the pn junction

between the gate and channel
is reverse biased.

When the magnitude of UGS is increased, the depletion layers increase too and the
area of the channel cross-section available for conduction decreases. At some UGS,
both depletion layers meet and the channel is pinched – off (emptied of carriers). The
voltage equired to pinch off the channel is referred to as the pinch – off voltage. (Up
or UGsoff ). This voltage typically ranges from 1 to 4 V for small – signal transistors.

Now consider what happens if a positive voltage is applied to the drain. A voltage
drop appears along the channel length.

The reverse bias voltage between the gate and

the channel is minimum near the source (UGS)
and maximum near the drain (UGS – UDS).
At some value of the drain voltage
UGS – UDS = Up

The depletion layers meet at the drain end of the channel. The current does not
cease to flow when pinch – off occurs near the drain because a large electric field
appears there. However, the drain current drops to zero when UGS = Up, because in
such a case the depletion layers meet along the whole length of the channel.
JFET electrical characteristics.

When the drain voltage is applied, electrons flow in the n-type channel from the
source towards the drain. However, the depletion layer which extends into the
channel reduces the cross – sectional area of the channel and increases its
resistance.
As the drain – source voltage increases from zero the current also increases as it
would in a simple resistor. However, the depletion layer increases in width (because
|UGS – UDS| increases) and reduces the cross – sectional area of the channel.
Therefore, the resistance increases and the rate of increase of the current
diminishes, until a point is reached when the channel is pinched off at the drain. For
further increase of UDS the drain current remains approximately constant and it is
said to be saturated. The point at which the channel becomes pinched off near the
drain, for a particular drain – source voltage is known as the knee voltage, UK = UGS
– Up . When UDS increases beyond the knee, the depletion layer moves towards the
source and the length of the active channel is reduced.
With increasing the magnitude of the gate voltage the rain current in the saturation
region decreases until for UGS = Up the channel is completely pinched off and the
current is reduced to a very small value.
Typical output characteristics of the JFET are shown below.

The simplest analytical description of the JFET output characteristics involves

square functions.
For the ohmic (linear) region of operation (UDS < UK):

I DSS
I D = 2
[ 2 (U GS − U p )U DS − U 2
DS ]
U p

For the saturation region (UDS>UK):

2
⎛ ⎞
I = I ⎜ 1 − U GS ⎟
D DSS ⎜ U ⎟
⎝ p ⎠

IDSS is the maximum saturation current (UGS = 0) and Up is the pinch – off voltage.
These two parameters appear in manufacturers’ data sheets.
The curves shown above can be presented in an alternative fashion by plotting the
drain current against gate voltage for the saturation region (transfer characteristic).
The resultant graph is shown below.

This curve can be described by the last

given expression.
For p – channel JFETs the characteristics are similar, but it should be noted that the
conventional directional of the drain current flow is from the drain towards the power
supply, the gate – source voltage should be positive and the drain – source voltage
should be negative.
Typical output and transfer characteristics of a p – channel JFET are shown in the
following figures.

Maximum ratings for JFETs (IDmax, UDSmax, PDmax) are similar to those for bipolar
transistors.
Note also that the gate – source reverse bias voltage should not exceed the
maximum rating. Otherwise the junction could be broken down and the transistor
destroyed. We should not also forward bias the gate – to – channel junction. The
excessive gate current could destroy the transistor too and, besides the gate voltage
does not control the drain current under such conditions.

Small - signal equivalent circuits for the JFET

For hand DC and large – signal analysis the JFET is represented by the nonlinear
equations given previously.
For small – signal analysis a linear equivalent circuit can be used.

Between the gate and the channel there is a pn junction which is normally reverse
biased. This reverse – biased junction exhibits very large values of resistance which
can usually be ignored, but the junction capacitance can have a considerable effect
on the performance of the transistor at high frequencies.
The current flow in the channel is controlled by the gate voltage and the drain to
source voltage. For the field effect transistor the improper parameter is the
transconductance which is defined as:
di D
gm =
dU GS
This parameter varies with the DC value of the drain current.

For the saturation region:

⎡ ⎛ ⎞
2
⎤
g =
dI D
=
d ⎢ I DSS ⎜ 1 − U GS ⎟ ⎥
m
dU dU ⎢ ⎜ U ⎟ ⎥
GS GS
⎣ ⎝ p ⎠ ⎦
2 I ⎛ ⎞ ⎛ ⎞
g = DSS ⎜ 1 − U GS ⎟ = g ⎜ 1 − U GS ⎟
m
U ⎜ U ⎟ m 0 ⎜ U ⎟
p ⎝ p ⎠ ⎝ p ⎠

Where gm0 is the maximum value of transconductance (for UGS = 0).

For low power FETs g m is usually much smaller (a few mS, typically), than the
corresponding parameter for bipolar transistor.

The small – signal equivalent circuit of the JFET, including the above considerations,
is shown below.

ig ≅ 0
1
id = g m u gs + u ds
r ds

rds represents the small – signal output resistance of the JFET (even in saturation)
the output characteristics are not horizontal).
The input resistance is very large (at least tens of MΩ) and can usually be neglected.

The junction capacitances Cgs and Cgd are important for high – frequency analysis
(>1MHz), but for low frequencies they too can be ignored.
Metal – Oxide – Semiconductor (MOS) FETs

MOS FETs are similarly to JFETs, voltage controlled devices too, but their principle
of operation is slightly different.
There are two basic types of MOSFET:
- depletion mode MOSFETs
- enhancement mode MOSFETs.

Each type, in addition, is available as either an n – channel or a p – channel device.

The corresponding symbols are shown below.

The principle of the MOSFET operation is based on the fact that when a voltage is
applied to a metal electrode which is positioned very close to the surface of a
semiconductor then the properties of the surface layer are changed. The electrons or
holes in the semiconductor are attracted or repelled depending on the polarity of the
electric field. This results in the creation or extinction of a channel at the surface of
the semiconductor. The current flow between two diffused regions at both ends of the
channel (source and drain) is controlled by the voltage applied to the external
electrode (gate). The gate electrode is a layer of metal which is deposited on a layer
of dielectric. The dielectric is a layer of silicon dioxide.
A cross – section of the basic depletion – mode n – channel MOSFET is shown
below.
For this type of transistor the channel is formed during the manufacturing process.
For a negative gate voltage UGS the electrons are repelled from the channel to the
substrate and the channel resistance increases. It is said that a negative gate voltage
depletes the channel.

For a positive gate voltage the electrons are attracted from the substrate to the
channel and the channel resistance decreases. It is said that a positive gate voltage
enhances the channel.

Unlike the JFET the voltage applied to the gate can have both polarities because the
gate oxide is a perfect insulator.

Typical output and transfer characteristics of the n – channel depletion mode

MOSFET are shown below.

They are very similar to those for the JFET and the basic difference is that the
operation is possible for both polarities of UGS.
The saturation current IDSS is defined as the current which flows when UGS = 0. Up is
the pinch – off voltage.

For the p – channel device ( n – type substrate), with the drain current and the drain –
to – source voltage reversed, the characteristics are similar.
The current flow in the depletion MOSFET can be described by the same square –
law equations as for the JFET.

For the enhancement – mode MOSFET no channel between the source and drain is
formed in the manufacturing process, so its structure is even simpler. The channel is
formed for n – channel devices when a sufficiently high positive voltage is applied to
the gate, and for the p – channel when a negative voltage is applied.
The transfer curves for the enhancement MOSFET are shown in the following
figures.