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MSP430
MSP430
MSP430
MSP430
MSP430
MSP430
MSP430
MSP430
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Memory map
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Nomenclature
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Architecture
Architecture
Addressing modes 7 addressing modes for source
4 for destination
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Architecture
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Functions and subroutines Functions and Subroutines are lines of code that you use more than once
Functions are used in C ,subroutines used in ALP Local variables are used only when a function is called
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What happens when a subroutine is called? The return address to be pushed on to the stack
The address of the subroutine is then loaded into the PC and
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Program- example
%Subroutine from substk 0.s43, which now saves and restores R4 correctly ; Subroutine to give delay of R12 *0.1s ; Parameter is passed in R12 and destroyed ; R4 used for loop counter, stacked and restored ----------------------------------------------------------------------DelayTenths: push.w R4 ; Stack R4: will be overwritten jmp LoopTest ; Start with test in case R12 = 0 OuterLoop: mov.w #DELAYLOOPS ,R4
DelayLoop: ; [clock cycles in brackets] dec.w R4 ; Decrement loop counter [1] jnz DelayLoop ; Repeat loop if not zero [2] dec.w R12 ; Decrement number of 0.1s delays LoopTest: cmp.w #0,R12 ; Finished number of 0.1s delays? jnz OuterLoop ; No: go around delay loop again pop.w R4 ; Yes: restore R4 before returning Ret ; Return to caller
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Stack Operation
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Very low power leakage, and it operates from a single supply rail Low current drain in standby mode Useful because it shuts down certain areas of the CPU in order to save power As the LPM mode rises power consumption decreases, the time needed to wake up increases register
The MSP430 is switched into a low power mode by altering bits in the status Processing within an interrupt routine will determine when the processor needs
to change from a low power mode to normal operation, and alters those same status register bits to achieve that
It does this by directly modifying the memory location where the processors
status register was pushed onto the stack at the start of the interrupt
When the interrupt routine returns, using the RETI instruction, the altered
status register value is loaded into the processor status register, and the processor continues operation in the newly selected mode
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LPM0 - The CPU is disabled. LPM1 - The loop control for the fast clock (MCLK) is also disabled. LPM2 - The fast clock (MCLK) is also disabled. LPM3 - The DCO oscillator and its DC generator are also disabled. following 1 Active mode (AM), I = 300 uA All clocks are active 2 Low-power mode 0 (LPM0), I = 85uA CPU is disabled ACLK and SMCLK remain active, MCLK is disabled 3 Low-power mode 3 (LPM3), I = 1uA CPU is disabled MCLK and SMCLK disabled ACLK remains active DCOs dc-generator is disabled
LPM4 - The crystal oscillator is also disabled. The most popular 3 are the
As the number of the LPM mode number rises, the number of things disabled
on the chip also rises
But interrupts can wake up the device from any low power mode, process, and
decide whether to restore the low power or active mode.
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Completing the currently executing instruction Pushing the PC, program counter which points to the next instruction, onto the
stack
Pushing the SR, status register, onto the stack Selects the highest priority interrupt, if more than one is waiting execution The interrupt request ag resets automatically on single-source ags; multiple
source ags remain set for servicing by software
The SR is cleared; This terminates any low-power mode; because the GIE
(interrupt enable) bit is cleared, further interrupts are disabled
The content of the interrupt vector is loaded into the PC; the program
continues with the interrupt service routine (ISR) at that address
On executing a return from an ISR, the SR and PC are popped from the stack;
returning to execute the instruction at the point of the interrupt
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Interrupt Stack
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Digital I/O
8 bit digital I/O port Multifunctional capabilities Digital I/O features: Independently programmable individual I/Os Individually congurable P1 and P2 interrupts Independent input and output data registers Individually congurable pullup or pulldown resistors Pins P2.6 and P2.7 - not digital inputs by default Avoiding oating pins Parallel port
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Watchdog Timer Real-time clock Timer A, Timer B Comparator A ADC: ADC10, SD16 A
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Timers
Essential to almost every embedded application Functions 1 Generate xed-period events
2 3 4
Periodic wakeup Count edges Timer calls allow CPU to sleep, consuming much less power
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Basic Timer1
Present in all MSP430xF4xx devices BTCTL, counters not initialized by reset Provides clock for LCD module
Watchdog timer
Features Up-counter
Counts up and resets the MSP430 when it reaches its limit Always active after the MSP430 has been reset Protects the system against failure of software
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Watchdog timer
WDT operation
Controlled by 16-bit register WDTCTL Password WDTPW = 0x5A in the upper byte Software reset
Figure: The lower byte of the watchdog timer control register WDTCTL
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Watchdog Timer
Important facts Always active after the MSP430 has been reset
Default period: 32,768 counts (32 ms) Counter (WDTCNTCL bit) must be repeatedly cleared:
petting, feeding, or kicking the dog Interval Timer Used when protective function is not desired
Set the WDTTMSEL bit
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Real-Time Clock
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Timer A Module
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Timer A Module
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ADC/DAC conversion)
External components
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up to CCR0 value
Up/down: Up to value specied by CCR0, count down to
Timer B
Event kinds Provided on larger devices in all MSP430 families Dierences with Timer A
Registers are double buered Range of periods can be selected for the Continuous mode 3 Sampling mode is not possible (not suitable for receiving asynchronous signals) 4 All outputs can be put into a high-impedance state (TBOUTH pin)
1 2
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Timer usages
Timer A or B.
Inputs to be sampled at regular intervals: Connect to Timer A
(Sampling mode)
Inputs to be timed: Timer A or B Periodic software interrupts 1 Watchdog timer (if it is not needed as a watchdog) 2 Basic Timer1 3 Timer A or B The last resort: Software loops
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Comparator A
Features Supports precision slope analog-to-digital conversion
Supply voltage supervision Monitoring of external analog signals Output provided to Timer A capture input Interrupt capability
Fast, 10-bit analog-to-digital conversions Implements a 10-bit SAR core Sample select control Reference generator Data transfer controller (DTC)
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(1.5 V or 2.5 V)
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representation
Stores the result in the ADC10MEM register Congured by two control registers,
ADC10CLK What the clk does.. Used both as the conversion clock and to generate the sampling period Selection using ADC10SSELx bits and division from 1 to 8 using the ADC10DIVx ADC10OSC, generated internally, is in the 5-MHz range
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Conversion Modes
CONSEQx 00 01 10 11 Mode Single channel single-conversion Sequence-of-channels Repeat single channel Repeat sequence-of-channels Operation single channel is converted once. sequence of channels is converted once. single channel is converted repeatedly. sequence of channels is converted repeatedly.
NADC = 1023
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Among the various registers, the control register comprises of the following bits,
SD16
Each channel has up to 8 fully dierential multiplexed analog input pairs including a built-in temperature sensor Built-in temperature sensor accessible by all channels Selectable low-power conversion mode Software selectable on-chip reference voltage generation (1.2 V)
3 4 5
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Interfacing
Random Light Display- John Davies ADC for thresholding using the 2 inbuilt LEDs LCD shield - a note on energia
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References
www.ti.com/msp430
http://www.uniti.in/teaching-material/79
en.wikipedia.org/wiki/TI_MSP430
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