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Process Part-I

Process Part-I
Aug-1-2013

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Introduction In an always block which is used to model combinational logic, forgetting an else leads to an unintended latch. To avoid this mistake, SystemVerilog adds specialized always_comb and always_latch blocks, which indicate design intent to simulation, synthesis and formal verification tools. SystemVerilog also adds an always_ff block to indicate sequential logic. SystemVerilog has both static processes, introduced by always, initial or fork, and dynamic processes, introduced by built-in fork...join_any and fork...join_none. New features added SystemVerilog is as below
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always_combo always_latch always_ff join_any join_none For continous assignements SystemVerilog allows to drive other then net type to be driven or assigned using assign statement (Continuous assignments), Like reg or integer. always_combo SystemVerilog provides a special always_comb procedure for modeling combinational logic behavior. There is an inferred sensitivity list that includes the expressions defined. The variables written on the left-hand side of assignments shall not be written to by any other process. The procedure is automatically triggered once at time zero, after all initial and always blocks have been started so that the outputs of the procedure are consistent with the inputs. Example - always_combo

1 module a l w a y s _ c o m b _ p r o c e s s ( ) ; 2 3 reg [ 7 : 0 ]s u m , a , b ; 4 reg 5 6 initial 7 p a r i t y ;

begin $monitor ( "@% g a = % h b = % h sum = % h parity = % b", 8 $time, a ,b ,s u m ,p a r i t y ) ; 9 #1 a= 1 ; 1 0 #1 b= 1 ; 1 1 #5 a= 1 0 ; 1 2 #1 $finish; 1 3 end

1 4 1 5 always_comb 1 6 begin 1 7 1 8

:A D D E R

s u m= b+ a ; p a r i t y= ^ s u m ;

1 9 end 2 0 2 1 endmodule You could download file always_comb_process.sv here

Simulator Output
@0 a = xx b = xx sum = xx parity = x

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@0 a = @1 a = @2 a = @7 a =

xx b = 01 b = 01 b = 0a b =

xx sum xx sum 01 sum 01 sum

= = = =

xx parity xx parity 02 parity 0b parity

= = = =

x x 1 1

Process Part-I

always_latch SystemVerilog also provides a special always_latch procedure for modeling latched logic behavior. The always_latch procedure determines its sensitivity and executes identically to the always_comb procedure. Example - always_latch
1 module a l w a y s _ l a t c h _ p r o c e s s ( ) ; 2 3 reg [ 7 : 0 ]s u m , a , b ; 4 reg 5 reg 6 7 initial 8 p a r i t y ; e n a b l e= 0 ;

begin

$monitor ( "@% g a = % h b = % h sum = % h parity = % b", 9 $time, a ,b ,s u m ,p a r i t y ) ; 1 0 #2 a= 1 ; 1 1 #2 b= 1 ; 1 2 #2 a= 1 0 ; 1 3 #2 $finish; 1 4 end

1 5 1 6 always #1 e n a b l e= ~e n a b l e ; 1 7 1 8 always_latch 1 9 begin 2 0

:A D D E R if ( e n a b l e ) begin 2 1 s u m <= b+ a ; 2 2 p a r i t y <= ^ ( b+ a ) ; 2 3 end 2 4 end

2 5 2 6 endmodule You could download file always_latch_process.sv here

Simulator Output
@0 a = @2 a = @4 a = @5 a = @6 a = @7 a = xx b = 01 b = 01 b = 01 b = 0a b = 0a b = xx sum xx sum 01 sum 01 sum 01 sum 01 sum = = = = = = xx parity xx parity xx parity 02 parity 02 parity 0b parity = = = = = = x x x 1 1 1

always_ff The SystemVerilog always_ff procedure can be used to model synthesizable sequential logic behavior. The SystemVerilog always_ff procedure can be used to model synthesizable sequential logic behavior. Variables on the left-hand side of assignments within an always_ff procedure, including variables from the contents of a called function, shall not be written to by any other process. Example - always_ff
1 module a l w a y s _ f f _ p r o c e s s ( ) ; 2 3 reg [ 7 : 0 ]s u m , a , b ; 4 reg 5 logic 6 reg 7 8 initial 9 1 0 p a r i t y ; c l k= 0 ; r s t= 0 ;

begin

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$monitor ( "@% g clk = % b rst = % b a = % h b = % h sum = % h parity = % b", $time, c l k ,r s t ,a ,b ,s u m ,p a r i t y ) ;

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Process Part-I

$time, c l k ,r s t ,a ,b ,s u m ,p a r i t y ) ; 1 1 #1 r s t= 1 ; 1 2 #5 r s t= 0 ; 1 3 #2 a= 1 ; 1 4 #2 b= 1 ; 1 5 #2 a= 1 0 ; 1 6 #2 $finish; 1 7 end

1 8 1 9 always #1 c l k++; 2 0 2 1 // use of iff makes sure 2 2 // triggered

that block does not get due to posedge of clk when rst == 1 2 3 always_ff @ ( posedge c l k iff r s t == 0 or posedge r s t ) 2 4 begin : A D D E R 2 5 if ( r s t ) begin 2 6 s u m <= 0 ; 2 7 p a r i t y <= 0 ; 2 8 $display ( "Reset is asserted BLOCK 1") ; 2 9 end else begin 3 0 s u m <= b+ a ; 3 1 p a r i t y <= ^ ( b+ a ) ; 3 2 end 3 3 end
3 4 3 5 // To

show how iff affected in earlier code @( posedge c l k or posedge r s t ) 3 7 begin 3 8 if ( r s t ) begin 3 9 $display ( "Reset is asserted BLOCK 2") ; 4 0 end 4 1 end
3 6 always_ff 4 2 4 3 endmodule You could download file always_ff_process.sv here

Simulator Output
@0 clk = 0 rst = 0 a = xx b = xx sum = xx parity = x Reset is asserted BLOCK 1 Reset is asserted BLOCK 2 @1 clk = 1 rst = 1 a = xx b = xx sum = 00 parity = 0 @2 clk = 0 rst = 1 a = xx b = xx sum = 00 parity = 0 Reset is asserted BLOCK 2 @3 clk = 1 rst = 1 a = xx b = xx sum = 00 parity = 0 @4 clk = 0 rst = 1 a = xx b = xx sum = 00 parity = 0 Reset is asserted BLOCK 2 @5 clk = 1 rst = 1 a = xx b = xx sum = 00 parity = 0 @6 clk = 0 rst = 0 a = xx b = xx sum = 00 parity = 0 @7 clk = 1 rst = 0 a = xx b = xx sum = xx parity = x @8 clk = 0 rst = 0 a = 01 b = xx sum = xx parity = x @9 clk = 1 rst = 0 a = 01 b = xx sum = xx parity = x @10 clk = 0 rst = 0 a = 01 b = 01 sum = xx parity = x @11 clk = 1 rst = 0 a = 01 b = 01 sum = 02 parity = 1 @12 clk = 0 rst = 0 a = 0a b = 01 sum = 02 parity = 1 @13 clk = 1 rst = 0 a = 0a b = 01 sum = 0b parity = 1

Continuous assignments In verilog only net data types can be driven by continous assignment, In systemVerilog this restriction is removed and any data type can be driven using continuous assignment. Nets can be driven by multiple continuous assignments or by a mixture of primitives and continuous assignments. Variables can only be driven by one continuous assignment or one primitive output.

Copyright 1998-2013 Deepak Kumar Tala - All rights reserved Do you have any Comment? mail me at:deepak@asic-world.com

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Process Part-I

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