RMIT VIETNAM SGSC

EEET2366
Two-Stage OPAMP Design Project

Instructor: Thanh Pham Chi

Student number: s3425733
Student name: Huynh Pham Ngoc Tram

9/18/2013

Contents
Contents ............................................................................................................................... 1
Table of illustrations ............................................................................................................ 3
1

Introduction ................................................................................................................. 1

Hand calculation .......................................................................................................... 1

2.1

Typology ................................................................................................................ 1

2.2

Specifications ......................................................................................................... 2

2.3

Calculations ............................................................................................................ 2

Channel length modulation.......................................................................................... 6

Simulation Optimization ............................................................................................. 8

4.1

Create test bench .................................................................................................... 8

4.2

Simulation optimization ......................................................................................... 9

4.3

Unity gain buffer simulation ................................................................................ 13

4.4

Input common mode range .................................................................................. 14

4.5

Open loop gain ..................................................................................................... 16

4.6

Transfer function and phase margin .................................................................... 19

4.7

Slew rate ............................................................................................................... 24

Third try ..................................................................................................................... 25

5.1

Sweep for sizing values ....................................................................................... 26

5.2

Unity gain buffer .................................................................................................. 27

5.3

Input common mode range .................................................................................. 27

5.4

Open loop gain ..................................................................................................... 28

5.4.1

Output swing ................................................................................................. 28

5.4.2

Offset input voltage ....................................................................................... 28

5.5
6

Transfer function and phase margin .................................................................... 29

Fourth try ................................................................................................................... 29

6.1

Unity gain buffer .................................................................................................. 30

6.2

Input common mode range .................................................................................. 31

6.3

Open loop gain ..................................................................................................... 31

6.3.1

Offset input voltage ....................................................................................... 31

6.3.2

Output swing ................................................................................................. 32

6.4

Transfer function and phase margin .................................................................... 32

6.4.1

Check for zero input offset ............................................................................ 32

6.4.2

Check for gain, phase margin........................................................................ 33

6.5

Slew rate ............................................................................................................... 34

6.6

Power ................................................................................................................... 35

Summary.................................................................................................................... 36

Discussion .................................................................................................................. 36

Conclusion ................................................................................................................. 37

Table of illustrations
Figure 1: OPAMP typology................................................................................................. 1
Figure 2: Specifications ....................................................................................................... 2
Figure 3: Technology information ....................................................................................... 2
Figure 4: First calculation results ........................................................................................ 5
Figure 5: First simulation schematic ................................................................................... 5
Figure 6: Test bench ............................................................................................................ 6
Figure 7: First run (gain = 55.64dB) ................................................................................... 6
Figure 8: Channel Modulation ............................................................................................. 6
Figure 9: Characterization PMOS (up) and NMOS (down)................................................ 7
Figure 10: Test bench for simulation and optimization ...................................................... 8
Figure 11: Simulation setup (test bench 1) .......................................................................... 9
Figure 12: ADE setup .......................................................................................................... 9
Figure 13: Calculate the phase margin (up) and unity gain frequency (down) ................. 10
Figure 14: Output results of the phase margin (left) and the output voltage in kV (right) 10
Figure 15: First simulation optimization ........................................................................... 11
Figure 16: Simulation setup with optimized variables ...................................................... 11
Figure 17: Simulation result (with optimized sizes).......................................................... 12
Figure 18: Characteristic of the optimized circuit (using calculator without testing on
specific test bench) ............................................................................................................ 12
Figure 19: Test bench (schematic) .................................................................................... 13
Figure 20: Transient simulation setup ............................................................................... 13
Figure 21: Output waveform ............................................................................................. 14
Figure 22: Output waveforms (zoom in) ........................................................................... 14
Figure 23: ICMR ADE setup ............................................................................................. 15
Figure 24: Plot Vout/Vin ................................................................................................... 15
Figure 25: ICMR simulation result .................................................................................... 16
Figure 26: Open loop gain test bench ................................................................................ 16
Figure 27: Simulation profile ............................................................................................ 17
Figure 28: Output waveform ............................................................................................. 17
Figure 29: Simulation profile setup ................................................................................... 18
Figure 30: Input offset ....................................................................................................... 18
Figure 31: Values on the linear region of the opamp ........................................................ 19
Figure 32: Schematic view (test bench) ............................................................................ 19
Figure 33: Simulation profile (testing Vout = 0 when Vin = 0) ........................................ 20
Figure 34: Check for Vout when Vin dc is zero (result) ................................................... 20
Figure 35: Transfer function and phase margin test bench ............................................... 21

Figure 36: AC sweep simulation profile ........................................................................... 21

Figure 37: Adding bode plot .............................................................................................. 22
Figure 38: Adding phase plot (in deg) ............................................................................... 22
Figure 39: Output gain (yellow curve) in dB and phase (green curve) ............................. 22
Figure 40: Use marker to find the frequency where gain is 0dB ...................................... 23
Figure 41: Setup 2nd marker at frequency 5.4041MHz ..................................................... 23
Figure 42: Result waveforms with markers....................................................................... 23
Figure 43: Slew rate test bench ......................................................................................... 24
Figure 44: Input voltage source (vpulse) setup ................................................................. 24
Figure 45: Transient analysis setup ................................................................................... 25
Figure 46: Input and output square voltages ..................................................................... 25
Figure 47: Parametric sweeping ........................................................................................ 26
Figure 48: New gain output ............................................................................................... 26
Figure 49: Devices sizes .................................................................................................... 26
Figure 50: Output voltage still follows the input voltage closely ..................................... 27
Figure 51: Input common mode range .............................................................................. 27
Figure 52: ICMR results .................................................................................................... 28
Figure 53: Output voltage swings from -2.498V (at -2.5V) and 2.341V (at 2.5V) .......... 28
Figure 54: Input offset decrease to 30.92uV ..................................................................... 28
Figure 55: Zero offset (the offset is -331.3nV) ................................................................. 29
Figure 56: Gain, Unity gain frequency and phase margin ................................................ 29
Figure 57: Sweep variables again ...................................................................................... 29
Figure 58: Optimization variables ..................................................................................... 30
Figure 59: Change the simulation profile .......................................................................... 30
Figure 60: Unity gain buffer (output still closely follows input) ...................................... 30
Figure 61: ICMR ............................................................................................................... 31
Figure 62: ICMR satisfy .................................................................................................... 31
Figure 63: Offset input voltage 114.7uV ........................................................................... 31
Figure 64: Output swing from -2.499V to 2.339V ............................................................ 32
Figure 65: Change the compensate voltage source ........................................................... 32
Figure 66: Input offset -177.92nV ..................................................................................... 33
Figure 67: Transfer function (72.3571dB) and phase margin (60.55deg), unity BW
(9.55948MHz) ................................................................................................................... 33
Figure 68: Slew rate without load ..................................................................................... 34
Figure 69: Slew rate with load ........................................................................................... 34
Figure 70: Summary slew rate ........................................................................................... 34
Figure 71: Simulation profile ............................................................................................ 35

Figure 72: Calculator setup ............................................................................................... 35

Figure 73: Consuming power maximum 4.881mW .......................................................... 35
Figure 74: Design summary .............................................................................................. 36

Table 1: Parameters table .................................................................................................... 8

Table 2: DC sweeping schematic setup ............................................................................... 9
Table 3: ICMR simulation output table ............................................................................. 16

EEET2366

Two-stage OPAMP design

1 Introduction
The purpose of this paper is to report the procedure and results when designing a twostage Operational Amplifier (OPAMP) using Cadence EDA tools and the process design
kit (PDK) AMI 0.6u library. The design must meet a set of specifications (See section
2.2)
Based on the provided OPAMP typology, the OPAMPs transistor sizes, base current,
miller capacitor will be calculated by hand. Then those results will be placed into the
schematic for the very first simulation. Any changes in the provided typology are
welcomed. If the calculated transistor sizes and values (bias current and miller capacitor)
cannot produce the required specifications (as they are most likely cannot), students are
required to optimize the schematic to produce the final OPAMP which satisfies all
specifications.
During the design process, there are some design choices which have been made:
1. Change the length of the design from minimum 600nm to 1.8um
2. Using simulation tool and parametric sweeping to optimize the OPAMP instead of
doing by hand
The final design has the maximum transistor size of 150um (M6), the capacitor Cc of
2.5pF and the bias current Ib of 30uA and meets all the design specifications.

2 Hand calculation
2.1 Typology

Figure 1: OPAMP typology

EEET2366

Two-stage OPAMP design

2.2 Specifications

Figure 2: Specifications

Figure 3: Technology information

2.3 Calculations
Compensation capacitance CC
CC 0.22CL = 0.22*10pF = 2.2pF
Choose CC = 3pF.
Current I5
I5 = SR*CC = 10*106*3*10-12 = 30*10-6 = 30uA
W3/L3 (Size of transistor M3)

EEET2366

Two-stage OPAMP design

S3 = 30*10-6/ ((37*10-6) * (2.5 1.5 0.94 + 0.73)2) = 1.23

Choose S3 = S4 = 2
Checking the minor pole

Cox is 2.4f/um2, we have:

P3 = -

Trans-conductance gm1

gm1 = 5*2*106*3*10-12 = 15*10-6 = 94.25uS

W1/L1 (Size of transistor M1)
S1 = S2 = (gm1)2/(2*K1*I1) = (94.25*10-6)2/ (2*115*10-6*15*10-6) = 2.575
Choose S1 = S2 = 3.

VDS5

VDS5 = (-1) (-2.5) -

W5/L5 (Size of transistor M5)

S5 = 2*30*10-6/ [(115*10-6)*(0.475)2] = 2.31

Choose S5 = S8= 3
3

0.475V

EEET2366

Two-stage OPAMP design

Trans-conductance gm6
gm6 10*gm1 = 10*94.25uS = 942.5uS
Tran-conductance gm4

47.12uS

W6/L6 (Size of transistor M6)

S6 = (942.5*2)/40.8 = 32.66
Choose S6 = 33
Current through M6 (I6)

I6 = (942.5*10-6)2 / (2*37*10-6*33) = 363.76uA

Power dissipation

Pdiss = (30uA + 363.76uA) * 5V = 1.97mW

W7/L7 (Size of transistor M7)

S7 = (363.76uA /30uA)*3 = 36.376(Choose S7 = 37)

Check output requirements
Voutm = VDS7(sat) =

< 1V

Check voltage gain (Assume l6 =l2 = 0.06 and l7 = l4 = 0.08)

EEET2366

Two-stage OPAMP design

Av = (2*94.25*10-6*942.5*10-6)/(30*10-6*(0.06+0.08)2* 363.76*10-6) = 830.61V/V =

58.39dB
To obtain Av = 70dB, we need I6 = 87.6uA. From that we do the hand optimization and
have:
S6 = 137
S4 = 23.45
Device

First calculation

M1, M2
M3,M4
M5,M8
M6
M7
Cc
IB
Av

3
2
3
35
35
3pF
30uA
58.39dB

Hand
optimization
3
23.45
3
137
8.76
3pF
30uA
72dB

Figure 4: First calculation results

Figure 5: First simulation schematic

Create the following test bench:

5

Width
5.4u
42.15u
5.4u
246.6u
15.75u
3p
30uA

EEET2366

Two-stage OPAMP design

Figure 6: Test bench

Figure 7: First run (gain = 55.64dB)

3 Channel length modulation

In previous calculations, we assume the channel length modulation to be 0.06 and 0.07
for NMOS and PMOS respectively. However, this number is much bigger in the current
library. Doing characterization process presented in lab7, we have:
The result of channel modulation is:
NMOS
0.123

PMOS
2.3
Figure 8: Channel Modulation

This number is too big and therefore will decrease the gain significantly. To solve this,
we need to find a way to decrease the channel length modulation.

EEET2366

Two-stage OPAMP design

Figure 9: Characterization PMOS (up) and NMOS (down)

1

Channel modulation is the shortening of the effective length

of the MOSFET. Since the current is reversely proportional
to the length, if the length is shortening, the current will get
bigger where it is expected to be constant (at saturation
region). If the shortening amount (L) is much smaller than
the length L, the effect will be less noticeable. Therefore, in

Picture source: http://www.onmyphd.com/?p=channel.length.modulation

EEET2366

Two-stage OPAMP design

this lab, instead of using the minimum length 0.6um we will use the length of 1.8um.

4 Simulation Optimization
To optimize the design, we will create the following test bench and use parametric sweep
to estimate the parameters of the design which will satisfy the specifications.

4.1 Create test bench

Figure 10: Test bench for simulation and optimization

For later usage, the widths of the transistors will be set as variables as the table below.
Variable
Width of M1,M2
Width of M3,M4
Width of M6
Width of M7

Name
w12
w34
w6
w7

Table 1: Parameters table

EEET2366

Two-stage OPAMP design

Figure 11: Simulation setup (test bench 1)

4.2 Simulation optimization

To optimize the design, we will perform a DC sweep of the size parameters as follow:
Variable
Width of M1,M2
Width of M3,M4
Width of M6
Width of M7

Name
w12
w34
w6
w7

Sweep range
1.5u to 30u
1.5u to 10u
1.5u to 300u
1.5u to 200u

Table 2: DC sweeping schematic setup

Figure 12: ADE setup

Total steps
5
5
5
5

EEET2366

Two-stage OPAMP design

We also monitor the phase margin:

And unity gain frequency

Figure 13: Calculate the phase margin (up) and unity gain frequency (down)

Choose this set of parameters

Figure 14: Output results of the phase margin (left) and the output voltage in kV (right)

There are multiple combination of the sizes of M1, M2, M3, M4, M6, M7 which can
produce the gain bigger than or equal the required gain (72dB) and the phase margin
bigger than 60deg.Choosing one parameter set among those and perform the individual
checking (for open loop gain, phase margin, slew rate).

10

EEET2366

Two-stage OPAMP design

Observation: At this point, based on this graph (Figure 14) we can draw three
observations as follow:
-

If we increase the size of M7, the phase margin will be increased.

The gain will changed based on different sizes combination. With the same
M1, M2 size if size of M6, M7 is different, the gain would be vastly different
(increase from some hundred volts to some kilovolts). The gain is the result of
the combination of the sizes. Its not simply increase M1, M2 and the gain will
increase.
From my observation, if the gain is big (for most of the cases I came upon), the
unity gain frequency is most likely to be big and the phase margin is most
likely to be very small.

For first simulation, to ensure the phase margin will not be violated, I chose a set of
transistor sizes which produce the gain of 4kV (72dB) and the phase margin (through the
calculator) is more than 63 deg. The parameters set are:
Device
M1, M2
M3,M4
M6
M7

Sweeping size
8.6u
3.6u
76u
51u

Chosen size
9u
3.6u
75.6u
50.4u

Figure 15: First simulation optimization

Simulate again using the same test bench while configure the variables to their optimized
values (See Figure 16):

Sweep AC without using parametric sweep

Optimized variables
Unity BW and phase margin results

Figure 16: Simulation setup with optimized variables

11

EEET2366

Two-stage OPAMP design

Figure 17: Simulation result (with optimized sizes)

Since we monitor the gain, unity gain frequency and the phase margin using expression
of the calculator on the simulation profile, we can see the rough values of those specs as
follow:
Gain
Unity gain bandwidth
Phase margin (using calculator)

71.79dB
5.388MHz
61.92 DEG

Figure 18: Characteristic of the optimized circuit (using calculator without testing on specific test bench)

These results above is the raw calculation and might not be very accurate (which I
observe later that they are indeed not very accurate in comparison to the values calculated
using specific test benches), therefore we will use specific test benches to test for the
specifications.
There are in total 5 test benches:
-

Unity gain buffer: This test bench is used to test the output in time domain
when the OPAMP acts as a unity gain buffer. This also tests for any distortion
during OPAMP operation. For a good OPAMP, we expect the output to be
closely follows the input. In the ideal case, we expect the output to be exactly
identical to the input voltage.
Common mode range: This test bench is used to test the input common mode
range of the circuit. We will sweep the input voltage from Vss to Vdd and
12

EEET2366

Two-stage OPAMP design

observe the fraction of Vout/Vin. This ratio is expected to be as closely to 1 as

possible when the input range is [-1.5V, 1V].
Open loop gain: This test bench is designed to test the open loop gain of the
design. We will plot Vout vs. Vin and estimate the slope of the linear region of
this graph. This slope is the estimated open loop gain of the design. Most
important, this test bench will be used to estimate the input offset of the
OPAMP (the input value where the output is 0).
Transfer function and phase margin: As the name indicated, this test bench
will plot the transfer function of the OPAMP and base on that plot, calculate
the phase margin of the design.
Slew rate: This test bench will input a step input voltage source and observe
the output (when the OPAMP performs as a unity-gain buffer). The slopes on
the rising edge and falling edge of the output plot are the slew rates of the
design.

4.3 Unity gain buffer simulation

Figure 19: Test bench (schematic)

We will test the transient behavior of the amplifier by run a transient simulation in 10ms
(10 cycles), plot the input and output voltages. The setup is as below:

Sweep trans without using parametric sweep

Optimized variables

Figure 20: Transient simulation setup

13

EEET2366

Two-stage OPAMP design

Figure 21: Output waveform

Figure 22: Output waveforms (zoom in)

Comments:
The output follows the input very closely (nearly no distortion) which means the
amplifier successfully performs as a unity gain buffer.

4.4 Input common mode range

Sweep dc voltage of input voltage from -2.5V to 2.5V using the same test bench as
before.
14

EEET2366

Two-stage OPAMP design

DC analysis

Figure 23: ICMR ADE setup

Figure 24: Plot Vout/Vin

15

EEET2366

Two-stage OPAMP design

Figure 25: ICMR simulation result

Vin (V)
-2.39
-1
1.5
2.5

Gain (times)
1.040289 (max)
1.000054
999.6048
839.5372(min)
Table 3: ICMR simulation output table

Comment:
The gain is very close to 1 during the input common mode range -1V to 1.5V, therefore
the design satisfy the specification.

4.5 Open loop gain

To measure the open loop gain, we use a dc input voltage source and sweep its value
from -2.5 to 2.5V while observing the behavior of the output.

Figure 26: Open loop gain test bench

16

EEET2366

Two-stage OPAMP design

Next, setup the simulation profile as follow:

Figure 27: Simulation profile

The output is as follow:

Figure 28: Output waveform

17

EEET2366

Two-stage OPAMP design

The voltage swing from -2.498V (at -2.5V) to 2.346V (at 2.5V)
Next, the sweeping range will be changed to -5mV to 5mV with total steps of 100 to
zoom in to the transition part. The settings are captured as follow:

Figure 29: Simulation profile setup

Figure 30: Input offset

18

EEET2366

Two-stage OPAMP design

The input offset is measured where the output is 0. The value measured is 54.4203uV.
This is a good value consider the desired ideal value is 0.

Figure 31: Values on the linear region of the opamp

Gain = slope =

= 4589.6 V/V = 73.23dB

4.6 Transfer function and phase margin

First, we need to add a dc voltage in series with the input voltage source. The value of
this dc voltage source is the input offset and therefore is 54.4203uV. The setup is as
follow:

Figure 32: Schematic view (test bench)

19

EEET2366

Two-stage OPAMP design

Run this simulation again and check for the output voltage where the input voltage (dc) is
zero.

Figure 33: Simulation profile (testing Vout = 0 when Vin = 0)

Since Vout = 0 would be the ideal case, we accept Vout which is less than 100mV (when
there is no dc input voltage).

Figure 34: Check for Vout when Vin dc is zero (result)

When there is no dc input voltage, the output voltage in this case is 2.47mV < 100mV
(This means the voltage compensate Vos must have value -54.4203uV instead of
54.4203uV. However, at this state this mistake will not affect the results very much
because of two reasons: First the offset still less than 100mV therefore its effect will not
be noticeable. Second, this set of variables does not match the gain and slew rate
anyway). For 3rd and 4th try, the compensate voltage can reduce the offset to nano volts.
20

EEET2366

Two-stage OPAMP design

Now we are ready to perform observe the output voltage when the frequency changes.
Firstly setup the test bench as follow:

Figure 35: Transfer function and phase margin test bench

Then, create a simulation profile which sweeps the frequency of the input AC voltage
source from 100Hz to 100MHz.

Figure 36: AC sweep simulation profile

21

EEET2366

Two-stage OPAMP design

Then add the plot of Vout/Vin in dB by doing:

Figure 37: Adding bode plot

Figure 38: Adding phase plot (in deg)

The result is captured as follow:

Figure 39: Output gain (yellow curve) in dB and phase (green curve)

The low frequency gain of the Opamp is around 70.94dB.

This value is smaller than the value calculated in section 4.5 since choosing two points in
the linear range by hand would be very inaccurate.
To find the phase margin, first we need to find the unity gain frequency. To do this, we
can use the marker and find the value where the gain is 0dB:
22

EEET2366

Two-stage OPAMP design

Figure 40: Use marker to find the frequency where gain is 0dB

Then we setup another marker to mark the phase (in deg) at the unity gain frequency.

Figure 41: Setup 2nd marker at frequency 5.4041MHz

The result is captured as follow:

Figure 42: Result waveforms with markers

The phase at unity gain frequency is -118.2432deg.

The phase margin is 180deg + (-118.2432deg) = 61.7568deg (meets the specification)

23

EEET2366

Two-stage OPAMP design

4.7 Slew rate

Create a test bench as follow:

Figure 43: Slew rate test bench

Remember to use the pulse voltage source and configure it as follow:

Figure 44: Input voltage source (vpulse) setup

24

EEET2366

Two-stage OPAMP design

Running a transient simulation to 600ns (3 cycles) and plotting the input and output
voltages with the following setups:

Figure 45: Transient analysis setup

The result is captured below:

Figure 46: Input and output square voltages

Choosing Cc = 3pF gives the slew rate of 0.99V/us which is very low compared to the
requirement.

5 Third try
Since the first set of parameters did not produce the expected output, we try to sweep the
values again using wider range:
25

EEET2366

Two-stage OPAMP design

5.1 Sweep for sizing values

Doing the parametric sweep again using the following settings:

Figure 47: Parametric sweeping

The output gain spectrum is as follow:

Figure 48: New gain output

Choose the gain of 72.93dB, the sizes are

Device
M1, M2
M3,M4
M6
M7
Cc
Ib

Chosen size
30.6u
3.6u
76u (choose 75.6u)
51u (choose 50.4u)
3pF
30uA
Figure 49: Devices sizes

Now we do all the checking again!

26

EEET2366

Two-stage OPAMP design

5.2 Unity gain buffer

Figure 50: Output voltage still follows the input voltage closely

5.3 Input common mode range

Figure 51: Input common mode range

27

EEET2366

Two-stage OPAMP design

Vin (V)
-2.5V
-2.39
-1
1.5
2.5

Gain (times)
999.3933mV
1.007471V (max)
999.9477mV
999.666mV
812.2921(min)
Figure 52: ICMR results

5.4 Open loop gain

5.4.1 Output swing

Figure 53: Output voltage swings from -2.498V (at -2.5V) and 2.341V (at 2.5V)

5.4.2 Offset input voltage

Figure 54: Input offset decrease to 30.92uV

28

EEET2366

Two-stage OPAMP design

5.5 Transfer function and phase margin

Apply the same process, we check for zero offset and the gain, unity gain frequency and
phase margin:

Figure 55: Zero offset (the offset is -331.3nV)

Unity gain frequency, low frequency gain and phase margin

Gain
Unity gain frequency
Phase margin

71.3dB
8.65203MHz
53DEG

Figure 56: Gain, Unity gain frequency and phase margin

Again, the phase margin and the gain do not match specification.

6 Fourth try
Since the phase margin will be increased once we increase the size of M7, we choose
another set of sizes as follow:

Figure 57: Sweep variables again

29

EEET2366

Two-stage OPAMP design

Device
M1, M2
M3,M4
M6
M7
Cc
Ib

Chosen size
22.87u (choose 22.95u)
3.6u
150.75u(choose 150u)
100.75u (choose 100u)
3pF
30uA
Figure 58: Optimization variables

Run the simulations again and the slew rate does not satisfy. After some changing (all by
hand), new parameters are:
Device
M1, M2
M3,M4
M6
M7
Cc
Ib

Chosen size
22.95u
3.6u
150u
100u
2.5pF
30uA
Figure 59: Change the simulation profile

Run the simulations again to check the specs.

6.1 Unity gain buffer

Figure 60: Unity gain buffer (output still closely follows input)

30

EEET2366

Two-stage OPAMP design

6.2 Input common mode range

Figure 61: ICMR

Vin (V)
-2.5
-1
1.5
2.5

Gain (times)
0.9996982
1.000022
0.999586
0.8151529(min)
Figure 62: ICMR satisfy

6.3 Open loop gain

6.3.1 Offset input voltage

Figure 63: Offset input voltage 114.7uV

31

EEET2366

Two-stage OPAMP design

6.3.2 Output swing

Figure 64: Output swing from -2.499V to 2.339V

6.4 Transfer function and phase margin

6.4.1 Check for zero input offset
Changing the compensate voltage source to 114.7uV, we have:

Figure 65: Change the compensate voltage source

32

EEET2366

Two-stage OPAMP design

Figure 66: Input offset -177.92nV

6.4.2 Check for gain, phase margin

Figure 67: Transfer function (72.3571dB) and phase margin (60.55deg), unity BW (9.55948MHz)

33

EEET2366

Two-stage OPAMP design

6.5 Slew rate

Figure 68: Slew rate without load

Figure 69: Slew rate with load

No load
With load
Rising
Falling
Rising
Falling
(0.8986471V +
(1.00876V +
(0.7066462V
(0.725376V +
0.8637669V)/(200.1635 0.946065V)/(100.1889 +0.6919052V)/(200.151 0.2733954V)/(100.1238
us 200.012us) =
us 100.0008us) =
us - 200.0324us) =
us 100.0336us) =
11.63V/us
10.392V/us
11.79V/us
11.07V/us
Figure 70: Summary slew rate

34

EEET2366

Two-stage OPAMP design

6.6 Power
Using the same test bench as unity gain buffer case, we setup the simulation profile as
follow:

Figure 71: Simulation profile

We calculate the power by setup the calculator as follow

Figure 72: Calculator setup

The power curve is captured as below:

Figure 73: Consuming power maximum 4.881mW

35

EEET2366

Two-stage OPAMP design

7 Summary
Device
M1, M2
M3,M4
M6
M8, M5
M7
Cc
Ib
ICMR
Unity gain at -1V input
Unity gain at 1.5V input
Unity gain frequency
Low frequency gain
Phase margin
Slew rate
No load
With load
Power

Chosen size
22.95u
3.6u
150u
5.4u
100u
2.5pF
30uA
1.000022
0.999586
9.55948MHz
72.3571dB
60.55deg
Rising
11.63V/us
11.79V/us
4mW

Falling
10.392V/us
11.07V/us

Figure 74: Design summary

8 Discussion
After changing sizes and values trying to optimize the design to match the specifications,
there are some observations/conclusions as follow:
1. Increase the minimum length of the transistors can help to increase the overall
gain because the channel length modulation effect would be less noticeable.
2. The slew rate depends heavily on Cc (can increase 10x when the capacitor changes
from 3pF to 2.5pF). The slew rate where there is not load is smaller than the slew
rate with load and the slew rate on the rising edge is bigger than the slew rate on
falling edge.
3. To some extend increase size of M1, M2 can increase the gain. However, when
increase too much; it might come into the combination (with other sizes of M6,
M7, M3, m4) where the gain is very small.
4. Choose a parameter set in which size of M7 is big will ensure a good phase
margin.

36

EEET2366

Two-stage OPAMP design

9 Conclusion
This paper has successfully designed a twostage OPAMP which can meet the design
specifications stated at the beginning of the report. Since we try to keep the sizes of the
transistors to be as small as possible, the achieved specifications neatly meet the design
specifications. As a result, good layout is necessary because if the layout is well-done, the
post layout simulation can produce the same or even better specifications. On the other
hand, bad layout might result an OPAMP which fails to meet the design specifications.

37