8086 INTERNAL ARCHITECTURE:

As shown by the block diagram the 8086 CPU is divided into two independent functional parts, the bus interface unit or BIU, and the execution unit or EU. Dividing the work between these two units speed up processing. The BIU sends out addresses, fetches instructions from memory, reads data from ports and memory, and writes data to ports and memory. In other words, the BIU handles all transfer of data and addresses on the buses for the execution unit. The EXECUTION UNIT of the 8086 tells the BIU where to fetch instructions or data from, decodes instructions and executes instructions.

The Execution Unit: The EU contains control circuitry which directs internal operations. A decoder in the DU translates instructions fetched from memory into a series of actions which the EU carries out. The EU has a 16-bit arithmetic logic unit which can add subtract, AND, OR, XOR, increment, decrement, complement, or shift binary numbers. Flag Register:

A flag is a flip flop which indicates some condition produced by the execution of an instruction or controls certain operations of the EU. A16-bit flag register in the EU contains nine active flags. Six of the nine flags are used to indicate some condition produced by an instruction. The six conditional flags in the group are the carry flag (CF), the parity flag(PF), the auxiliary carry flag (AF), the zero flag (ZF), the sign flag (SF) and the overflow flag (OF). The flag register also contains 3 control flags, theses flags are different from the six conditional flags described above in the way they are set or reset. The conditional flags are set or reset by the EU on the basis of the results of some arithmetic or logic operation. The control flags are deliberately set or reset

with some specifi instructions you put in your program. The three control flags are the trap flag (TF), which is used for single stepping through a program; the interrupt flag (IF), which is used to allow or prohibit the interruption of a program; and the direction flag (DF), which is used with string instructions. General Purpose Registers: In the CPU, registers are used store information temporarily. The information can be one or two bytes of data, or the address of data. In 8088/8086 general-purpose registers can be accessed as either16-bit or 8-bit registers. All other registers can be accessed as full 16-bit registers.

The bits of the registers are numbered in descending order:

The advantage for using internal registers for the temporary storage of data is that, since the data is already in the EU, it can be accessed much more quickly than it could be accessed in external memory.

The BIU: The Queue:

The DIU fetches up to six instruction bytes for the following instructions. These prefetched bytes are stored in a first-in-first-out register set called a queue. Fetching the next instruction while the current one executes is called pipelining.

Physical Address And Logical Address: Every memory location has two kinds of address - physical and logical. A physical address is the 20-bit value that uniquely identifies each byte location in the Megabyte memory space. These may range from 0 to FFFFF Hex. All exchanges between the CPU and memory components use this physical address. Programs deal with logical, rather than physical, addresses. A logical address consists of a segment base value and an offset value. For any given memory location, the segment base value locates the first byte of the containing segment and the offset value is the distance, in bytes, of the target location from the beginning of the segment. OFFSET:

Note from the figure that the offset or the displacement is the distance above the start of the segment.

Physical Address Generation:

A segment register holds the upper 16 bits of the starting address. The code segment register for example holds the upper 16 bits of the starting address for the segment from which the BIU is currently fetching instruction code bytes. The BIU always inserts zeros for the lowest 4 bits (nibble) of the 20-bit starting address for a segment (Program boundaries). After appending a zero to the segment address the offset is added to the generated value. This is how the physical address is generated.

Default Segments and Offset Address:

The microprocessor has a set of rules that apply to segments whenever memory is addressed. These rules, define the segment register and offset register combinations.

Instruction Pointer: The code segment register holds the upper 16 bits of the starting address of the segment from which the BIU is currently fetching instruction code bytes. The instruction pointer register holds the 16-bit address, or offset, of the next code byte within this code segment.

The CS register points to the base or start of the current code segment. The IP contains the distance or offset from this base address to the next instruction byte to be fetched . Figure shows how the 16-bit offset in IP is added to the 16-bit segment base address in CS to produce the 20-bit physical address. Notice that the two 16-bit numbers are not added directly in line, because the CS register contains only the upper 16-bits of the base address for the code segment. As we said before, the BIU automatically inserts zeros for the lowest 4 bits of the segment base address.

Stack Segment Register And Stack Pointer Register: The Stack

Stack is an area of memory for keeping temporary data.The stack is a section of memory set aside to store addresses and data while a subprogram is executing. PUSH - stores 16 bit value in the stack. POP - gets 16 bit value from the stack. Syntax for PUSH instruction: PUSH REG PUSH SREG PUSH memory PUSH immediate REG: AX, BX, CX, DX, DI, SI, BP, SP. SREG: DS, ES, SS, CS. memory: 16 bit variable, etc... immediate: 5, -24, 3Fh, 10001101b, etc...

Syntax for POP instruction: POP REG POP SREG POP memory REG: AX, BX, CX, DX, DI, SI, BP, SP. SREG: DS, ES, SS, (except CS). memory: 16 bit variable, etc...

Note that PUSH and POP work with 16 bit values only! That is the memory for the stack is word organized and 16 bit data format is used for saving. The stack uses LIFO (Last In First Out) algorithm, this means that if we push these values one by one into the stack: 1, 2, 3, 4, 5 the first value that we will get on pop will be 5, then 4, 3, 2, and only then 1.

PUSH and POP instruction are especially useful because we don't have too much registers to operate with, so here is a trick:

Store original value of the register in stack (using PUSH). Use the register for any purpose. Restore the original value of the register from stack (using POP).

Here is an example:

ORG 100h MOV AX, 1234h PUSH AX ; store value of AX in stack. MOV AX, 5678h ; modify the AX

value. POP AX value of AX. RET END ; restore the original

Another use of the stack is for exchanging the values, here is an example:

ORG 100h MOV AX, 1212h ; store 1212h in AX. MOV BX, 3434h ; store 3434h in BX

PUSH AX in stack. PUSH BX stack. POP AX value of BX. POP BX value of AX. RET END

; store value of AX ; store value of BX in

; set AX to original ; set BX to original

The exchange happens because stack uses LIFO (Last In First Out) algorithm, so when we push 1212h and then 3434h, on pop we will first get 3434h and only after it 1212h.

The stack memory area is set by SS (Stack Segment) register, and SP (Stack Pointer) register. Generally operating system sets values of these registers on program start. "PUSH source" instruction does the following:

Subtract 2 from SP register. Write the value of source to the address SS:SP.

"POP destination" instruction does the following:

Write the value at the address SS:SP to destination. Add 2 to SP register.

The current address pointed by SS:SP is called the top of the stack.

The 8086 allows you to set aside an entire 64K-byte segment as a stack. The upper 16 bits of the starting address for this segment are kept in the stack segment (SS) register. The stack pointer (SP) register in the execution unit holds the 16-bit offset from the start of the segment to the memory location where a word was most recently stored in the stack.

Segment and Offset Addressing Scheme Allows Relocation:

The complex scheme of segment plus offset addressing allows programs to be relocated in the memory system. A relocatable program is one that can be placed into any area of memory and executed without change. This is the ideal use of general-purpose computer systems in which not all machines contain the same memory area. This requires relocatable software and data.

Because memory is addressed within a segment by an offset address, the memory segment can be moved to any place in the memory system without changing any of the offset addresses. This is accomplished by moving the entire program, as a block, to a new area and then changing only the contents of the segment register. If an instruction is 4 byte above the start of the segment, its offset is 4. If the entire program is moved to a new area of memory, this offset address of 4 still points to 4 bytes above the start of the segment.

Inside the 8086 Central Processor Unit (CPU)

GENERAL PURPOSE REGISTERS

8086 CPU has 8 general purpose registers, each register has its own name: AX - the accumulator register (divided into AH / AL): 1. Arithmetic, logic and data transfer 2. One number must be in AL or AX 3. Multiplication & Division

For these instructions the accumulator has a special purpose, but is generally considered to be a multipurpose register.
BX - the base address register (divided into BH / BL).

It is known as the base register due to the fact that it is at times used to hold the base address of a location in the memory system in all versions of microprocessors.

CX - the count register (divided into CH / CL):

Apart from being a general purpose register The CX also serves as a counter register holding the count for different looping instructions.
DX - the data register (divided into DH / DL):

Apart from being a general purpose register DX also serves as a data register in different operations, like in multiplication it holds part of the result or part of the dividend before a division operation. The CPU uses it as a default register for such operations without informing the user.

SI - source index register: 1. Can be used for pointer addressing of data 2. Used as source in some string processing instructions 3. Offset address relative to DS DI - destination index register: 1. Can be used for pointer addressing of data 2. Used as destination in some string processing instructions 3. Offset address relative to ES BP - base pointer: 1. Primarily used to access parameters passed via the stack 2. Offset address relative to SS SP - stack pointer: 1. Always points to top item on the stack 2. Offset address relative to SS 3. An empty stack will had SP = FFFEh

SEGMENT REGISTERS
CS - points at the segment containing the current program. DS - generally points at segment where variables are defined. ES - extra segment register, it's up to a coder to define its usage. SS - points at the segment containing the stack. Although it is possible to store any data in the segment registers, this is never a good idea. The segment registers have a very special purpose - pointing at accessible blocks of memory. Segment registers work together with general purpose register to access any memory value. For example if we would like to access memory at the physical address 12345h (hexadecimal), we could set the DS = 1230h and SI = 0045h. This way we can access much more memory than with a single register, which is limited to 16 bit values. The CPU makes a calculation of the physical address by multiplying the segment register by 10h and adding the general purpose register to it (1230h * 10h + 45h = 12345h):

The address formed with 2 registers is called an effective address. By default BX, SI and DI registers work with DS segment register; BP and SP work with SS segment register. Other general purpose registers cannot form an effective address. Also, although BX can form an effective address, BH and BL cannot.

SPECIAL PURPOSE REGISTERS

IP - the instruction pointer: 1. Always points to next instruction to be executed 2. Offset address relative to CS IP register always works together with CS segment register and it points to currently executing instruction.

FLAGS REGISTER
Flags Register - determines the current state of the processor. They are modified automatically by CPU after mathematical operations, this allows to determine the type of the result, and to determine conditions to transfer control to other parts of the program. Generally you cannot access these registers directly.

1. Carry Flag (CF) - this flag is set to 1 when there is an unsigned overflow. For example when you add bytes 255 + 1 (result is not in range 0...255). When there is no overflow this flag is set to 0. 2. Parity Flag (PF) - this flag is set to 1 when there is even number of one bits in result, and to 0 when there is odd number of one bits. 3. Auxiliary Flag (AF) - set to 1 when there is an unsigned overflow for low nibble (4 bits). 4. Zero Flag (ZF) - set to 1 when result is zero. For non-zero result this flag is set to 0. 5. Sign Flag (SF) - set to 1 when result is negative. When result is positive it is set to 0. (This flag takes the value of the most significant bit.) 6. Trap Flag (TF) - Used for on-chip debugging. 7. Interrupt enable Flag (IF) - when this flag is set to 1 CPU reacts to interrupts from external devices. 8. Direction Flag (DF) - this flag is used by some instructions to process data chains, when this flag is set to 0 - the processing is done forward, when this flag is set to 1 the processing is done backward. 9. Overflow Flag (OF) - set to 1 when there is a signed overflow. For example, when you add bytes 100 + 50 (result is not in range 128...127).