CHAP 4 SPICE MOS MODELS

Q Q Q

DIODES NMOS and PMOS Transistors Approach Q Select a process i.e channel length driven acquire .MODEL card for NMOS and PMOS devices Q Enter the Schematic post design Q SPICE the VTC (.DC) and then Transient (.TRAN) Q accurate results demand we enter AD,AS, PD, and PS Q Layout the Design- DRC, extract and resimulate Q LVS to verify schematic against extracted layout
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C. Hutchens Chap 4 ECEN 4303 Handouts

Key SPICE MODEL Parameters

Q

DIODES
IS RS TT CJ MJ PB Is R T Cj0 mj saturation current Series contact resistance NOT dynamic resistance Transit time forward zero bias Cap Grading coiefficent exponent built in potential

C. Hutchens Chap 4 ECEN 4303 Handouts

SPICE MODEL Parameters

Q

MOS TRAN
VT0 VTX threshold where X = N or P mobility where X = n or p U0 X gate oxide thickness TOX tox LD LD gate drain (source) overlap GAMMA body threshold modulation parameter substate doping X = A or D for N or P MOS NSUB NX PHI |2F| surface strong inversion potential built in contact potential junction to bulk PB 0 CJ Cj0 zero bias bottom cap. for D-Bdy and S- Bdy CJSW Cj-sw0 zero bias side wall cap. for D-Bdy and S- Bdy LAMBDA 1/ recipocal forward early voltage 1/= VA RX RE Series S and D contact resistance X = S o D Grading coiefficent exponent junction bot. MJ mj MJSW mj-sw Grading coiefficent exponent junction sidewall CGD0 Cgd/W per unit width G-D and G-S overlap cap.

C. Hutchens Chap 4 ECEN 4303 Handouts

SPICE LEVEL MODELS

Q Q

Level 1 is primarily for academic discussion & Hand Calculations. Use Level 49 or BSIM3 or proprietary models Q This is required to handle short channel effects What are we using for hand analysis? Q VTO, kn (kn), to determine effect Ron (or desired W given L) Q CJ and CJSW along with AD, AS, PD and PS to calculate the added cap due to the depletion cap contributions. Q TOX along with the effective dielectric constant to determine Cgs. Note we will limp Cgs = WLCox. Q We need RS, RD and the poly sheet Res.in high speed design
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C. Hutchens Chap 4 ECEN 4303 Handouts

MODEL CARD EX 1

C. Hutchens Chap 4 ECEN 4303 Handouts

MODEL CARD EX 2

C. Hutchens Chap 4 ECEN 4303 Handouts

SPICE GUIDELINES
Calculate Rise and Fall times in advance. Know the order of magnitude of the answer. DIVIDE and Conquer approach. KISS Principle.(keep it simple,stupid) Use SPICE-spectre like a Bench Scope
Dont forget Body Ties when extracting.

C. Hutchens Chap 4 ECEN 4303 Handouts

LAYOUT EX

AD = AS = 7 X 4 = 28 2 PD = PS = 2 X 7 + 4 = 22 EX resistance of ploy looking into the ploy gate Rg = Rpolysheet [(2/4) + (1 + 4 + 2 )/( 2 )] Rg = Rpolysheet( 1/2 + 7/2) Note this diagram does NOT show a body tie!!
C. Hutchens Chap 4 ECEN 4303 Handouts
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Diffusion verse Active Pullup EX

L W Figure 1

Rsegment /2 = R/2n pp 237

Csegment =C/n

Time Delay Equations Diffusion Diffusion n

2

EX Lumped ploy line

= RC

(1)

t Lumped 2.2 = 2.2 RC

or

=Rsegment Csegment and the effective trise is 1/2. Lumped -Active or Passive RC

R = Rsheet-ployl/w, C = Csheet l w R = 30sq.(1000m/4um) = 7.5k C = 0.7fFd/um2 (1000um X 4um) = 280fF

t Lumped 2.2 = 2.2 RC V DD

W 2 kp V DD L2

(2)

COMPARE to Equation (1) to lumped we note a factor of 2, 2.1 vs. 1.05nS.

C. Hutchens Chap 4 ECEN 4303 Handouts

SPICE EXAMPLE
Beta matched inv vdd 1 0 3.3 .PROBE .op .include TSOS.lib m1 2 5 1 1 pFET w=30u l=2u pd=30u ps=30u + ad = 90p as= 90p m4 2 5 6 6 nFET w=15u l=2u pd=15u ps=15u + ad = 450p as= 45p Vin 5 0 dc -0 .dc vin 0 3.3 .05 .tran 0 3.3 0.1nS 1nS 1nS 20nS 50nS .end

*NEURAL SOS LOT 911 * *TYPICAL CASE PARAMETERS, 1.25-10 MICRON, T=25 DEGREES C ********* .MODEL NSS1_25U NMOS (LD=0.0E-7 XJ=1.0E-7 TOX=2.5E-8 + VTO=0.74 UO=376 NSUB=4.7E16 + UEXP=0.5 UCRIT=3.0E5 UTRA=0.5 + GAMMA=1.0 LAMBDA=0.05 NFS=1.0E11 + LEVEL=2 PHI=.6 CJ=0.0 MJSW=3.33E-1 + CJSW=6.0E-11 MJ=5.0E-1 + CGSO=2.80E-10 CGDO=2.80E-10 RSH=200 ) ********* .MODEL PSS1_25U PMOS (LD=0.0E-7 XJ=1.0E-7 TOX=2.5E-8 + VTO=-0.9 UO=204 NSUB=1.0E15 + GAMMA=1.1 UEXP=0.2 UCRIT=8.0E4 UTRA=0.5 + LAMBDA=0.035 NFS=1.0E11 + LEVEL=2 CJ=0.0E-4 MJSW=3.33E-1 + CJSW=3.0E-12 MJ=5.0E-1 + CGSO=2.8E-10 CGDO=2.8E-10 RSH=200 )

C. Hutchens Chap 4 ECEN 4303 Handouts

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SPICE as a Design Support Tool EXAMPLE

Approach 1. Synthesize logic 2. Determine transistor geomerties 3. Validate DC VTC curves with SPICE Noise margin logic 4. Estimate from geometries expected rise and fall times 5. Add appropriate loading and AD, AS, PD AND PS to transistors as required. 6. Using estimated raise and fall times select .TRAN values (one must use a faster pulse 5-10X, to test the gate than the gates expected performance. 7. Execute SPICE and use waveform viewer to measure tr and tf. 8. Modify Ws as required and repeat if necessary.
C. Hutchens Chap 4 ECEN 4303 Handouts
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Tapered Buffer EX

C. Hutchens Chap 4 ECEN 4303 Handouts

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Tappered Buffer

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