ACKNOWLEDGEMENT

We wish to take this opportunity to express our sincere gratitude and deep sense of
respect to our beloved Prof. Dr. K. PRAKASH, Principal, VAAGDEVI ENGINEERING
COLLEGE for making us available all the required assistance and for his support and inspiration
to carry out this project in the institute.
We extend our heartfelt thanks to Prof.Dr. D.V.KRISHNA REDDY, Head of the Dept
of ECE, VAAGDEVI ENGINEERING COLLEGE, for his constant support and giving
necessary guidance for completion of this project.
We express heartfelt thanks to the HOD of ECE Department and internal guide, Asst.
Prof. Mr.B.RAJANNA, for providing us with necessary infrastruture and there by giving us
freedom to carry out the project.
Finally we express our sincere thanks and gratitude to my family members, friends and
classmates for there magnanimous encouragment and outpouring there knowledge and
experience through thesis.

Submitted By
K.GOUTHAMI
AFREEN
P.MANASA
R.PREMCHAND

(10UK5A0409)
(10UK5A0402)
(10UK5A0403)
(09UK1A0480)

DECLARATION

We, the undersigned, declare that the mini project entitled POWER OPTIMIZATION
OF BIST CIRCUIT USING LOW POWER LFSR submitted in partial fulfillment for the
award of bachelor of degree in Electronics & Communication Engineering to Jawaharlal
Nehru Technological University is the work carried out by us.

Submitted By
K.GOUTHAMI
AFREEN
P.MANASA
R.PREMCHAND

(10UK5A0409)
(10UK5A0402)
(10UK5A0403)
(09UK1A0480)

CONTENTS
Name

Page No.

Abstract.. vi
List of Figures..vii
List of Tablesix
Chapter-1

Introduction...1
1.1 Project Motivation.1
1.2 Project Objectives..2
1.3 Thesis Outline........3

Chapter-2

Introduction to VLSI4
2.1 Overview of VLSI4
2.2 History of Scale Integration..5
2.3 Advantages of ICs Over Discrete Components..6
2.4 VLSI and Systems.6
2.4.1 VLSI Design Flow.7
2.5 Applications of VLSI........8
2.6 ASIC..9

Chapter-3

SOC Background........11
3.1 SOC Attributes....11
3.2 SOC Design Tools and Methodology....12
3.3 SOC Power Consumption ..14
3.4 SOC Manufacturing Processes.......14

3.5 SOC Test and Assembly....16

Chapter-4

Implementation Test..17
4.1 SOC Test Tools and Methodology....17
4.2 Built In Self-Test (BIST)...19
4.2.1 BIST Block Diagram..20
4.2.2 Modified clock Scheme..20
4.2.3 LP ATPG Scheme...21
4.2.4 LT-LFSR Scheme...21
4.3 BIST Architecture..23
4.3.1 Implementation of BIST.....24
4.3.2 Low Transition Test Pattern...25
4.3.3 Algorithm for LT-LFSR.25
4.4 BIST Pattern Generation Using LFSR......26

Chapter-5

Low Power Test Pattern Generation...30

5.1 Low Power Test Pattern .30
5.2 Technic for Low Power Test Pattern....31
5.3 Bench Mark Design Circuits34
5.4 Bus Translations .37

Chapter-6

Modelsim38
6.1 Introduction...38
6.2 The Modelsim GUI...38
6.3 New to Modelsim 40
6.4 Automating the Modelsim Simulation Process

...41

6.5 Script and Behavioral Verilog File42

Chapter-7

Results and Discussion43

7.1 Simulation Using Standard LFSR Pattern.43
7.2 Simulation Using LP-LFSSR.44
7.3 Power Consumption Using Standard LFSR Pattern......45
7.4 Power Consumption Using Low Power Pattern .....46
7.5 Power Consumption Comparison ..47

Chapter-8

Advantages and Applications....49

8.1 Advantages....49
8.2 Applications..49

Chapter-9

Conclusion..50

Chapter-10

Recommendations for Future Work ...51

Bibliography...52

ABSTRACT

LIST OF FIGURES
Figure

Page No.

2.4.1.1 VLSI Design Flow

3.2.1 IC Design Methodology

13

4.1.1 Test Methodology

17

4.2.1 IEEE 1146.1 Tap

19

4.2.1.1 BIST Block Diagram

20

4.3.1 BIST Archtecht

23

4.4.1 LFSR

26

4.4.2 Maximal Length LFSR

28

5.1.1 LP-LFSR

31

5.3.1 ISCAS-85 C432 27-Channel Interrupt Controller

34

5.3.2 ISCAS-85 C432 M1

37

5.3.3 ISCAS-85 C432 M2

37

5.3.4 ISCAS-85 C432 M3

37

5.3.5 ISCAS-85 C432 M4

37

5.3.6 ISCAS-85 C432

37

7.1.1 8-Bit LFSR

43

7.1.2 Maximal 8-Bit LFSR

44

7.2.1 LP-LFSR Pattern Simulation

44

7.3.1 Power Estimation Flow

45

LIST OF TABLES
Table

Page No.

3.4.1 ITRS Roadmap by Product

15

4.4.1 Present/Next State

27

5.4.1 Bus Translations

37

7.5.1 Power Consumption Comparison

48