MOSFET Device Physics and Operation

Rajaram Sivasubramanian Associate Professor ECE Department Thiagarajar College of Engineering Madurai-15

Contents
y Introduction y The MOS Capacitor
y Interface Charge y Threshold Voltage y MOS Capacitance

y Basic MOSFET Operation y Basic MOSFET Modeling

y Simple Charge Control Model y The Meyer Model y Velocity Saturation Model

y Capacitance Models y Comparison of Basic MOSFET Models

Contents
y Introduction y The MOS Capacitor
y Interface Charge y Threshold Voltage y MOS Capacitance

y Basic MOSFET Operation y Basic MOSFET Modeling

y Simple Charge Control Model y The Meyer Model y Velocity Saturation Model

y Capacitance Models y Comparison of Basic MOSFET Models

Introduction

y MOS structure controls the mobile charge in the channel

by capacitive coupling.

y FET
y y y

Conducting semiconductor channel Two ohmic contacts : source and drain Third contact : Gate

y Examples of FET

MOSFET y JFET y MESFET y HFET

y

MOSFET
y Insulator: SiO2 layer y For the applied gate voltage, y Charge carriers in channel constitute inversion charge y P type semiconductor - electrons y N type semiconductor holes y Charge carriers enter and exit the channel at Source & Drain

CMOS technology
y Bipolar y FET y MOSFET y CMOS
Analog circuits y Application: Audio circuit KHZ Wireless applications GHZ
y

y SOI y BiCMOS : Bipolar and CMOS

Contents
y Introduction y The MOS Capacitor
y Interface Charge y Threshold Voltage y MOS Capacitance

y Basic MOSFET Operation y Basic MOSFET Modeling

y Simple Charge Control Model y The Meyer Model y Velocity Saturation Model

y Capacitance Models y Comparison of Basic MOSFET Models

MOS Capacitor

For the applied gate voltage, y Induce Charge in metal y Induce counter charge in semiconductor constitute inversion charge y control the type of interface charge

Contents
y Introduction y The MOS Capacitor
y Interface Charge y Threshold Voltage y MOS Capacitance

y Basic MOSFET Operation y Basic MOSFET Modeling

y Simple Charge Control Model y The Meyer Model y Velocity Saturation Model

y Capacitance Models y Comparison of Basic MOSFET Models

Flat-band voltage

Flat Band Voltage,

y At stationary condition- no current flow from Source

to Drain y Fermi level in, y Semiconductor Constant y Between semiconductor & metal

y P-type semiconductor, V<VFB<0 y N-type semiconductor, V>VFB>0

Important terms
y Potential in the semiconductor y Energy separation between Ef and Ei y Surface Concentration of holes and Electrons y Potential distribution y Electric field at si/sio2 interface y Total charge y Applied Voltage

Energy separation between Ef and Ei , Surface concentration of holes and electrons, Potential distribution,

Electric field at si/sio2 layer, Where, Total charge, Applied voltage,

y Strong inversion

y Depletion and the weak inversion

y Flat band Condition

y Accumulation Mode

Contents
y Introduction y The MOS Capacitor
y Interface Charge y Threshold Voltage y MOS Capacitance

y Basic MOSFET Operation y Basic MOSFET Modeling

y Simple Charge Control Model y The Meyer Model y Velocity Saturation Model

y Capacitance Models y Comparison of Basic MOSFET Models

How Thresholding Occurs

G (+) 0V S
n+
2F
E

2/8

VG < VT :

D 0.1V
n+
2F

As gate voltage increases, the E field pushes holes down creating a widening depletion layer and exposing negative ionic charge to balance the positive Gate charge.

NMOS
NS

p substrate NB

VG > VT : Surface reaches equi-potential (with 2F across dep layer) and electrons now flow in from S to form a conducting film or channel on the silicon surface. As VG increases further, dep layer does not grow wider, but balancing charge comes from a strengthening of the channel on the surface.

Surface doping concentration

F =

kT NB Ln n q i

NB

Bulk concentration

xj
Junction depth

With 2F across dep layer, the surface is as negative as the Bulk is positive, which conveniently defines VT.

In SPICE, 2F is PHI , typically 0.8V.

THRESHOLD AND BODY EFFECT

Components of Threshold Voltage

G (+) 0V S
tox
n+
2F
width= Xd

3/8

D 0.1V
n+
2F

Xd =

2ksi0 (Bias) qNB

Depletion layer width

QB = qNB Xd

Depletion layer ionic charge in coulombs/m2. Gate oxide capacitance in Farads/m2.

NMOS B
VT = 2F + QB + MS Cox
across gate oxide

p substrate NB

Cox =

kox0 tox

MS is a component (some tenths of a volt) due to workfunction difference between the gate material and the silicon. It is a fixed value, and need not concern us, because we can independently adjust VT by ion implantation. The QB term is voltage dependent, a function of the (Bias) that determines Xd. The nominal threshold is VTO. It occurs when VDB=VSB=0 such that Bias = 2F (across Xd) and . . .

across dep layer then:

VT 0 = 2F +

QB0 + MS Cox

where

QB0 = qNB

2ksi0 (2F ) = 2ksi0qNB (2F ) qNB

Threshold voltage
|

Threshold voltage

Final threshold voltage

y

By application of bias voltage V shifted to V-VB [threshold referred to potential shifted by VB]

Contents
y Introduction y The MOS Capacitor
y Interface Charge y Threshold Voltage y MOS Capacitance

y Basic MOSFET Operation y Basic MOSFET Modeling

y Simple Charge Control Model y The Meyer Model y Velocity Saturation Model

y Capacitance Models y Comparison of Basic MOSFET Models

MOS capacitance
CMOS capacitance is,

The semiconductor capacitance is,

where,CSO is Semiconductor capacitance at flat band condition given by,

Equivalent circuit of MOS capacitance

z Where Cs is given by, Cs = Cfc +Cd z The depletion layer capacitance is given by,

Where depletion layer width,

At Low frequency, neglect the effect of RGR and Rs

Where,

At high frequency,

At low frequency, the induced charge per unit area is,

The Flat band capacitance is,

Then VFB is simply equal to applied voltage corresponding to this capacitance.

Contents
y Introduction y The MOS Capacitor
y Interface Charge y Threshold Voltage y MOS Capacitance

y Basic MOSFET Operation y Basic MOSFET Modeling

y Simple Charge Control Model y The Meyer Model y Velocity Saturation Model

y Capacitance Models y Comparison of Basic MOSFET Models

Electric fields in the MOSFET

MOS structure in depletion

MOS structure in inversion

N-channel MOSFET with Vgs<Vt

n-Channel MOSFET With VGS > VT , small VDS

n-Channel MOSFET With VGS > VT , large VDS

MOSFET Regions of Operation

>

>

nMOS Cutoff
y No channel y Ids = 0 y Vgs 0
Vgs = 0

+ s n+

+ d n+

Vgd

p-type body b

nMOS Linear
y Channel forms y Current flows from d to s
y e- from s to d
Vgs > Vt Vgd = Vgs g

y Ids increases with Vds y Similar to linear resistor

Vgs > Vt

+ s n+

+ d n+

Vds = 0

p-type body b

+ s n+

+ d n+

Vgs > Vgd > Vt Ids 0 < Vds < Vgs-Vt

p-type body b

I-V Characteristics
y In Linear region, Ids depends on

How much charge is in the channel? y How fast is the charge moving?
y

Channel Charge
y MOS structure looks like parallel plate capacitor while operating in inversion y Gate oxide channel

polysilicon gate W tox n+ L p-type body n+ SiO2 gate oxide (good insulator, ox = 3.9)

+ + Cg Vgd drain source Vgs Vs Vd channel + n+ n+ Vds p-type body

gate Vg

Channel Charge
y MOS structure looks like parallel plate capacitor while

operating in inversion
y

Gate oxide channel

Cox = ox / tox

y Qchannel = CV

y C = Cg = oxWL/tox = CoxWL y V = Vgc Vt = (Vgs Vds/2) Vt

polysilicon gate W tox n+ L p-type body n+ SiO2 gate oxide (good insulator, ox = 3.9)

+ + Cg Vgd drain source Vgs Vs Vd channel + n+ n+ Vds p-type body

gate Vg

nMOS Saturation
y Channel pinches off y Ids independent of Vds y We say current saturates y Similar to current source
Vgs > Vt

+ -

+ -

Vgd < Vt

d Ids Vds > Vgs-Vt

n+ p-type body b

n+

nMOS I-V Summary

y nMOS Characteristics

Contents
y y

Introduction The MOS Capacitor

y y y y

Interface Charge Threshold Voltage MOS Capacitance MOS Charge Control Model

y y

Basic MOSFET Operation Basic MOSFET Modeling

y Simple Charge Control Model y The Meyer Model y Velocity Saturation Model

y y

Capacitance Models Comparison of Basic MOSFET Models

Basic MOSFET modeling

Gradual channel approximation(GCA) y Analytical, semi analytical MOSFET models y Electrostatic problem can be expressed in terms of 1-D Poisson's equation y Poisson equation determines the vertical charge density profile under the gate and charge transport equation for the channel y Allows to determine channel potential and charge profile

Contd.,
y y

2-terminal device- 1D Poisson's equation

MOSFET-2D Poisson's equation Reason,,,,,

electric field

y Geometric effects y Lateral electric field component perpendicular to the vertical

GCA valid for MOSFET,

the vertical field

y Assume E in the lateral direction of the channel is much less than

GCA invalid for Saturation region

Contd.,
y For high speed and low power applications,

3-simple MOSFET models

y Simple charge control model(SCCM) y Meyer model(MM) y Velocity Saturation Model(VSM)

Basic Models: Levels 1-3

y

Gradual channel approximation is valid for long channel MOSFETs

y Ratio between the gate length and the vertical distance of the space charge

region from the gate electrode is large (aspect ratio) y When biased in saturation, the GCA become invalid near the drain
y

Large lateral field gradient that develops

y How the models Level 1, 2, and 3 deal with saturation is the difference

among them

Simple Charge Control Model (Level 1)

y y y

Developed at a time when the MOSFET gate lengths were typically tens of m long. Assume constant mobility Mobile inversion charge, like the parallel plate expression but taking into account potential variation from drain

y y

Variation of depletion layer charge along the channel is negligible Expression relies on GCA so it is only applicable for nonsaturated part of the channel

Simple Charge Control Model (Level 1)

y

Threshold voltage given by

y y

Threshold voltage can be adjusted by doping or by using different gate metals (work function, flat band voltage) Strong dependence on substrate bias (Body plot) Slope of plot gives bodyeffect parameter =(2sNa)1/2/ci

Simple Charge Control Model (Level 1)

y y y

Assuming constant electron mobility

I ds W n q n s F

F is the magnitude of the electric field Integrating over the gate length

Simple Charge Control Model (Level 1)

y

Channel conductance

Transconductance

y Large electron mobilities y Large gate insulator capacitance

=Wnci/L, the transconductance parameter

y Large gate width to length ratios

sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

Meyer (I-V) Model (Level 2)

y

Inclusion of both inversion and depletion charges

Saturation voltage is obtained using pinch off condition of ns=0

sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

Velocity Saturation Model (Level 3)

y

Saturation current is better described in short channel devices in terms of saturation of the carrier drift velocity Electric field near the drain becomes sufficiently high
y Two piece model y Sodini model y Empirical velocity field relationship

Use simple charge control model below saturation

Contents
y y

Introduction The MOS Capacitor

y y y y

Interface Charge Threshold Voltage MOS Capacitance MOS Charge Control Model

y y

Basic MOSFET Operation Basic MOSFET Modeling

y Simple Charge Control Model y The Meyer Model y Velocity Saturation Model

y y

Capacitance Models Comparison of Basic MOSFET Models

Comparison of Basic Models y All models coincide at small drain

y

source voltages In saturation SCCM gives the highest current

y Long channel, low doped devices

Meyer Model, effect of including variation in depletion charge (dash)

y Long channel, moderate doping level

VSM, effect of velocity saturation (dot)

y Reasonable estimate for short channel

devices, without other short channel effects (DIBL, CLM)

Capacitance Models
Storedchargein devices
Gateelectrode Conductingchannel Depletionlayers

y y

Distinguish between parasitic capacitance elements and intrinsic transistor capacitance elements Capacitance models
y Meyer: Derivative of intrinsic gate charge with respect to terminal voltages y Ward Dutton: Assign inversion charge to source and drain terminals, and

depletion charge to substrate terminal

Meyer Capacitance Models

Inversionchargedominatesfor CGS (gatesourcecapacitance) andCGD (gatedraincapacitance) instronginversion Thegatesubstratecapacitance CGB inthesubthresholdregime, depletionchargeisdominant Stronginversion,longchannel Meyercapacitances VSAT=VGT isthesaturation voltageinSCCM,the capacitancesatsaturationare foundbyreplacingVDS=VSAT

Meyer Capacitance Models

VDS=VSAT in saturation

Contd.,
|

Three lumped capacitances between intrinsic terminals,

Contribution of inversion charge to the gate charge is,

Where,

In SCCM,
|

For non-saturation region,

Long channel Meyer capacitances are,

At saturation Voltage, Vsat=VGT

In MM
y Depletion charge,

y Subthreshold capacitances,

In VSM,
|

Capacitances in the saturation region in case of VSM model are found by,

[With condition of VGT>VDS and replace VGT by VSAT.]

WardDutton model
y an analysis of the charge distribution in the channel versus the

terminal bias voltages y problem is simplified by assigning the distributed charges to the various intrinsic terminals y the mobile charge QI of a MOSFET is divided into a source charge QS = FpQI and a drain charge QD = (1 Fp)QI, where Fp is a partitioning factor y The depletion charge QB under the gate is assigned to the MOSFET substrate terminal. The total gate charge QG = QI QB = QS QD QB.

WardDutton model contd...

y

we have introduced a set of intrinsic capacitance elements CXY , the so-called transcapacitances, defined by

For the four-terminal MOSFET, the WardDutton Description leads to a total of 16 transcapacitances. This set of 16 elements can be organized as follows in a 4 4 matrix, a so-called indefinite admittance matrix

WardDutton model contd...

Non-quasi-static modeling
y For very high-frequency operation of the MOSFET,

comparable to the inverse carrier transport time of the channel (non-quasi-static (NQS) regime), we have to consider the temporal relaxation of the inversion and depletion charges. y quasi-static assumption (QSA), in which an instantaneous charging of the inversion layer is assumed. Hence, circuit simulations will fail to accurately predict the performance of high-speed circuits.

Non-quasi-static modeling contd

y The channel of a MOSFET is analogous to a bias-dependent

distributed RC network

Non-quasi-static modeling contd..

y Elmore equivalent circuit can be viewed as a first step

toward an NQS model. The Elmore resistance RElmore is calculated from the channel resistance in strong inversion as

Non-quasi-static modeling contd

y The overall relaxation time for channel charging and

discharging can be written as a combination of the contributions due to drift and diffusion as follows:

MOSFET Capacitances

MOSFET Capacitances

Advanced Models
BerkleyShortChannelIGFETModel(BSIM)
StillbasedonGCAwithnumerousempiricalfixestomaintainthe requiredaccuracy Hundredsofdeviceparametersasaresult

Forexample:BSIM3addressesthephysicaleffectsintothe sub100nmregime
Featuresbuiltindependenceondimensionalandprocessing parameters
Gatelengthandwidth(L,W) Gateoxidethickness(di) Sourceanddraindopingjunctiondepth(Xj) Substratedopingprofile(Nsub(x,y))

DifferentMOSFETstructures(LDDetc.)

UptoseveralversionsofBSIM4 (oftenusedbyindustry)

Advanced Models
BSIM3FeaturesInclude: Majorhighfieldandshortchanneleffects
Mobilityreductionowingtoverticalfield Carriervelocitysaturation(Sodini) DIBL ChannelLengthModulation Substratecurrent Subthresholdcurrent Parasiticresistanceeffects

Improvedconvergenceproperties

Introduction
PSpice And AIMSpice

AIMSpice

M. Shur, Introduction to Electronic Devices, John Wiley and Sons, 1996, pg. 397.

CMOS Fabrication
y CMOS transistors are fabricated on silicon wafer y Lithography process similar to printing press y On each step, different materials are deposited or etched y Easiest to understand by viewing both top and cross-section

of wafer in a simplified manufacturing process

Inverter Cross-section
y Typically use p-type substrate for nMOS transistor

Requires n-well for body of pMOS transistors y Several alternatives: SOI, twin-tub, etc.
y
A GND Y VDD SiO2 n+ diffusion n+ n+ p substrate nMOS transistor pMOS transistor p+ n well p+ p+ diffusion polysilicon metal1

Well and Substrate Taps

y Substrate must be tied to GND and n-well to VDD y Metal to lightly-doped semiconductor forms poor connection

called Shottky Diode y Use heavily doped well and substrate contacts / taps
A GND Y VDD

p+

n+

n+ p substrate

p+ n well

p+

n+

substrate tap

well tap

Inverter Mask Set

y Transistors and wires are defined by masks y Cross-section taken along dashed line

GND nMOS transistor substrate tap pMOS transistor well tap

VDD

Fabrication Steps
y Start with blank wafer y Build inverter from the bottom up y First step will be to form the n-well

Cover wafer with protective layer of SiO2 (oxide) y Remove layer where n-well should be built y Implant or diffuse n dopants into exposed wafer y Strip off SiO2
y

p substrate

Oxidation
y Grow SiO2 on top of Si wafer
y

900 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate

Photoresist
y Spin on photoresist

Photoresist is a light-sensitive organic polymer y Softens where exposed to light

y

Photoresist SiO2

p substrate

Lithography
y Expose photoresist through n-well mask y Strip off exposed photoresist

Photoresist SiO2

p substrate

Etch
y Etch oxide with hydrofluoric acid (HF)
y

Seeps through skin and eats bone; nasty stuff!!!

y Only attacks oxide where resist has been exposed

Photoresist SiO2

p substrate

Strip Photoresist
y Strip off remaining photoresist
y

Use mixture of acids called piranah etch

y Necessary so resist doesnt melt in next step

SiO2

p substrate

n-well
y n-well is formed with diffusion or ion implantation y Diffusion

Place wafer in furnace with arsenic gas y Heat until As atoms diffuse into exposed Si
y

y Ion Implanatation

Blast wafer with beam of As ions y Ions blocked by SiO2, only enter exposed Si
y
SiO2 n well

Strip Oxide
y Strip off the remaining oxide using HF y Back to bare wafer with n-well y Subsequent steps involve similar series of steps

n well p substrate

Polysilicon
y Deposit very thin layer of gate oxide
y y

< 20 (6-7 atomic layers)

y Chemical Vapor Deposition (CVD) of silicon layer

Place wafer in furnace with Silane gas (SiH4) y Forms many small crystals called polysilicon y Heavily doped to be good conductor

Polysilicon Thin gate oxide n well p substrate

Polysilicon Patterning
y Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon Thin gate oxide n well p substrate

Self-Aligned Process
y Use oxide and masking to expose where n+ dopants should

be diffused or implanted y N-diffusion forms nMOS source, drain, and n-well contact

n well p substrate

N-diffusion
y Pattern oxide and form n+ regions y Self-aligned process where gate blocks diffusion y Polysilicon is better than metal for self-aligned gates because

it doesnt melt during later processing

n+ Diffusion

n well p substrate

N-diffusion
y Historically dopants were diffused y Usually ion implantation today y But regions are still called diffusion

n+

n+ n well p substrate

n+

N-diffusion
y Strip off oxide to complete patterning step

n+

n+ n well p substrate

n+

P-Diffusion
y Similar set of steps form p+ diffusion regions for pMOS

source and drain and substrate contact

p+ Diffusion

p+

n+

n+ p substrate

p+ n well

p+

n+

Contacts
y Now we need to wire together the devices y Cover chip with thick field oxide y Etch oxide where contact cuts are needed

Contact

Thick field oxide p+ n+ n+ p substrate p+ n well p+ n+

Metallization
y Sputter on aluminum over whole wafer y Pattern to remove excess metal, leaving wires

M e ta l

Metal Thick field oxide p+ n+ n+ p substrate p+ n well p+ n+

Layout
y Chips are specified with set of masks y Minimum dimensions of masks determine transistor size (and

hence speed, cost, and power) y Feature size f = distance between source and drain
y

Set by minimum width of polysilicon

y Feature size improves 30% every 3 years or so y Normalize for feature size when describing design rules y Express rules in terms of = f/2
y

E.g. = 0.3 m in 0.6 m process

Simplified Design Rules

y Conservative rules to get you started

Thank you