AT91SAM9263-EK Evaluation Board Rev.

B
...................................................................................................................

User Guide

6341D–ATARM–30-Sep-09
 Table of Contents

Section 1
Overview .................................................................................................................... 1-1
1.1 Scope................................................................................................................................. 1-1
1.2 How to Identify the Kit BOM Revision ................................................................................ 1-1
1.3 How to Identify the PCB Revision ...................................................................................... 1-2
1.4 How to Identify the SAM9263 Silicon Revision .................................................................. 1-2
1.5 NAND Flash Access Issue................................................................................................. 1-3
1.6 Deliverables ....................................................................................................................... 1-3
1.7 AT91SAM9263-EK Evaluation Board Rev. B .................................................................... 1-4

Section 2
Setting Up the AT91SAM9263-EK Board Rev. B....................................................... 2-1
2.1 Electrostatic Warning ......................................................................................................... 2-1
2.2 Requirements..................................................................................................................... 2-1
2.3 Layout ................................................................................................................................ 2-1
2.4 Powering Up the Board...................................................................................................... 2-4
2.5 Backup Power Supply........................................................................................................ 2-4
2.6 Getting Started................................................................................................................... 2-4
2.7 AT91SAM9263-EK Block Diagram .................................................................................... 2-5

Section 3
Board Description....................................................................................................... 3-1
3.1 AT91SAM9263 Microcontroller .......................................................................................... 3-1
3.2 AT91SAM9263 Block Diagram .......................................................................................... 3-4
3.3 Memory .............................................................................................................................. 3-5
3.4 Clock Circuitry.................................................................................................................... 3-5
3.5 Reset Circuitry ................................................................................................................... 3-5
3.6 Shutdown Controller .......................................................................................................... 3-5
3.7 Power Supply Circuitry....................................................................................................... 3-5
3.8 Remote Communication .................................................................................................... 3-5
3.9 Audio Stereo Interface ....................................................................................................... 3-6
3.10 User Interface .................................................................................................................... 3-6
3.11 Debug Interface ................................................................................................................. 3-6
3.12 Expansion Slot ................................................................................................................... 3-6
3.13 PIO Usage ......................................................................................................................... 3-7

Section 4

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6341D–ATARM–30-Sep-09
Table of Contents (Continued)

Configuration .............................................................................................................. 4-1

4.1 Configuration Jumpers and Straps .................................................................................... 4-1

Section 5
Schematics................................................................................................................. 5-1
5.1 Schematics ........................................................................................................................ 5-1

Section 6
Warning ...................................................................................................................... 6-1
6.1 BMS Signal Sampling ........................................................................................................ 6-1

Section 7
Revision History ......................................................................................................... 7-1
7.1 Revision History ................................................................................................................. 7-1

ii AT91SAM9263-EK Evaluation Board Rev. B User Guide

6341D–ATARM–30-Sep-09
 Section 1
Overview

1.1 Scope
The AT91SAM9263-EK evaluation kit enables the evaluation of and code development for applications
running on an AT91SAM9263.
This guide focuses on the AT91SAM9263-EK board Rev. B as an evaluation platform.

1.2 How to Identify the Kit BOM Revision

Table 1-1. AT91SAM9263-EK History

AT91SAM9623 Boot from Boot from
Kit BOM Schematics PCB Silicon DataFlash® on-board
Revision Revision Revision NAND Flash Device Mounted on Board Revision Card NAND Flash
001..003 A A MN21B = Samsung® K9F2G08U0M-PCB0 A yes no
004..006 B B MN21B = Samsung K9F2G08U0M-PCB0 A yes no
007 B B MN21B = Micron® MT29F2G08AACWP B yes yes
008..on C B MN21B = Micron MT29F2G08AACWP B yes yes

The BOM (bill of material) revision level is tagged on the kit box as shown below in Figure 1-1.

AT91SAM9263-EK Evaluation Board Rev. B User Guide 1-1

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Overview

Figure 1-1. AT91SAM9263-E Kit BOM

1.3 How to Identify the PCB Revision

The PCB revision can be clearly identified by looking at the board copper marking on the bottom side.
The last character of the series indicates the revision. Thus, If the series of characters ends with the let-
ter “B” (e.g. 63PC0608021B), your board is Rev. B.
For technical information on Revision A boards, refer to the corresponding User Guide, Atmel literature
number 6279, available on the Atmel web site.

1.4 How to Identify the SAM9263 Silicon Revision

The AT91SAM9263 MRL B (Marketing Revision Level B) parts are identified with a letter “B” on top of
the package as shown below:

Figure 1-2. AT91SAM92639263 MRL B

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 Overview

1.5 NAND Flash Access Issue

On the AT91SAM9263-EK with Kit BOM revision 007, the user can experience access errors when read-
ing or writing the NAND Flash device (MN21B).
This problem is due to disturbances on the chip select line. It can be fixed by the following:
„ replacing the resistor R139 (0 Ohms) by a 2.2 µH inductor
„ replacing the resistor R33 (470 K Ohms) by a 100 pF capacitor
This fix has been implemented on the AT91SAM9263-EK with Kit BOM revisions 008 and onward.
Alternatively, tying the NAND Flash chip select line to the ground fixes the problem.
This can be achieved simply by connecting pin 2 of J29 together with pin 30 of J23. However, this sim-
pler solution prevents some Flash modes from being operational because the accesses are then
controlled only through NANDOE and NANDWE. But, this does at least allow to boot WinCE and Linux
on the board from the NAND Flash.

1.6 Deliverables
The AT91SAM9263-EK package contains the following items:
„ an AT91SAM9263-EK board Rev. B
„ one A/B-type USB cable
„ one serial RS232 cable
„ one RJ45 crossed Ethernet cable
„ one CD-ROM that allows the user to begin evaluating the AT91 ARM® Thumb® 32-bit microcontroller
quickly.

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Overview

1.7 AT91SAM9263-EK Evaluation Board Rev. B

The board is equipped with an AT91SAM9263 (324-ball LFBGA package) together with the following:
„ 64 Mbytes of SDRAM memory
„ 4 Mbytes of PSRAM memory on EBI1
„ 256 Mbytes of NAND Flash memory
„ One NOR Flash memory (footprint only)
„ One 1.8” Hard disk connectors
„ One TWI serial memory
„ One USB device port interface
„ Two USB Host port interfaces
„ One RS232 serial communication port
„ One DBGU serial communication port
„ One serial CAN 2.0B communication port
„ One JTAG/ICE debug interface
„ One Ethernet 100-base TX with three status LEDs
„ One AC97 Audio DAC
„ One 3.5" 1/4 VGA TFT LCD Module with TouchScreen and backlight
„ One ISI connector (camera interface)
„ One Power LED and two general-purpose LEDs
„ Two user input push buttons
„ One Wakeup input push button
„ One reset push button
„ One DataFlash®/SD/SDIO/MMC card slot
„ One SD/SDIO/MMC card slot
„ One Lithium Coin Cell Battery Retainer for 12 mm cell size

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6341D–ATARM–30-Sep-09
 Section 2
Setting Up the AT91SAM9263-EK Board Rev. B

2.1 Electrostatic Warning

The AT91SAM9263-EK evaluation board Rev. B is shipped in protective anti-static packaging. The
board must not be subjected to high electrostatic potentials. A grounding strap or similar protective
device should be worn when handling the board. Avoid touching the component pins or any other metal-
lic element.

2.2 Requirements
In order to set up the AT91SAM9263-EK evaluation board Rev. B, the following items are needed:
„ the AT91SAM9263-EK evaluation board Rev. B itself
„ AC/DC power adapter (12V at 1A), 2.1 mm by 5.5 mm

2.3 Layout
See Figures 2-1 and 2-2.

AT91SAM9263-EK Evaluation Board Rev. B User Guide 2-1

6341D–ATARM–30-Sep-09
Setting Up the AT91SAM9263-EK Board Rev. B

Figure 2-1. AT91SAM9263-EK Layout - Top View

2-2 AT91SAM9263-EK Evaluation Board Rev. B User Guide

6341D–ATARM–30-Sep-09
 Setting Up the AT91SAM9263-EK Board Rev. B

Figure 2-2. AT91SAM9263-EK Layout - Bottom View

AT91SAM9263-EK Evaluation Board Rev. B User Guide 2-3

6341D–ATARM–30-Sep-09
Setting Up the AT91SAM9263-EK Board Rev. B

2.4 Powering Up the Board

The AT91SAM9263-EK requires 12V DC. DC power is supplied to the board via the 2.1 mm by 5.5 mm
socket J1. Coaxial plug center positive standard.

2.5 Backup Power Supply

The user has the possibility to plug a battery (3V Lithium Battery CR1225 or equivalent) in order to per-
manently power the backup part of the device.

2.6 Getting Started

The AT91SAM9263-EK evaluation board Rev. B is delivered with a CD-ROM that allows the user to
begin evaluation of the AT91 ARM Thumb 32-bit microcontroller quickly. Please refer to the AT91 web
site, http://www.atmel.com/products/AT91/, for the most up-to-date information on getting started with
the AT91SAM9263-EK.

2-4 AT91SAM9263-EK Evaluation Board Rev. B User Guide

6341D–ATARM–30-Sep-09
 Setting Up the AT91SAM9263-EK Board Rev. B

2.7 AT91SAM9263-EK Block Diagram

Figure 2-3. AT91SAM9263-EK Block Diagram

AT91SAM9263-EK Evaluation Board Rev. B User Guide 2-5

6341D–ATARM–30-Sep-09
 Section 3
Board Description

3.1 AT91SAM9263 Microcontroller

„ Incorporates the ARM926EJ-S™ ARM® Thumb® Processor
– DSP Instruction Extensions, Jazelle® Technology for Java® Acceleration
– 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer
– 200 MIPS at 180 MHz
– Memory Management Unit
– EmbeddedICE™, Debug Communication Channel Support
– Mid-level Implementation Embedded Trace Macrocell™
„ Bus Matrix
– Nine 32-bit-layer Matrix, Allowing a Total of 28.8 Gbps of On-chip Bus Bandwidth
– Boot Mode Select Option, Remap Command
„ Embedded Memories
– One 128 Kbyte Internal ROM, Single-cycle Access at Maximum Bus Matrix Speed
– One 80 Kbyte Internal SRAM, Single-cycle Access at Maximum Processor Bus Matrix Speed
– One 16 Kbyte Internal SRAM, Single-cycle Access at Maximum Bus Matrix Speed
„ Dual External Bus Interface (EBI0 and EBI1)
– EBI0 Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash®
– EBI1 Supports SDRAM, Static Memory and ECC-enabled NAND Flash
„ DMA Controller (DMAC)
– Acts as one Bus Matrix Master
– Embeds 2 Unidirectional Channels with Programmable Priority, Address Generation, Channel
Buffering and Control
„ Twenty Peripheral DMA Controller Channels (PDC)
„ LCD Controller
– Supports Passive or Active Displays
– Up to 24 bits per Pixel in TFT Mode, Up to 16 bits per Pixel in STN Color Mode
– Up to 16M Colors in TFT Mode, Resolution Up to 2048x2048, Supports Virtual Screen Buffers
„ 2D Graphics Accelerator
– Line Draw, Block Transfer, Polygon Fill, Clipping, Commands Queuing
„ Image Sensor Interface
– ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate
– 12-bit Data Interface for Support of High Sensibility Sensors
– SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format

AT91SAM9263-EK Evaluation Board Rev. B User Guide 3-1

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Board Description

„ USB 2.0 Full Speed (12 Mbits per second) Host Double Port
– Dual On-chip Transceivers
– Integrated FIFOs and Dedicated DMA Channels
„ USB 2.0 Full Speed (12 Mbits per second) Device Port
– On-chip Transceiver, 2,432-byte Configurable Integrated DPRAM
„ Ethernet MAC 10/100 Base-T
– Media Independent Interface or Reduced Media Independent Interface
– 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit
„ Fully-featured System Controller, including
– Reset Controller, Shutdown Controller
– Twenty 32-bit Battery Backup Registers for a Total of 80 Bytes
– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Double Real-time Timer
„ Reset Controller (RSTC)
– Based on Two Power-on Reset Cells, Reset Source Identification and Reset Output Control
„ Shutdown Controller (SHDWC)
– Programmable Shutdown Pin Control and Wake-up Circuitry
„ Clock Generator (CKGR)
– 32768Hz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent Slow
Clock
– 3 to 20 MHz On-chip Oscillator and Two Up to 240 MHz PLLs
„ Power Management Controller (PMC)
– Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
– Four Programmable External Clock Signals
„ Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
„ Debug Unit (DBGU)
– 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access
Prevention
„ Periodic Interval Timer (PIT)
– 20-bit Interval Timer plus 12-bit Interval Counter
„ Watchdog Timer (WDT)
– Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock
„ Two Real-time Timers (RTT)
– 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler
„ Five 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC, PIOD and PIOE)
– 160 Programmable I/O Lines Multiplexed with Up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
„ One Part 2.0A and Part 2.0B-compliant CAN Controller

3-2 AT91SAM9263-EK Evaluation Board Rev. B User Guide

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 Board Description

– 16 Fully-programmable Message Object Mailboxes, 16-bit Time Stamp Counter

„ Two Multimedia Card Interface (MCI)
– SDCard/SDIO and MultiMediaCard™ Compliant
– Automatic Protocol Control and Fast Automatic Data Transfers with PDC
– Two SDCard Slots Support on eAch Controller
„ Two Synchronous Serial Controllers (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
„ One AC97 Controller (AC97C)
– 6-channel Single AC97 Analog Front End Interface, Slot Assigner
„ Three Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation, Manchester
Encoding/Decoding
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
„ Two Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
– Synchronous Communications at Up to 90Mbits/sec
„ One Three-channel 16-bit Timer/Counters (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
„ One Four-channel 16-bit PWM Controller (PWMC)
„ One Two-wire Interface (TWI)
– Master Mode Support, All Two-wire Atmel® EEPROMs Supported
„ IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins
„ Required Power Supplies
– 1.08V to 1.32V for VDDCORE and VDDBU
– 3.0V to 3.6V for VDDOSC, VDDPLL and VDDIOP0 (Peripheral I/Os)
– 1.65V to 3.6V for VDDIOP1 (Peripheral I/Os)
– Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM0/VDDIOM1 (Memory I/Os)
„ Available in a 324-ball BGA Green Package

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 3-4
3.2

6341D–ATARM–30-Sep-09
Board Description

K
FC
-

5
3
3
MASTER SLAVE

L
E
E X

0
S
O
R L

C
S
0
B

SE

T
S PK1
M

R - X
M

K -T
DCEN K
X
10
Figure 3-1.

K
AG
D
D

C
C
H

TC
TS LK
TPYN
TPS0
BM 0-T S2
LC
LCDD
L DV -LC
LCDH YN DD
L DD YNC 23
LCDD TCC
ET C
ETXCK
ECXEN-ER
ER S- ETX CK
ERXE CO ER ERE
ET X0- -ER
EM 0-E RX DV
EMDC TX
EF DIO
HDPB
H A
HD PA

RT
JT CK

NT
TDRS
TDI
TMO
TC S
TST System JTAG Boundary Scan
EBI0_
Transc. Transc. D0-D15
Controller A0/NBS0
EBI0
A1/NBS2/NWR2
FIQ AIC CompactFlash A2-A15, A18-A20
In-Circuit ARM926EJ-S Processor LCD A16/BA0
IRQ0-IRQ1 10/100 Ethernet NAND Flash
Emulator ETM Controller USB A17/BA1
DRXD DBGU MAC OHCI NCS0
ICache DCache
DTXD PDC MMU NCS1/SDCS
TCM Interface 16K bytes 16K bytes LUT FIFO FIFO FIFO
PCK0-PCK3 NRD
AT91SAM9263 Block Diagram

Bus Interface NWR0/NWE

PMC ITCM DTCM DMA DMA DMA NWR1/NBS1
PLLRCA PLLA I D NWR3/NBS3
SDRAM SDCK, SDCKE
PLLRCB PLLB Controller RAS, CAS
XIN SDWE, SDA10
OSC Fast SRAM
XOUT Static NANDOE, NANDWE
80 Kbytes A21/NANDALE
WDT PIT Memory A22/NANDCLE
9-layer Bus Matrix Controller
VDDCORE NWAIT
A23-A24
AT91SAM9263 Block Diagram

VDDBU 20GPREG
ECC NCS4/CFCS0
PIOA Controller NCS5/CFCS1
RTT0 NCS3/NANDCS
XIN32 OSC A25/CFRNW
XOUT32 RTT1 PIOB
CFCE1-CFCE2
SRAM DMA D16-D31
SHDN PIOC
SHDWC 16 Kbytes Peripheral 20-channel NCS2
WKUP 2D
Bridge Peripheral 2-channel
PIOD EBI1_
POR DMA DMA Graphics D0-D15
RSTC EBI1 A0/NBS0
PIOE ROM Controller NAND Flash A1/NWR2
VDDCORE POR 128 Kbytes A2-A15/A18-A20
NRST A16/BA0
APB A17/BA1
SDRAM NCS0
Controller NRD
NWR0/NWE
DMA NWR1/NBS1
PDC PDC PDC PDC PDC Static SDCK
Memory A21/NANDALE
CAN USB A22/NANDCLE
MCI0 USART0 SPI0 PWMC TC0 AC97C SSC0 Image Controller
TWI Device NWAIT
MCI1 USART1 SPI1 TC1 SSC1 Sensor
USART2 TC2 Port NWR3/NBS3
Interface ECC NCS1/SDCS
Controller NCS2/NANDCS
D16-D31
SDCKE
RAS, CAS
Transc. SDWE, SDA10
NANDOE, NANDWE

3
2
3
3

A
O
M
CK

D2
F
D
Q

CK
C
M

O
IS
P
M

DAB
C 1

CD 3
NR X
DD

-D
-
TW
I_

DD P

9 X

C
R 2
TX 2
M CK
M SI

R
A
SP S0
AR 1
I_ C

0
0 D
0 F

PW
V N

-T A2
F

NP X
NPCS
NPCS
N CS

0- DX
CA NT
M -RK1
I S S Y NC

AC97C 2
AC97RS

0-
AC IOB
AC 97 K
T 0-T
I_ Y 1

TK 7TX
I

TD 0-TK1
R 0-R 1

DB
DA C B3
X S 2
D

RD 0-T F1

B0 TIO 2

M
D0 SI_
IS _HS D1
IS -IS CK

L
O T
O 0- LK
0_ K R

CT TW D
RTS0- K
TX 0- CK2
_

SC S0- TS
RD K0- TS
TI K0-
T A C
Q R F0- D1

PW
SI I

MCI0_, MCI_1 SPI0_, SPI1_

TC
I

AR
DM

AT91SAM9263-EK Evaluation Board Rev. B User Guide

 Board Description

3.3 Memory
„ 16 Kbytes of Internal data cache
„ 16 Kbytes of Internal instruction cache
„ 128 Kbytes of Internal ROM
„ 80 Kbytes of Internal single-cycle access high-speed SRAM
„ 16 Kbytes of Internal single-cycle access high-speed SRAM
„ 8 Mbytes of Atmel NOR Flash (not populated)
„ 64 Mbytes of SDRAM memory
„ 4 Mbytes of PSRAM (EBI1)
„ 256 Mbytes of NAND Flash memory
„ Atmel TWI serial EEPROM

3.4 Clock Circuitry

„ 16.36766 MHz standard crystal for the embedded oscillator
„ 32.768 kHz standard crystal for the slow clock oscillator

3.5 Reset Circuitry

„ Internal reset controller with bi-directional reset pin
„ External reset pushbutton

3.6 Shutdown Controller

„ Programmable shutdown and Wake-Up
„ Wake-up push button

3.7 Power Supply Circuitry

„ For dynamic power consumption, the AT91SAM9263 consumes a maximum of 50 mA on VDDCORE
at maximum speed in typical conditions (1.2V, 25°C), processor running full-performance algorithm.
„ On-board 1.2V high efficiency step-down Charge Pump regulator with shutdown control
„ On-board 3.3V switching regulator with shutdown control
„ On-board 5V switching regulator with shutdown control

3.8 Remote Communication

„ One RS232 serial communication port
„ One serial CAN 2.0B communication port via 3-position printed circuit terminal block
„ One USB V2.0 Full-speed Compliant, 12 Mbits per second (UDP)
„ Two USB Host ports V2.0 Full-speed Compliant, 12 Mbits per second (UHP)
„ One RMII Ethernet 100-base TX with three status LEDs

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Board Description

3.9 Audio Stereo Interface

„ One AC'97 2.3 compliant Codec (20-bit PCM DAC)
„ One 32-ohm Stereo Headset line-out
„ One stereo line input
„ One stereo electret microphone input
„ One mono 8-ohm amplified speaker

3.10 User Interface

„ Two user input push buttons
„ Two user green LEDs
„ One yellow power LED (can be also software controlled)
„ One 3.5" ¼ VGA display LCD with Touch Panel and white LED backlight
„ One ISI connector (camera interface)

3.11 Debug Interface

„ 20-pin JTAG/ICE interface connector
„ One Serial interface (DBGU COM Port) via RS-232 DB9 male socket

3.12 Expansion Slot

„ One DataFlash/SD/SDIO/MMC card slot
„ One SD/SDIO/MMC card slot
„ All unused I/Os of the AT91SAM9263 are routed to peripheral extension connectors (J24 and J25).
This allows the developer to add external hardware components or boards.

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 Board Description

3.13 PIO Usage

Table 3-1. PIO Controller A
I/O Line Peripheral A Peripheral B Peripheral Usage Powered by

SD/MMC/DATAFLASH SOCKET (J9) & TOUCH

PA0 MCI0_DA0 SPI0_MISO MCI0_DA0 or SPI0_MISO VDDIOP0
SCEEN CONTROLLER

SD/MMC/DATAFLASH SOCKET (J9) & TOUCH

PA1 MCI0_CDA SPI0_MOSI MCI0_CDA or SPI0_MOSI VDDIOP0
SCEEN CONTROLLER

SD/MMC/DATAFLASH SOCKET (J9) & TOUCH

PA2 SPI0_SPCK SPI0_SPCK VDDIOP0
SCEEN CONTROLLER

PA3 MCI0_DA1 SPI0_NPCS1 SD/MMC/DATAFLASH SOCKET (J9) VDDIOP0

PA4 MCI0_DA2 SPI0_NPCS2 SD/MMC/DATAFLASH SOCKET (J9) VDDIOP0

PA5 MCI0_DA3 SPI0_NPCS0 SD/MMC/DATAFLASH SOCKET (J9) VDDIOP0

PA6 MCI1_CK PCK2 SD/MMC SOCKET (J10) MCI1_CK VDDIOP0

PA7 MCI1_CDA SD/MMC SOCKET (J10) MCI1_CDA VDDIOP0

PA8 MCI1_DA0 SD/MMC SOCKET (J10) MCI1_DA0 VDDIOP0

PA9 MCI1_DA1 SD/MMC SOCKET (J10) MCI1_DA1 VDDIOP0

PA10 MCI1_DA2 SD/MMC SOCKET (J10) MCI1_DA2 VDDIOP0

PA11 MCI1_DA3 SD/MMC SOCKET (J10) MCI1_DA3 VDDIOP0

PA12 MCI0_CK SD/MMC/DATAFLASH SOCKET (J9) MCI0_CK VDDIOP0

PA13 CANTX PCK0 CAN BUS INTERFACE (J17) CANTX VDDIOP0

PA14 CANRX IRQ0 CAN BUS INTERFACE (J17) CANRX VDDIOP0

PA15 TCLK2 IRQ1 TOUCH SCREEN CONTROLLER (MN19) IRQ1 VDDIOP0

PA16 MCI0_CDB EBI1_D16 IMAGE SENSORS CONNECTORS (J23) PA16 as CTRL1 VDDIOM1
PA17 MCI0_DB0 EBI1_D17 IMAGE SENSORS CONNECTORS (J23) PA17 as CTRL2 VDDIOM1

PA18 MCI0_DB1 EBI1_D18 CAN INTERFACE (RXEN) PA18 as RXEN VDDIOM1

PA19 MCI0_DB2 EBI1_D19 CAN INTERFACE (RS) PA19 as RS VDDIOM1

PA20 MCI0_DB3 EBI1_D20 USB HOST B POWER MONITOR (MN17) PA20 as FLGB VDDIOM1

PA21 MCI1_CDB EBI1_D21 USB HOST B POWER CONTROL (MN17) PA21 as ENB VDDIOM1

PA22 MCI1_DB0 EBI1_D22 NAND FLASH (MN12B) PA22 as RDY/BSY VDDIOM1

PA23 MCI1_DB1 EBI1_D23 USB HOST B POWER MONITOR (MN17) PA23 as FLGA VDDIOM1

PA24 MCI1_DB2 EBI1_D24 USB HOST B POWER CONTROL (MN17) PA24 as ENA VDDIOM1

PA25 MCI1_DB3 EBI1_D25 USB DEVICE INTERFACE PA25 as USB_CNX VDDIOM1

PA26 TXD0 EBI1_D26 RS232 COM PORT (J15) TXD0 VDDIOM1

PA27 RXD0 EBI1_D27 RS232 COM PORT (J15) RXD0 VDDIOM1

PA28 RTS0 EBI1_D28 RS232 COM PORT (J15) RTS0 VDDIOM1

PA29 CTS0 EBI1_D29 RS232 COM PORT (J15) CTS0 VDDIOM1

PA30 SCK0 EBI1_D30 LCD PANEL (Power Control In) PA30 as PCI VDDIOM1

PA31 DMARQ0 EBI_D31 TOUCH SCREEN CONTROLLER (MN19) PA31 as BUSY VDDIOM1

AT91SAM9263-EK Evaluation Board Rev. B User Guide 3-7

6341D–ATARM–30-Sep-09
Board Description

Table 3-2. PIO Controller B

I/O Line Peripheral A Peripheral B Peripheral Usage Powered by

PB0 AC97FS TF0 AC97 CODEC (MN12) AC97FS VDDIOP0

PB1 AC97CK TK0 AC97 CODEC (MN12) AC97CK VDDIOP0

PB2 AC97TX TD0 AC97 CODEC (MN12) AC97TX VDDIOP0

PB3 AC97RX RD0 AC97 CODEC (MN12) AC97RX VDDIOP0

PB4 TWD RK0 TWI EEPROM (MN11) TWD / SDA VDDIOP0

PB5 TWCK RF0 TWI EEPROM (MN11) TWCK / SCL VDDIOP0

PB6 TF1 DMARQ1 VDDIOP0

PB7 TK1 PWM0 POWER LED CONTROL (DS3) PB7 or PWM0 VDDIOP0

PB8 TD1 PWM1 USER'S LED1 CONTROL (DS1) PB8 or PWM1 VDDIOP0

PB9 RD1 LCDCC LCD PANEL (backlight control) LCDCC VDDIOP0

PB10 RK1 PCK1 AC97 CODEC (MN12) Optional clock source PCK1 VDDIOP0
PB11 RF1 SPI0_NPCS3 TOUCH SCREEN CONTROLLER (MN19) SPI0_NPCS3 VDDIOP0

PB12 SPI1_MISO VDDIOP0

PB13 SPI1_MOSI VDDIOP0

PB14 SPI1_SPCK VDDIOP0

PB15 SPI1_NPCS0 VDDIOP0

PB16 SPI1_NPCS1 PCK1 VDDIOP0

PB17 SPI1_NPCS2 TIOA2 VDDIOP0

PB18 SPI1_NPCS3 TIOB2 VDDIOP0

PB19 VDDIOP0

PB20 VDDIOP0
PB21 VDDIOP0

PB22 VDDIOP0

PB23 VDDIOP0
PB24 DMARQ3 VDDIOP0

PB25 VDDIOP0

PB26 VDDIOP0

PB27 PWM2 VDDIOP0

PB28 TCLK0 VDDIOP0

PB29 PWM3 VDDIOP0

PB30 VDDIOP0

PB31 VDDIOP0

3-8 AT91SAM9263-EK Evaluation Board Rev. B User Guide

6341D–ATARM–30-Sep-09
 Board Description

Table 3-3. PIO Controller C

I/O Line Peripheral A Peripheral B Peripheral Usage Powered by

PC0 LCDVSYNC VDDIOP0

PC1 LCDHSYNC LCD PANEL LCDHSYNC VDDIOP0

PC2 LCDDOTCK LCD PANEL LCDDOTCK VDDIOP0

PC3 LCDDEN PWM1 LCD PANEL LCDDEN VDDIOP0

PC4 LCDD0 LCDD3 USER'S PUSH BUTTON (BP2) PC4 as RIGHT CLICK VDDIOP0

PC5 LCDD1 LCDD4 USER'S PUSH BUTTON (BP1) PC5 as LEFT CLICK VDDIOP0

PC6 LCDD2 LCDD5 LCD PANEL LCDD2 RED VDDIOP0

PC7 LCDD3 LCDD6 LCD PANEL LCDD3 RED VDDIOP0

PC8 LCDD4 LCDD7 LCD PANEL LCDD4 RED VDDIOP0

PC9 LCDD5 LCDD10 LCD PANEL LCDD5 RED VDDIOP0

PC10 LCDD6 LCDD11 LCD PANEL LCDD6 RED VDDIOP0

PC11 LCDD7 LCDD12 LCD PANEL LCDD7 RED VDDIOP0

PC12 LCDD8 LCDD13 LCD PANEL LCDD13 GREEN VDDIOP0

PC13 LCDD9 LCDD14 VDDIOP0

PC14 LCDD10 LCDD15 LCD PANEL LCDD10 GREEN VDDIOP0

PC15 LCDD11 LCDD19 LCD PANEL LCDD11 GREEN VDDIOP0

PC16 LCDD12 LCDD20 LCD PANEL LCDD12 GREEN VDDIOP0

PC17 LCDD13 LCDD21 LCD PANEL LCDD21 BLUE VDDIOP0

PC18 LCDD14 LCDD22 LCD PANEL LCDD14 GREEN VDDIOP0

PC19 LCDD15 LCDD23 LCD PANEL LCDD15 GREEN VDDIOP0

PC20 LCDD16 ETX2 VDDIOP0

PC21 LCDD17 ETX3 VDDIOP0

PC22 LCDD18 ERX2 LCD PANEL LCDD18 BLUE VDDIOP0

PC23 LCDD19 ERX3 LCD PANEL LCDD19 BLUE VDDIOP0

PC24 LCDD20 ETXER LCD PANEL LCDD20 BLUE VDDIOP0

PC25 LCDD21 ERXDV ETHERNET RMII (MN18) ERXDV VDDIOP0

PC26 LCDD22 ECOL LCD PANEL LCDD22 BLUE VDDIOP0

PC27 LCDD23 ERXCK LCD PANEL LCDD23 BLUE VDDIOP0

PC28 PWM0 TCLK1 VDDIOP0

PC29 PCK0 PWM2 USER'S LED2 CONTROL (DS2) PC29 or PWM2 VDDIOP0

PC30 DRXD SERIAL DEBUG PORT (J14) DRXD VDDIOP0

PC31 DTXD SERIAL DEBUG PORT (J14) DTXD VDDIOP0

AT91SAM9263-EK Evaluation Board Rev. B User Guide 3-9

6341D–ATARM–30-Sep-09
Board Description

Table 3-4. PIO Controller D

I/O Line Peripheral A Peripheral B Peripheral Usage Powered by

PD0 TXD1 SPI0_NPCS2 VDDIOP0

PD1 RXD1 SPI0_NPCS3 VDDIOP0

PD2 TXD2 SPI1_NPCS2 HDD CONNECTORS (J8) PD2 as IRQ VDDIOP0

PD3 RXD2 SPI1_NPCS3 HDD CONNECTORS (J8) PD3 as IOREADY VDDIOP0

PD4 FIQ DMARQ2 VDDIOP0

PD5 EBI0_NWAIT RTS2 VDDIOM0

PD6 EBI0_NCS4/CFCS0 CTS2 VDDIOM0

PD7 EBI0_NCS5/CFCS1 RTS1 VDDIOM0

PD8 EBI0_CFCE1 CTS1 HDD CONNECTORS (J8) EBI0_CFCE1 VDDIOM0

PD9 EBI0_CFCE2 SCK2 HDD CONNECTORS (J8) EBI0_CFCE2 VDDIOM0

PD10 SCK1 VDDIOM0

PD11 EBI0_NCS2 TSYNC VDDIOM0

PD12 EBI0_A23 TCLK VDDIOM0

PD13 EBI0_A24 TPS0 VDDIOM0

PD14 EBI0_A25_CFRNW TPS1 VDDIOM0

PD15 EBI0_NCS3/NANDCS TPS2 NAND FLASH (MN12B) EBI0_NCS3/NANDCS VDDIOM0

PD16 EBI0_D16 TPK0 EBI0 SDRAM DATA BUS D16 VDDIOM0

PD17 EBI0_D17 TPK1 EBI0 SDRAM DATA BUS D17 VDDIOM0

PD18 EBI0_D18 TPK2 EBI0 SDRAM DATA BUS D18 VDDIOM0

PD19 EBI0_D19 TPK3 EBI0 SDRAM DATA BUS D19 VDDIOM0

PD20 EBI0_D20 TPK4 EBI0 SDRAM DATA BUS D20 VDDIOM0

PD21 EBI0_D21 TPK5 EBI0 SDRAM DATA BUS D21 VDDIOM0

PD22 EBI0_D22 TPK6 EBI0 SDRAM DATA BUS D22 VDDIOM0

PD23 EBI0_D23 TPK7 EBI0 SDRAM DATA BUS D23 VDDIOM0

PD24 EBI0_D24 TPK8 EBI0 SDRAM DATA BUS D24 VDDIOM0

PD25 EBI0_D25 TPK9 EBI0 SDRAM DATA BUS D25 VDDIOM0

PD26 EBI0_D26 TPK10 EBI0 SDRAM DATA BUS D26 VDDIOM0

PD27 EBI0_D27 TPK11 EBI0 SDRAM DATA BUS D27 VDDIOM0

PD28 EBI0_D28 TPK12 EBI0 SDRAM DATA BUS D28 VDDIOM0

PD29 EBI0_D29 TPK13 EBI0 SDRAM DATA BUS D29 VDDIOM0

PD30 EBI0_D30 TPK14 EBI0 SDRAM DATA BUS D30 VDDIOM0

PD31 EBI0_D31 TPK15 EBI0 SDRAM DATA BUS D31 VDDIOM0

3-10 AT91SAM9263-EK Evaluation Board Rev. B User Guide

6341D–ATARM–30-Sep-09
 Board Description

Table 3-5. PIO Controller E

I/O Line Peripheral A Peripheral B Peripheral Usage Powered by

PE0 ISI_D0 IMAGE SENSORS CONNECTORS (J23) ISI_D0 VDDIOP1

PE1 ISI_D1 IMAGE SENSORS CONNECTORS (J23) ISI_D1 VDDIOP1

PE2 ISI_D2 IMAGE SENSORS CONNECTORS (J23) ISI_D2 VDDIOP1

PE3 ISI_D3 IMAGE SENSORS CONNECTORS (J23) ISI_D3 VDDIOP1

PE4 ISI_D4 IMAGE SENSORS CONNECTORS (J23) ISI_D4 VDDIOP1

PE5 ISI_D5 IMAGE SENSORS CONNECTORS (J23) ISI_D5 VDDIOP1

PE6 ISI_D6 IMAGE SENSORS CONNECTORS (J23) ISI_D6 VDDIOP1

PE7 ISI_D7 IMAGE SENSORS CONNECTORS (J23) ISI_D7 VDDIOP1

PE8 ISI_PCK TIOA1 IMAGE SENSORS CONNECTORS (J23) ISI_PCK VDDIOP1

PE9 ISI_HSYNC TIOB1 IMAGE SENSORS CONNECTORS (J23) ISI_HSYNC VDDIOP1

PE10 ISI_VSYNC PWM3 IMAGE SENSORS CONNECTORS (J23) ISI_VSYNC VDDIOP1

PE11 ISI_MCK PCK3 IMAGE SENSORS CONNECTORS (J23) ISI_MCK VDDIOP1

PE12 ISI_D8 IMAGE SENSORS CONNECTORS (J23) ISI_D8 VDDIOP1

PE13 ISI_D9 IMAGE SENSORS CONNECTORS (J23) ISI_D9 VDDIOP1

PE14 ISI_D10 IMAGE SENSORS CONNECTORS (J23) ISI_D10 VDDIOP1

PE15 ISI_D11 IMAGE SENSORS CONNECTORS (J23) ISI_D11 VDDIOP1

PE16 SD/MMC/DATAFLASH SOCKET (J9) PE16 as CD (Card Detect) VDDIOP1

PE17 VDDIOP1

PE18 TIOA0 SD/MMC SOCKET (J10) PE18 as CD (Card Detect) VDDIOP1

PE19 TIOB0 VDDIOP1

PE20 as CKSEL (Clock

PE20 EBI1_NWAIT SD/MMC/DATAFLASH SOCKET (J9) VDDIOM1
Select)

PE21 ETXCK EBI1_NANDWE ETHERNET RMII (MN18) ETXCK VDDIOM1

PE22 ECRS EBI1_NCS2/NANDCS VDDIOM1

PE23 ETX0 EB1_NANDOE ETHERNET RMII (MN18) ETX0 VDDIOM1

PE24 ETX1 EBI1_NWR3/NBS3 ETHERNET RMII (MN18) ETX1 VDDIOM1

PE25 ERX0 EBI1_NCS1/SDCS ETHERNET RMII (MN18) ERX0 VDDIOM1

PE26 ERX1 ERX1 VDDIOM1

PE27 ERXER EBI1_SDCKE ETHERNET RMII (MN18) ERXER VDDIOM1

PE28 ETXEN EBI1_RAS ETHERNET RMII (MN18) ETXEN VDDIOM1

PE29 EMDC EBI1_CAS ETHERNET RMII (MN18) EMDC VDDIOM1

PE30 EMDIO EBI1_SDWE ETHERNET RMII (MN18) EMDIO VDDIOM1

PE31 EF100 EBI1_SDA10 ETHERNET RMII (MN18) PE31 as IRQ VDDIOM1

AT91SAM9263-EK Evaluation Board Rev. B User Guide 3-11

6341D–ATARM–30-Sep-09
 Section 4
Configuration

4.1 Configuration Jumpers and Straps

Table 4-1. Configuration Jumpers and Straps

Designation Default Setting Feature
Forces power on. To use the software shutdown control, J2 must be opened
J2 Closed
and the battery backup inserted in its socket.
J4-1 Closed VDDBU jumper (1)
J4-2 Closed VDDCORE jumper (1)
J5-1 Closed VDDOSC jumper (1)
J5-2 Closed VDDIOP0 jumper(1)
J5-3 Closed VDDIOP1 jumper(1)
J5-4 Closed VDDIOM0 jumper (1)
J5.5 Closed VDDIOM1 jumper (1)
Opened Enables Boot on the internal ROM. Close to boot from NCS0.
J5-6
Closed Enables Boot on the NCS0
J5-7 Opened NTRST Ground
J16 Closed Enables 120 ohms CAN bus resistance termination
J21 Closed Enables Ethernet Auto MDIX control
J29 Closed NAND FLash chip select
S1 Opened Selects ICE or JTAG mode. (closed)
S2 Opened Disables NAND FLASH write protect
S3 Opened Disables 5V power supply on J24, J25 expansion connectors
R17 IN Enables the ICE NTRST input
R18 IN Enables the ICE NRST input
R13 IN Enables the use of the Y1 crystal. If an external clock has to be used, R13
R15 IN and R15 must be unsoldered and R16/J16 fitted.

Enables the use of the MN7 SDRAM device. Needs to be removed when
R30 IN
ETM is used.(2)
R45 IN Enables the use of the SERIAL EEPROM SCL (PB5)
R46 IN Enables the use of the SERIAL EEPROM SDA (PB4)
R75 IN Enables the use of the DBGU TXD signal (PC31)

AT91SAM9263-EK Evaluation Board Rev. B User Guide 4-1

6341D–ATARM–30-Sep-09
Configuration

Table 4-1. Configuration Jumpers and Straps (Continued)

Designation Default Setting Feature
R79 IN Enables the use of the DBGU RXD signal (PC30)
R84 IN Enables the use of the USB CNX detection (PA25)
R76 IN Enables the use of the RS232 COM PORT TXD signal (PA26)
R78 IN Enables the use of the RS232 COM PORT RTS signal (PA28)
R80 IN Enables the use of the RS232 COM PORT RXD signal (PA27)
R82 IN Enables the use of the RS232 COM PORT CTS signal (PA29)
R87 IN Enables the use of the CAN BUS driver RS control signal (PA26)
R89 IN Enables the use of the CAN BUS driver CANTXRT RTS signal (PA28)
R91 IN Enables the use of the RS232 COM PORT RXD signal (PA27)
R93 IN Enables the use of the RS232 COM PORT CTS signal (PA29)
R112 IN Enables the use of interrupt ETHERNET PHY (PE31)
R126 IN Enables the use of TOUCH SCEEN CONTROLLER (PB11_SPI0_NPCS3)
R127 IN Enables the use of TOUCH SCEEN CONTROLLER BUSY signal (PA31)
R128 IN Enables the use of TOUCH SCEEN CONTROLLER PENIRQ (PA15_IRQ1)
TP67 N.A GND Test point
TP68 N.A GND Test point
TP69 N.A GND Test point
TP70 N.A GND Test point
TP71 N.A 0 to 3.3V analog user's input
TP72 N.A 0 to 3.3V analog user's input
TP73 N.A AGND of TP71
TP74 N.A AGND of TP72

Note: 1. These jumpers are provided for power consumption measurement use. By default, they are closed. To
use this feature, the user has to open the strap and insert an ammeter.
2. AT91SAM9263 ETM signals [TPK0 - TPK15] are multiplexed with EBI0 signals [EBI0_D16 - EBI0_D31].
AT91SAM9263-EK EBI0 signals [EBI0_D16 - EBI0_D31] are connected to an SDRAM device
(part MN7).
Having this SDRAM device enabled adds capacitance to the data line [EBI0_D16 - EBI0_D31], which
leads to ETM data corruption.
You need to remove the resistor R30 to release the EBI0_NCS1_SDCS signal and put the
SDRAM IOs [EBI0_D16 - EBI0_D31] in High-Z. Having these signals in High-Z removes the
added capacitance; the ETM signals are no longer corrupted.

4-2 AT91SAM9263-EK Evaluation Board Rev. B User Guide

6341D–ATARM–30-Sep-09
 Section 5
Schematics

5.1 Schematics
This section contains the following schematics:
„ AT91SAM9263-EK Diagram
„ Power Supply
„ AT91SAM9263
„ EBI0 Memory
„ EBI1 Memory
„ Serial Memory
„ Audio AC97
„ Serial Interfaces
„ Ethernet
„ LCD and ISI
„ Expansion

AT91SAM9263-EK Evaluation Board Rev. B User Guide 5-1

6341D–ATARM–30-Sep-09
 8 7 6 5 4 3 2 1

POWER SUPPLY - PAGE 2 AT91SAM9263 - SHEET 3 EBI0 MEMORY - SHEET 4

EBI0_D[0..31]

12VDC
SHDN SHDN EBI0_D[0..31] D[0..31]

EBI0
PWM0
POWERLED NRSTFLASH EBI0_A[0..22]
NRSTFLASH EBI0_A[0..22] A[0..22]

EBI0_RAS RAS

INTERFACE
PWM1
USERLED1 EBI0_CAS CAS

USER'S
PWM2 EBI0_SDA10 SDA10
USERLED2 EBI0_SDWE SDWE
PC4 EBI0_NCS1/SDCS SDCS
RIGHTCLIC PC5 VDDISI

SDRAM
LEFTCLIC VDDISI EBI0_SDCK SDCK
EBI0_SDCKE SDCKE
D D
EBI0_A0
SERIAL INTERFACES - SHEET 8 EBI0_NBS1 NBS0
DTXD EBI0_A1 NBS1
DTXD DRXD EBI0_NBS3 NBS2
DBGU DRXD NBS3
RS232

TXD0 EBI0_A16
TXD RXD0 EBI0_A17 BA0
RXD RTS0 BA1
COM0 RTS CTS0 EBI0_A22

NORFLASH NANFLASH
CTS EBI0_A21 CLE
PA25 ALE
USBCNX EBI0_NANDOE NANDOE
DEVICE DDM DDM EBI0_NANDWE PD15 NANDWE
DDP DDP PA22 NANDCS
RDYBSY
HDMA HDMA
USB

HDPA HDPA
HOST A ENA
PA24
PA23
FLGA EBI0_NCS0 NCS
EBI0_NWE/NWR0/CFWE NWE
HDMB HDMB EBI0_NRD/CFOE NRD
HDPB HDPB
HOST B ENB
PA21 NRSTFLASH
NRSTFLASH
PA20
FLGB
PA19 NRST
CANRS PA18 NRST RESET-
CANRXEN
CAN

EBI0_CFCE1

1.8" HDD
CANRX EBI0_CFCE2 CS0-
CANRX CANTX EBI0_NBS1 CS1-
C CANTX EBI0_NBS1/NW1/CFIOR EBI0_NBS3 DIOR- C
EBI0_NBS3/NW3/CFIOW DIOW-
RMII ETHERNET - SHEET 9 PD2
ETXCK PD3 INTRQ
TX_CLK IORDY
10/100 FAST ETHERNET

ETX1
TXD1 ETX0 EBI1 MEMORY - SHEET 5
TXD0 ETXEN EBI1_D[0..15]
TX_EN EBI1_D[0..15] D[0..15]

EBI1
EBI1_A[0..21]
ERX1 EXPANSION CONNECTORS - SHEET 10 EBI1_A[0..21] EBI1_A[1..21]
RXD1 ERX0 PA[0..31] A[1..21]
RXD0 ERXDV PA[0..31] PA[0..31]
RX_DV ERXER PB[0..31] EBI1_NCS0 NCS

PSRAM
RX_ER PB[0..31] PB[0..31] EBI1_NWE/NWR0/CFWE NWR
EMDC PC[0..31] EBI1_NRD/CFOE NOE
MDC EMDIO PC[0..31] PC[0..31] EBI1_A0
MDIO PE31 PD[0..31] LB
MDINTR PD[0..31] PD[0..31] EBI1_NBS1/NW1/CFIOR UB
NRST PE[0..31]
NRST PE[0..31] PE[0..31] EBI1_SDCK MCI & TWI - SHEET 6
PE16
LCD & ISI - SHEET 10 MCI0_CD
LCDD[2..7] MCI0_DA0

MMC SD/SDIO
DATAFLASH
R[0..5] LCDD[10..15] MCI0_DA1 MCI0_DA0
G[0..5] LCDD[18..23] MCI0_DA2 MCI0_DA1 CARD
B[0..5] MCI0_DA3 MCI0_DA2 READER
LCDHSYNC MCI0_CDA MCI0_DA3
LCD INTERFACE

3.5" QVGA HSYNC LCDDOTCK MCI0_CDA

DCLK LCDDEN MCI0_CK
DTMG SPI0_SPCK MCI0_CK
B B
LCDCC PE20 SPI0_SPCK
VCTRL PA30 CKSEL
PCI
SPI0_MOSI PIO USAGE PE18
MCI1_CD

MMC SD/SDIO
MOSI SPI0_MISO MCI1_DA0
MISO SPI0_SPCK PA[0..31] PB[0..31] PC[0..31] PD[0..31] PE[0..31] MCI1_DA1 MCI1_DA0
TOUCH SCREEN
SPCK SPI0_NPCS3 MCI1_DA2 MCI1_DA1 CARD
CONTROLLER NPCS MCI1_DA3 MCI1_DA2 READER
IRQ1 SPI0_MISO PA0 PA0 MCI0_DA0 PB0 AC97FS PC0 PD0 PE0 ISI_D0 MCI1_CDA MCI1_DA3
IRQ PA31 SPI0_MOSI PA1 PA1 MCI0_CDA PB1 AC97CK PC1 LCDHSYNC PD1 PE1 ISI_D1 MCI1_CDA
BUSY PA2 SPI0_SPCK PB2 AC97TX PC2 LCDDOTCK PD2 (INTRQ) PE2 ISI_D2 MCI1_CK
ISI_D[0..11] PA3 MCI0_DA1 PB3 AC97RX PC3 LCDDEN PD3 (IORDY) PE3 ISI_D3 MCI1_CK
ISI_D[0..11] PA4 MCI0_DA2 PB4 TWD PC4 (RIGHTCLIC) PD4 PE4 ISI_D4

EEPROM
CAMERA INTERFACE

SERIAL
ISI_MCK PA5 MCI0_DA3 PB5 TWCK PC5 (LEFTCLIC) PD5 PE5 ISI_D5 TWCK
ISI_MCK ISI_VSYNC PA6 MCI1_CK PB6 PC6 LCDD2 PD6 PE6 ISI_D6 TWD SCL
ISI_VSYNC ISI_HSYNC PA7 MCI1_CDA PB7 PWM0 PC7 LCDD3 PD7 PE7 ISI_D7 SDA
ISI_HSYNC ISI_PCK PA8 MCI1_DA0 PB8 PWM1 PC8 LCDD4 PD8 EBI0_CFCE1 PE8 ISI_PCK
ISI_PCK PA9 MCI1_DA1 PB9 LCDCC PC9 LCDD5 PD9 EBI0_CFCE2 PE9 ISI_HSYNC
ISI VDDISI PA10 MCI1_DA2 PB10 PCK1 PC10 LCDD6 PD10 PE10 ISI_VSYNC AUDIO AC97 - SHEET 7
VDDISI PA11 MCI1_DA3 PB11 SPI0_NPCS3 PC11 LCDD7 PD11 PE11 ISI_MCK AC97FS

OUT
TWD PA12 MCI0_CK PB12 PC12 LCDD13 PD12 PE12 ISI_D8 AC97CK SYNC
SDA TWCK PA13 CANTX PB13 PC13 PD13 PE13 ISI_D9 AC97TX BITCLK
SCL PA14 CANRX PB14 PC14 LCDD10 PD14 PE14 ISI_D10 AC97RX SDATA_OUT
SDATA_IN
PA17 PA15 IRQ1 PB15 PC15 LCDD11 PD15 (NANDCS) PE15 ISI_D11 AUDIO

MIC IN
CTRL2 PA16 PA16 (CTRL1) PB16 PC16 LCDD12 PD16 PE16 (MCI0_CD) PCK1
CTRL1 PA17 (CTRL2) PB17 PC17 LCDD21 PD17 PE17 EXT_CLK
PA18 (CANRXEN) PB18 PC18 LCDD14 PD18 PE18 (MCI1_CD) NRST
PA19 (CANRS) PB19 PC19 LCDD15 PD19 PE19 RST#
PA20 (FLGB) PB20 PC20 PD20 PE20 (CKSEL)
A A
PA21 (ENB) PB21 PC21 PD21 PE21 ETXCK
PA22 (RDYBSY) PB22 PC22 LCDD18 PD22 PE22
PA23 (FLGA) PB23 PC23 LCDD19 PD23 PE23 ETX0
PA24 (ENA) PB24 PC24 LCDD20 PD24 PE24 ETX1
PA25 (USBCNX) PB25 PC25 ERXDV PD25 PE25 ERX0
PA26 TXD0 PB26 PC26 LCDD22 PD26 PE26 ERX1 C PP 10-JUI-08
PA27 RXD0 PB27 PC27 LCDD23 PD27 PE27 ERXER B JPG 15-MAR-07
PA28 RTS0 PB28 PC28 PD28 PE28 ETXEN AINIT EDIT JPG 10-OCT-06
PA29 CTS0 PB29 PC29 PWM2 PD29 PE29 EMDC REV MODIF. DES. DATE VER. DATE
PA30 (PCI) PB30 PC30 DRXD PD30 PE30 EMDIO
PA31 (BUSY) PB31 PC31 DTXD PD31 PE31 (MDINTR) AT91SAM9263-EK SCALE
1/1 REV. SHEET
1
C
DIAGRAM
11
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

C1 CR1
180NF BAT20J

CR2
J1 STPS2L30A 5V

2
MN1
1 3 6

BOOST
VIN SW L1
2 4 VIN SW 5
C2 2.2µH
2.2µF 11 12 C3
SHDN FB
3

LT1765-5 10µF
R141 7
200K NC CR3

SYNC
3 10

GND
GND
GND
GND
GND
2.1 MM SOCKET NC STPS2L30A
15

VC
NC

14

1
8
17
9
16

13
1 C4
Q1 2.2NF
BSH103
2
R3
100K C5 C6
1µF 1µF
C7 CR4
180NF BAT20J
8 6 3 4
C C
3V3 C10 R1 1V2
C1M C1P C2M C2P
2

MN3 22µF 100K

3 6 5 7
BOOST

VIN SW L2 VIN VOUT

4 VIN SW 5
C8 2.2µH C11
2.2µF 11 12 C9 10PF
SHDN LT1765-3.3 FB 10µF TPS60500
7 C12 10
NC CR5 2.2µF FB
SYNC

3 10
GND
GND
GND
GND
GND

NC STPS2L30A R2
15
VC

NC 200K
1 EN PG 2
GND
14

1
8
17
9
16

13

1 C13 MN2
Q2 2.2NF 9
BSH103
Q3 2
3
BSH103

R4 10K J2
SHDN 1
FORCE
POWER R140 0R
NRSTFLASH
2
ON
C14
15PF

B B

USER INTERFACE
3V3

3V3
R5 R6 220R
120R DS2 GREEN USERLED2 ADHESIVE FEET GND TEST POINT
R7 220R
DS1 GREEN Z1 Z2 TP67 TP68 TP69 TP70
POWER LED USERLED1
11.1 11.1

R8
DS3 Z3 Z4 Z5
470K
YELLOW
11.1 11.1 11.1
RIGHT CLICK
3 RIGHTCLIC
BP2

R9 0R
1 POWERLED LEFT CLICK
A A
Q4 BP1 LEFTCLIC
IRLML2402
2

C PP 10-JUI-08
B JPG 15-MAR-07
AINIT EDIT JPG 10-OCT-06
REV MODIF. DES. DATE VER. DATE
AT91SAM9263-EK SCALE
1/1 REV. SHEET
2
POWER SUPPLY C 11
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

PA[0..31] PB[0..31] EBI0_D[0..31] EBI1_D[0..15]

MN4A MN4B MN4F MN4G
PA0 N16 K17 PB0 PD16 EBI0_D16 EBI0_D0 C2 T10 EBI1_D0
PA0/MCI0_DA0/SPI0_MISO PB0/AC97FS/TF0 EBI0_D0 EBI1_D0 EBI1_A[0..21]
PA1 N15 K16 PB1 PD17 EBI0_D17 EBI0_D1 D4 R10 EBI1_D1
PA2 PA1/MCI0_CDA/SPI0_MOSI PB1/AC97CK/TK0 PB2 PD18 EBI0_D18 EBI0_D2 EBI0_D1 EBI1_D1 EBI1_D2
P15 PA2/SPI0_SPCK PB2/AC97TX/TD0 K18 A1 EBI0_D2 EBI1_D2 N10
PA3 P14 K13 PB3 PB3 PD19 EBI0_D19 EBI0_D3 D2 U11 EBI1_D3
PA4 PA3/MCI0_DA1/SPI0_NPCS1 BMS_PB3/AC97RX/RD0 PB4 PD20 EBI0_D20 EBI0_D4 EBI0_D3 EBI1_D3 EBI1_D4
M15 PA4/MCI0_DA2/SPI0_NPCS2 PB4/TWD/RK0 L14 B1 EBI0_D4 EBI1_D4 P12
PA5 PB5 PD21 EBI0_D21 EBI0_D5 EBI1_D5
PA6
M17
M14
PA5/MCI0_DA3/SPI0_NPCS0 PB5/TWCK/RF0 J15
J16 PB6 PD22 EBI0_D22 EBI0_D6
E3
C1
EBI0_D5 EBI1_D5 V11
N11 EBI1_D6 ETM
PA7 PA6/MCI1_CK/PCK2 PB6/TF1/DMARQ1 PB7 PD23 EBI0_D23 EBI0_D7 EBI0_D6 EBI1_D6 EBI1_D7
PA8
M16
M18
PA7/MCI1_CDA PB7/TK1/PWM0 J17
J18 PB8 PD24 EBI0_D24 EBI0_D8
E2
E4
EBI0_D7 EBI1_D7 T11
R11 EBI1_D8 TRACE PORT
PA9 PA8/MCI1_DA0 PB8/TD1/PWM1 PB9 PD25 EBI0_D25 EBI0_D9 EBI0_D8 EBI1_D8 EBI1_D9
L15 PA9/MCI1_DA1 PB9/RD1/LCDCC J13 F3 EBI0_D9 EBI1_D9 N12
PA10 L17 J14 PB10 PD26 EBI0_D26 EBI0_D10 D1 P13 EBI1_D10
PA11 PA10/MCI1_DA2 PB10/RK1/PCK1 PB11 PD27 EBI0_D27 EBI0_D11 EBI0_D10 EBI1_D10 EBI1_D11 TPS0 TPK8
L18 PA11/MCI1_DA3 PB11/RF1/SPI0_NPCS3 J12 F4 EBI0_D11 EBI1_D11 V12 38 37
PA12 L16 H18 PB12 PD28 EBI0_D28 EBI0_D12 F5 R12 EBI1_D12 TPS1 36 35 TPK9
D
PA13 PA12/MCI0_CK PB12/SPI1_MISO PB13 PD29 EBI0_D29 EBI0_D13 EBI0_D12 EBI1_D12 EBI1_D13 TPS2 TPK10
D
L13 PA13/CANTX/PCK0 PB13/SPI1_MOSI H15 F2 EBI0_D13 EBI1_D13 U12 34 33
PA14 K14 H17 PB14 PD30 EBI0_D30 EBI0_D14 G4 T12 EBI1_D14 TSYNC 32 31 TPK11
PA15 PA14/CANRX/IRQ0 PB14/SPI1_SPCK PB15 PD31 EBI0_D31 EBI0_D15 EBI0_D14 EBI1_D14 EBI1_D15 TPK0 TPK12
K15 PA15/TCLK2/IRQ1 PB15/SPI1_NPCS0 H14 E1 EBI0_D15 EBI1_D15 R13 30 29
PA16 P3 B17 PB16 TPK1 28 27 TPK13
PA16/MCI0_CDB/EBI1_D16 PB16/SPI1_NPCS1/PCK1 EBI0_A[0..22]
PA17 U1 H13 PB17 R134 EBI0_A0 E9 U6 EBI1_A0 TPK2 26 25 TPK14
PA18 PA17/MCI0_DB0/EBI1_D17 PB17/SPI1_NPCS2/TIOA2 PB18 4.7K EBI0_A1 EBI0_NBS0/A0 EBI1_NBS0/A0 EBI1_A1 TPK3 TPK15
R3 PA18/MCI0_DB1/EBI1_D18 PB18/SPI1_NPCS3/TIOB2 G18 A9 EBI0_NBS2/NWR2/A1 EBI1_NWR2/A1 V5 24 23
PA19 T3 H12 PB19 EBI0_A2 D9 R6 EBI1_A2 TPK4 22 21 NTRST
PA20 PA19/MCI0_DB2/EBI1_D19 PB19 PB20 EBI0_A3 EBI0_A2 EBI1_A2 EBI1_A3 TPK5 TDI
U2 PA20/MCI0_DB3/EBI1_D20 PB20 G14 C9 EBI0_A3 EBI1_A3 V6 20 19
PA21 T4 G13 PB21 EBI0_A4 B9 P8 EBI1_A4 TPK6 18 17 TMS
PA22 PA21/MCI1_CDB/EBI1_D21 PB21 PB22 J5-6 R135 4.7K EBI0_A5 EBI0_A4 EBI1_A4 EBI1_A5 TPK7 TCK
V2 PA22/MCI1_DB0/EBI1_D22 PB22 G17 A8 EBI0_A5 EBI1_A5 U7 16 15
PA23 U3 G15 PB23 11 12 EBI0_A6 F9 N7 EBI1_A6 3V3 14 13 RTCK
PA24 PA23/MCI1_DB1/EBI1_D23 PB23 PB24 EBI0_A7 EBI0_A6 EBI1_A6 EBI1_A7 TDO
U4 PA24/MCI1_DB2/EBI1_D24 PB24/DMARQ3 H16 B8 EBI0_A7 EBI1_A7 T7 R136 12 11
PA25 R4 F15 PB25 EBI0_A8 C8 P7 EBI1_A8 10K 10 9 NRST
PA26 PA25/MCI1_DB3/EBI1_D25 PB25 PB26 BOOT MODE SELECT EBI0_A9 EBI0_A8 EBI1_A8 EBI1_A9
T5 PA26/TXD0/EBI1_D26 PB26 F14 D8 EBI0_A9 EBI1_A9 V7 8 7
PA27 V3 F17 PB27 Opened = Internal ROM BOOT EBI0_A10 A7 U8 EBI1_A10 TCLK 6 5
PA28 PA27/RXD0/EBI1_D27 PB27/PWM2 PB28 Closed = NCS0 EBI0_A11 EBI0_A10 EBI1_A10 EBI1_A11
U5 PA28/RTS0/EBI1_D28 PB28/TCLK0 G16 A6 EBI0_A11 EBI1_A11 N8 R137 4 3
PA29 V4 F16 PB29 EBI0_A12 F8 T8 EBI1_A12 0R 2 1
PA30 PA29/CTS0/EBI1_D29 PB29/PWM3 PB30 EBI0_A13 EBI0_A12 EBI1_A12 EBI1_A13 R138
R5 PA30/SCK0/EBI1_D30 PB30 E15 C7 EBI0_A13 EBI1_A13 R8
PA31 T6 E17 PB31 EBI0_A14 E7 R7 EBI1_A14 10K
PA31/DMARQ0/EBI1_D31 PB31 EBI0_A15 EBI0_A14 EBI1_A14 EBI1_A15 C160
B7 EBI0_A15 EBI1_A15 V8
EBI0_A16 F7 U9 EBI1_A16 100NF
EBI0_BA0/A16 EBI1_BA0/A16

G1
G2
G3
G4
G5
EBI0_A17 D6 R9 EBI1_A17 J28
PC[0..31] EBI0_BA1/A17 EBI1_BA1/A17
MN4C MN4D EBI0_A18 D7 T9 EBI1_A18
PD[0..31] EBI0_A18 EBI1_A18
PC0 E16 B10 PD0 EBI0_A19 A5 P9 EBI1_A19
PC1 PC0/LCDVSYNC PD0/TXD1/SPI0_NPCS2 PD1 EBI0_A20 EBI0_A19 EBI1_A19 EBI1_A20
D17 PC1/LCDHSYNC PD1/RXD1/SPI0_NPCS3 D10 D5 EBI0_A20 EBI1_A20 V9
PC2 D16 C10 PD2 EBI0_A21 C6 M9 EBI1_A21
PC3 PC2/LCDDOTCK PD2/TXD2/SPI1_NPCS2 PD3 EBI0_A22 EBI0_A21 EBI1_A21
C15 PC3/LCDDEN/PWM1 PD3/RXD2/SPI1_NPCS3 F10 B6 EBI0_A22 EBI1_A22 N9 NOT USED
PC4
PC5
E14 PC4/LCDD0/LCDD3 PD4/FIQ/DMARQ2 A10 PD4
PD5
This Inductor
B16 G5 B4
C PC6 D13
PC5/LCDD1/LCDD4 PD5/EBI0_NWAIT/RTS2
G3 PD6 is intentionally mounted EBI0_RAS
EBI0_CAS B3
EBI0_RAS C
PC6/LCDD2/LCDD5 PD6/EBI0_NCS4/CFCS0/CTS2 EBI0_CAS
PC7 B15 PC7/LCDD3/LCDD6 PD7/EBI0_NCS5/CFCS1/RTS1 F1 PD7 in place of R139 EBI0_SDWE C4 EBI0_SDWE
PC8 C14 G6 PD8 E8
PC8/LCDD4/LCDD7 PD8/EBI0_CFCE1/CTS1 EBI0_SDA10 EBI0_SDA10
PC9 B14 H4 PD9 A2
PC9/LCDD5/LCDD10 PD9/EBI0_CFCE2/SCK2 EBI0_SDCKE EBI0_SDCKE
PC10 D15 G7 PD10 C5 R15
PC10/LCDD6/LCDD11 PD10/SCK1 EBI0_SDCK EBI0_SDCK EBI1_SDCK EBI1_SDCK
PC11 E13 H5 TSYNC 1 8 PD11
PC12 PC11/LCDD7/LCDD12 PD11/EBI0_NCS2/TSYNC TCLK PD12 RR3
A15 PC12/LCDD8/LCDD13 PD12/EBI0_A23/TCLK G2 2 7 EBI0_NCS0 F6 EBI0_NCS0 EBI1_NCS0 P10 EBI1_NCS0
PC13 F13 H2 TPS0 3 6 PD13 0R A4
PC13/LCDD9/LCDD14 PD13/EBI0_A24/TPS0 EBI0_NCS1/SDCS EBI0_NCS1/SDCS 3V3
PC14 C13 H6 TPS1 4 5 PD14
PC15 PC14/LCDD10/LCDD15 PD14/EBI0_A25_CFRNW/TPS1 TPS2 PD15 R139 CR6
E12 PC15/LCDD11/LCDD19 PD15/EBI0_NCS3/NANDCS/TPS2 H3 EBI0_NRD/CFOE E6 EBI0_NRD/CFOE EBI1_NRD/CFOE U10 EBI1_NRD/CFOE
PC16 D14 PC16/LCDD12/LCDD20 PD16/EBI0_D16/TPK0 H7 TPK0 1 2.2µH 8 PD16
EBI0_NWE/NWR0/CFWE A3 EBI0_NWE/NWR0/CFWE EBI1_NWE/NWR0/CFWE P11 EBI1_NWE/NWR0/CFWE
MMBD1704A J3

2
PC17 B13 G1 TPK1 2 7 PD17 RR4 E5 V10
PC17/LCDD13/LCDD21 PD17/EBI0_D17/TPK1 EBI0_NBS1/NW1/CFIOR EBI0_NBS1/NWR1/CFIOR EBI1_NBS1/NWR1/CFIOR EBI1_NBS1/NW1/CFIOR
PC18 F12 J5 TPK2 3 6 PD18 0R B5 VDDBU C16
PC18/LCDD14/LCDD22 PD18/EBI0_D18/TPK2 EBI0_NBS3/NW3/CFIOW EBI0_NBS3/NWR3/CFIOW
PC19 A14 J4 TPK3 4 5 PD19 J4-1 100NF Z7
PC20 PC19/LCDD15/LCDD23 PD19/EBI0_D19/TPK3 TPK4 PD20 CR1225
D12 PC20/LCDD16/E_TX2 PD20/EBI0_D20/TPK4 J8 1 8 EBI0_NANDOE B2 EBI0_NANDOE 1 2 3

2
PC21 B12 J7 TPK5 2 7 PD21 RR5 C3
PC22 E11
PC21/LCDD17/E_TX3 PD21/EBI0_D21/TPK5
J3 TPK6 3 6 PD22 0R
EBI0_NANDWE EBI0_NANDWE MN5 +

VDD
OUT
PC23 PC22/LCDD18/E_RX2 PD22/EBI0_D22/TPK6 TPK7 PD23 R1100D121C 3V
C12 J6 4 5

GND
PC24 PC23/LCDD19/E_RX3 PD23/EBI0_D23/TPK7 TPK8 PD24 R21 10K MN4H
A13 PC24/LCDD20/E_TXER PD24/EBI0_D24/TPK8 H1 1 8

1
PC25 D11 K8 TPK9 2 7 PD25 RR6 R2 M8 C15 100NF 1K R10
PC26 PC25/LCDD21/E_RXDV PD25/EBI0_D25/TPK9 TPK10 PD26 0R TST VDDBU
A12 PC26/LCDD22/E_COL PD26/EBI0_D26/TPK10 J2 3 6 GNDBU L12

3
PC27 F11 K5 TPK11 4 5 PD27 J4-2
PC28 PC27/LCDD23/E_RXCK PD27/EBI0_D27/TPK11 TPK12 PD28
B11 PC28/PWM0/TCLK1 PD28/EBI0_D28/TPK12 K2 1 8 3 4 1V2
PC29 C11 K7 TPK13 2 7 PD29 RR7 C18
PC29/PCK0/PWM2 PD29/EBI0_D29/TPK13 HDPB HDPB
PC30 A11 J1 TPK14 3 6 PD30 0R D18 V1 C17 100NF
PC30/DRXD PD30/EBI0_D30/TPK14 HDMB HDMB VDDCORE
PC31 E10 K6 TPK15 4 5 PD31 H10 C18 100NF
PC31/DTXD PD31/EBI0_D31/TPK15 VDDCORE
HDPA E18 HDPA VDDCORE A16 C19 100NF
F18 J5-1
HDMA HDMA
PE[0..31] 1 2 3V3
B MN4E A18 B
DDP DDP
PE0 K3 B18 V18 C20 100NF
PE0/ISI_D0 DDM DDM VDDPLLB
PE1 K4 U17 C21 100NF
PE2 PE1/ISI_D1 VDDPLLA
L6 PE2/ISI_D2 C22 4.7NF VDDOSC T1 C23 100NF
PE3 L7 R11 1,96K 1% P18 T17
PE4 PE3/ISI_D3 PLLRCB GNDPLLB
L2 PE4/ISI_D4 C24 470 pF GNDPLLA N14
PE5 L5 J5-2
PE5/ISI_D5 C25 10NF
PE6 K1 R12 1.5K U18 3 4 3V3
PE7 PE6/ISI_D6 PLLRCA
L4 PE7/ISI_D7 C26 1NF
PE8 M7 L11 C27 100NF
PE9 PE8/ISI_PCK/TIOA1 C28 R13 0R VDDIOP0
L3 PE9/ISI_HSYNC/TIOB1 R18 XOUT VDDIOP0 C17 C29 100NF
PE10 L1 22PF A17 C30 100NF
PE11 PE10/ISI_VSYNC/PWM3 Y1 VDDIOP0 J5-3
M4 PE11/ISI_MCK/PCK3 16.36766MHz
PE12 M6 J6 5 6 3V3
PE13 PE12/ISI_D8 NOT POPULATED C31 R15 0R
M5 PE13/ISI_D9 T18 XIN VDDISI
PE14 M2 1 22PF L8 C32 100NF
PE15 PE14/ISI_D10 RR1 VDDIOP1 J5-4
M3 PE15/ISI_D11 2 3
PE16 N6 100K 4 5 C33 R1 7 8 3V3
PE16 XOUT32
4

PE17 R16 15PF

PE18
N5
M1
PE17 ICE INTERFACE 3V3
NOT POPULATED Y2 L10 C34 100NF
PE18/TIOA0 VDDIOM0
5
6
7
8

PE19 N3 32.768 kHz K12 C35 100NF

PE20 PE19/TIOB0 SMB MALE C36 VDDIOM0
P6 PE20/EBI1_NWAIT P1 XIN32 VDDIOM0 K10 C37 100NF
1

PE21 V13 3V3 J7 3V3 15PF H8

PE21/E_TXCK/EBI1_NANDWE VDDIOM0 C38 100NF
PE22 U13 J5-5
PE23 PE22/E_CRS/EBI1_NCS2/NANDCS VDDBU S1
T13 PE23/E_TX0/EBI1_NANDOE 2 1 P5 JTAGSEL 9 10 3V3
4
3
2
1

PE24 V14 4 3 R17 0R NTRST U16

PE25 PE24/E_TX1/EBI1_NWR3/NBS3/CFIOW TDI NTRST
T14 PE25/E_RX0/EBI1_NCS1/SDCS 6 5 P17 TDI VDDIOM1 T2 C39 100NF
PE26 R14 8 7 TMS N17 M13 C40 100NF
PE27 PE26/E_RX1 TCK TMS VDDIOM1
U14 PE27/E_RXER/EBI1_SDCKE 10 9 R17 TCK VDDIOM1 M10 C41 100NF
PE28 P16 12 11 RTCK U15 L9 C42 100NF
A
PE29 PE28/E_TXEN/EBI1_RAS TDO RTCK VDDIOM1 A
T15 PE29/E_MDC/EBI1_CAS 14 13 N18 TDO
WKUP

0R
SHDN

PE30 R16 16 15 R18 NRST V15

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PE31 PE30/E_MDIO/EBI1_SDWE NRST
T16 18 17
NC
NC
NC
NC
NC

PE31/EF100/EBI1_SDA10 VDDBU
20 19
3V3 J5-7
P2
P4

D3
G9
N1
N2
N4

V16
V17
C16
G8
G10
G11
G12
H9
H11
J9
J10
J11
K9
K11
M11
M12
N13
14 13 C PP 10-JUI-08
R20 B JPG 15-MAR-07
R19 100K AINIT EDIT JPG 10-OCT-06
SHDN
1K BP3 BP4 REV MODIF. DES. DATE VER. DATE

NRST
AT91SAM9263-EK SCALE
1/1 REV. SHEET
3
C
NRST WAKE UP
AT91SAM9263
11
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

SDRAM
A[0..22]
NORFLASH
D[0..31]

MN6 MN7 MN8

A2 23 2 D0 A2 23 2 D16 A1 25 29 D0
A3 A0 MT48LC16M16A2 DQ0 D1 A3 A0 MT48LC16M16A2 DQ0 D17 A2 A0 I/00 D1
24 A1 DQ1 4 24 A1 DQ1 4 24 A1 I/O1 31
A4 25 5 D2 A4 25 5 D18 A3 23 33 D2
A5 A2 DQ2 D3 A5 A2 DQ2 D19 A4 A2 I/O2 D3
26 A3 DQ3 7 26 A3 DQ3 7 22 A3 I/O3 35
A6 29 8 D4 A6 29 8 D20 A5 21 38 D4
A7 A4 DQ4 D5 A7 A4 DQ4 D21 A6 A4 I/O4 D5
D 30 A5 DQ5 10 30 A5 DQ5 10 20 A5 I/O5 40 D
A8 31 11 D6 A8 31 11 D22 A7 19 42 D6
A9 A6 DQ6 D7 A9 A6 DQ6 D23 A8 A6 I/O6 D7
32 A7 DQ7 13 32 A7 DQ7 13 18 A7 I/O7 44
A10 33 42 D8 A10 33 42 D24 A9 8 30 D8
A11 A8 DQ8 D9 A11 A8 DQ8 D25 A10 A8 I/O8 D9
34 A9 DQ9 44 34 A9 DQ9 44 7 A9 I/O9 32
SDA10 22 45 D10 SDA10 22 45 D26 A11 6 34 D10
SDA10 A10 DQ10 A10 DQ10 A10 I/O10
A13 35 47 D11 A13 35 47 D27 A12 5 36 D11
A11 DQ11 D12 A11 DQ11 D28 P15 R22 0R A20 A13 A11 I/O11 D12
DQ12 48 DQ12 48 4 A12 I/O12 39
BA0 20 50 D13 BA0 20 50 D29 A14 3 41 D13
BA0 BA0 DQ13 BA0 DQ13 R23 A13 I/O13
BA1 21 51 D14 BA1 21 51 D30 A15 2 43 D14
BA1 BA1 DQ14 BA1 DQ14 NOT POPULATED A14 I/O14
53 D15 53 D31 A16 1 45 D15
A14 DQ15 A14 DQ15 A17 A15 I/O15
36 A12 3V3 36 A12 3V3 48 A16
40 1 40 1 P9 R24 0R A22 A18 17
N.C VDD C43 100NF N.C VDD C44 100NF A17
14 14 A19 16
VDD C45 100NF VDD C46 100NF A18 AT49BV642D
SDCKE 37 27 SDCKE 37 27 P15 15
SDCKE CKE VDD C47 100NF CKE VDD C48 100NF A19
3 3 A21 10
VDDQ C49 100NF VDDQ C50 100NF A20
SDCK 38 9 SDCK 38 9 P9 9
SDCK CLK VDDQ C51 100NF CLK VDDQ C52 100NF A21 3V3
43 43 3V3 R144 4.7K
VDDQ C53 100NF VDDQ C54 100NF
15 49 15 49 C57 100NF
NBS0 DQML VDDQ C55 100NF NBS2 DQML VDDQ C56 100NF
NBS1 39 DQMH NBS3 39 DQMH NRSTFLASH 12 RESET VCCQ 47
VSS 28 VSS 28 NWE 11 WE
CAS 17 41 CAS 17 41 14
3V3 CAS CAS VSS CAS VSS N.C
RAS 18 54 RAS 18 54 3V3 13 37
RAS RAS VSS RAS VSS VPP VCC
VSSQ 6 VSSQ 6 26 CE
12 12 28 C58 100NF
VSSQ 3V3 VSSQ NRD OE
SDWE 16 46 SDWE 16 46 46
SDWE WE VSSQ WE VSSQ GND
R25 19 52 19 52 27
CS VSSQ CS VSSQ GND
470K
C
R26 0R 256 Mbits R27
470K
256 Mbits NOT POPULATED C

SDCS
R28 0R R29 470K
R30 0R NCS 3V3

3V3

NANDFLASH
R33 IDE CONNECTOR
10K J8

DUAL FOOTPRINT
MN21A !"#$!%&$'"(#) MN21B !"#$!%&$'"(#) LT1
CLE CLE 16 26 D0 CLE 16 29 D0
ALE CLE I/O0 D1 ALE CLE I/O0 D1
ALE 17 ALE I/O1 28 17 ALE I/O1 30 A B
NANDOE R31 0R RE 8 30 D2 RE 8 31 D2 C D
0R WE RE I/O2 D3 WE RE I/O2 D3
NANDWE R32 18 32 18 32 E F
CE WE I/O3 D4 CE WE I/O3 D4
NANDCS 9 CE I/O4 40 9 CE I/O4 41 RESET- 1 2
42 D5 42 D5 D7 3 4 D8
J29 I/O5 I/O5
RDYBSY R34 0R RB 7 44 D6 RB 7 43 D6 D6 5 6 D9
1K R/B I/O6 D7 R/B I/O6 D7 D5 D10
R35 46 44 7 8
WP I/O7 D8 WP I/O7 D4 D11
3V3 19 WP I/O8 27 19 WP 9 10
R37 470K 29 D9 48 D3 11 12 D12
I/O9 D10 N.C D2 D13
I/O10 31 N.C 47 13 14
B D11 D1 D14 B
1 N.C I/O11 33 1 N.C N.C 46 15 16
S2 2 41 D12 2 45 D0 17 18 D15
N.C I/O12 D13 N.C N.C
3 N.C I/O13 43 3 N.C N.C 40 3V3 R38 10K 19 20
4 45 D14 4 39 21 22
N.C I/O14 D15 N.C N.C
5 N.C I/O15 47 5 N.C PRE 38 DIOW- 23 24
6 N.C 6 N.C N.C 35 DIOR- 25 26 R39 10K 3V3
10 N.C N.C 39 10 N.C N.C 34 IORDY 27 28
11 N.C PRE 38 11 N.C N.C 33 29 30
14 N.C N.C 36 14 N.C N.C 28 INTRQ 31 32
15 3V3 15 27 A1 33 34
N.C C60 N.C N.C A0 A2
20 N.C 20 N.C 3V3 35 36
21 37 100NF 21 37 37 38
N.C VCC N.C VCC CS0- CS1-
22 N.C VCC 12 22 N.C VCC 12 39 40
23 N.C 23 N.C 3V3 41 42 3V3
24 N.C VSS 48 24 N.C 43 44
34 25 25 36 C62
N.C VSS N.C VSS 10µF
35 N.C VSS 13 26 N.C VSS 13 LT2
C59 10V
100NF
NOT POPULATED C61
100NF
IDE ATA-6

A A

C PP 10-JUI-08
B JPG 15-MAR-07
AINIT EDIT JPG 10-OCT-06
REV MODIF. DES. DATE VER. DATE
AT91SAM9263-EK SCALE
1/1 REV. SHEET

EBI0 MEMORY C 4
11
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

PSRAM
D[0..15]

A[1..21]
MN9
A1 A3 B6 D0
A2 A0 DQ0 D1
A4 A1 DQ1 C5
A3 A5 C6 D2
A4 A2 DQ2 D3
B3 A3 DQ3 D5
A5 B4 E5 D4
A6 A4 DQ4 D5
C3 A5 DQ5 F5
A7 C4 F6 D6
C A8 A6 DQ6 D7 C
D4 A7 DQ7 G6
A9 H2 B1 D8
A10 A8 DQ8 D9
H3 A9 DQ9 C1
A11 H4 C2 D10
A12 A10 DQ10 D11
H5 A11 DQ11 D2
A13 G3 E2 D12
A14 A12 DQ12 D13
G4 A13 DQ13 F2
A15 F3 F1 D14
A16 A14 DQ14 D15
F4 A15 DQ15 G1
A17 E4
A18 A16
D3 A17 3V3
A19 H1 E1
A20 A18 VCC
G2 A19
A21 H6 C63
A20
E3 NC VSS D1 100NF

R40 10K
A6 3V3
3V3 E2
NCS B5 E1
G5 R142 0R
NWR W
NOE A2 G
D6 R143 NOT POPULATED 5 1
VCC VOUT VIN
A1 C64 3
LB LB VEN
UB B2 UB VSS E6 100NF
C161 4 2 C162
M69AW048B 1µF N.C GND 1µF
MN21
LP5951MF-1.8
B B

A A

C PP 10-JUI-08
B JPG 15-MAR-07
AINIT EDIT JPG 10-OCT-06
REV MODIF. DES. DATE VER. DATE
AT91SAM9263-EK SCALE
1/1 REV. SHEET

EBI1 MEMORY C 5
11
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8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

CKSEL
MN10
MCI0_CK 1 IN1 IN2 6

2 GND VCC 5 3V3

D 3 4 C65 D
SPI0_SPCK IN0 Y 100NF
SN74LVC1G97

3V3

5
6
7
8
RR8
68K R41
10K

4
3
2
1
MCI0_CD
J9 FPS009 12
C66 100NF 8 11
MCI0_DA1
MCI0_DA0 7 10
3V3 6
5
4
3
MCI0_CDA 2
MCI0_DA3 1
MCI0_DA2 9

C
SD CARD / MMC CARD C

DATAFLASH CARD INTERFACE

3V3

5
6
7
8
RR9
68K R42
10K

4
3
2
1
MCI1_CD
J10 FPS009 12
C67 100NF 8 11
MCI1_DA1
MCI1_DA0 7 10
3V3 6
MCI1_CK 5
4
3
B B
MCI1_CDA 2
MCI1_DA3 1
MCI1_DA2 9

SD CARD / MMC CARD INTERFACE

3V3

R43 R44
2,2K 2,2K

MN11
R45 0R
SCL 6 SCL A0 1
SDA 5 SDA A1 2
R46 0R NC 3
3V3 8 VCC
C68
A
100NF 4 7 A
GND WP

SERIAL EEPROM
C PP 10-JUI-08
B JPG 15-MAR-07
AINIT EDIT JPG 10-OCT-06
REV MODIF. DES. DATE VER. DATE
AT91SAM9263-EK SCALE
1/1 REV. SHEET

MCI & TWI C 6

11
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8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

C69 100µF 6V3 3.5 PHONEJACK STEREO

J11

+
3 5
L3 742792093

CLOCK SELECTION - PIN STRAPING TABLE 2 HEADPHONE

+
L4 742792093 LINE-OUT
RA RB CODEC ID CLK FREQ C70 100µF 6V3

OUT OUT PRIMARY 24.576 MHz Local XTAL AVDD_AC97 R47 R48 C71 C72
C74 1 4
OUT IN SECONDARY 12.288 MHz Ext. BITCLK 100NF
1K 1K 470 pF 470 pF
IN OUT PRIMARY 48.000 MHz Ext. BITCLK (Into XTAL-IN) (see table)
D D
IN IN PRIMARY 14.318 MHz Ext. BITCLK (Into XTAL-IN)
R49 1K C75
RA C73 10µF
100NF 10V AGND_AC97
RB
R50 1K
R51 NOT POPULATED AGND_AC97 C76 1µF R52 22K R53 22K
EXT_CLK
C81
C77 22PF 100NF 3V3 C78 10µF

48
47
46
45
44
43
42
41
40
39
38
37

AGND_AC97
MN12
AVDD_AC97

EAPD

NC
HP_OUT_R
SPDIF

ID1
ID0
AVSS3
AVDD3

AVSS2
HP_OUT_L
AVDD2
MONO_OUT
Y3 C79 C82
24.576MHz 10µF 100NF 6 C83 100NF
10V MN13
AVDD_AC97 VDD
C80 22PF 4 -IN
1 36 Vo1 5 SPK1
DVDD1 LINE_OUT_R
2 XTL_IN LINE_OUT_L 35 3 +IN
3 XTL_OUT AVDD4 34 C84 100NF
4 DVSS1 AVSS4 33
SDATA_OUT 5 SDATA_OUT AFILT4 32 C85 270 pF
R54 47R 6 AD1981B 31 C86 270 pF
BITCLK BIT_CLK AFILT3
7 DVSS2 AFILT2 30 C87 270 pF
SDATA_IN R55 47R 8 29 C88 270 pF
SDATA_IN AFILT1 VREFOUT
9 DVDD2 VREFOUT 28 VDD/2 Av=1 8
SYNC 10 SYNC VREF 27 C89 100NF 2 Bypass Vo2 SR800SMT
RST# 11 RESET AVSS1 26
C C
12 NC AVDD1 25 C90 100NF
C91 1µF C92

CD_GND_REF
100NF 1 Shutdown Bias

PHONE_IN

LINE_IN_R
LINE_IN_L
GND

AUX_R
AUX_L

CD_ R
AGND_AC97 SSM2211

CD_L

MIC1
MIC2
7

JS1
JS0
13
14
15
16
17
18
19
20
21
22
23
24
MN20 3V3 AGND_AC97
1 A VCC 5

2 B
3 4 R56 2,2K
GND C C93 1µF R57 4.7K 3.5 PHONEJACK STEREO
SN74LVC1G66 3 J12 5
R58 2,2K L5 742792093

Need only to isolate PB3/BMS during the reset sequence C94 1µF R59 4.7K
2 LINE-IN
L6 742792093

AGND_AC97 R60 R61 C95 C96

4.7K 4.7K 470 pF 470 pF 1 4

B OPTIONAL VOICE B
FILTER COMPONENTS AGND_AC97

C97 100NF R62 100R 3.5 PHONEJACK STEREO

3 J13 5
L7 742792093
5V AVDD_AC97
L8 4.7µH 220mA C98 100NF R63 100R
2 MONO / STEREO
L9 742792093 MICROPHONE INPUT
C102 C103
C101 100NF 47 uF C99 C100 R64 R65
10µF 6V3 10NF 10NF 3,9K 3,9K C104 C105
R66 0R 1 4
10V 470 pF 470 pF

C106
AGND_AC97 470 pF
AGND_AC97

R67
OPTIONAL MIC BIASING FROM VREFOUT AVDD_AC97 0R

R68
NOT POPULATED R69 470R
VREFOUT AGND_AC97

R71 470R
A A

R70
NOT POPULATED
TO BIAS FROM VREFOUT C107 C108
CHANGE R64 and R65 to 3k 5% 10µF 10µF
DO NOT INSTALL R71, R69, C107, C108 10V 10V C PP 10-JUI-08
B JPG 15-MAR-07
AINIT EDIT JPG 10-OCT-06
VREFOUT MUST BE PROGRAMMED TO 3.7V REV MODIF. DES. DATE VER. DATE
USING VREFH BIT (REG 76h) AGND_AC97
AT91SAM9263-EK SCALE
1/1 REV. SHEET
7
AUDIO AC97 C
11
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8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

3V3 MN15 MN14 3V3

C109
16 VCC C1+ 1
C111 3V3 C112
1 C1+ VCC 16
C113 RS232 COM PORT
SERIAL DEBUG PORT 100NF 100NF 100NF 100NF
15 3V3 15
MALE RIGHT ANGLE GND GND MALE RIGHT ANGLE
C1- 3 3 C1-
C110 2 V+ 4 4 2 C114
100NF C2+ C115 C116 C2+ V+ 100NF
1 100NF R73 R74 100NF 1
6 C117 R72 100K 100K C118 6
D D
2 100NF 6 V- 5 100K 5 6 100NF 2
C2- C2- V-
7 0R R75 R76 0R 7
3 14 T 11 DTXD TXD 11 T 14 3
8 8
4 0R R77 4
R78 0R
9 7 10 RTS 10 7 9
T T
5 5
0R R79 R80 0R
13 R 12 DRXD RXD 12 R 13
11

10

10

11
0R R81
R82 0R
8 R 9 CTS 9 R 8

J14 J15
ADM3202ARNZ ADM3202ARNZ

15K R83
R84 0R 3V3
* USBCNX

C R85 C
22K R86 CAN BUS
3V3 10K

NOT POPULATED MN16

R87 0R
CANRS 8 Rs J17
1
R88 CANH 7 J16
R89 0R
1,5K 1 D 2
CANTX CANL 6
C119
J18 33PF USB DEVICE INTERFACE R90 3
R91 0R
CANRXEN 5 EN 120R
1 2 27R R92
DDM R93 0R
C120 4 R
CANRX
100NF 4 3 27R R94
DDP
C121 C122 2 GND VCC 3 3V3
6 5 15PF 15PF R95
10K SN65HVD234
C124
C123 10µF
100NF 10V

5V USB HOST INTERFACE

MN17
B 8 OUTA ENA 1 ENA B

C126 7 2
33 uF IN FLGA FLGA
C125
16V 100NF
6 GNG FLGB 3 FLGB
5 OUTB ENB 4 ENB
C127 SP2526A-2
33 uF
J19 16V
CCUSBA-32002-30X

B1 A1
B2 A2 NOT POPULATED 39R R96
HDMA
B3 A3 HDPA
B4 A4 39R R97

C130 C131
4 3 2 1 47pF 47pF R98 R99
15K 15K

C128 C129
100NF 100NF

NOT POPULATED 39R R100

HDMB
HDPB
39R R101
A A

C132
47pF C133 R102 R103
47pF 15K 15K

C PP 10-JUI-08
B JPG 15-MAR-07
AINIT EDIT JPG 10-OCT-06
REV MODIF. DES. DATE VER. DATE
AT91SAM9263-EK SCALE
1/1 REV. SHEET
8
SERIAL INTERFACES C
11
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8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D
3V3

R104 10K

1 OE VDD 4
C134
50 MHz 100NF
2 VSS OUT 3

Y4

C135
SG-8002JC-50.0000M-PCB R105 100NF
0R

GND_ETH
MN18
R106 0R 42 43 R107 R108
TX_CLK REF_CLK/XT2 XT1 49R9 49R9
17 1% 1%

15

16
TXD3 J20
18 TXD2
TXD1 19 TXD1 TX+ 7 1 TD+ TX+ 1
TXD0 20 TXD0
TX_EN 21 TX_EN 4 CT
22 TX_CLK/ISOLATE
TX- 8 2 TD- TX- 2
C C
26 RXD3/PHYAD3
R145 10K 27 RXD2/PHYAD2 AVDDT
RXD1 28 RXD1/PHYAD1
RXD0 29 RXD0/PHYAD0 RX+ 3 3 RD+ RX+ 3
R146 10K
34 RX_CLK/10BTSER 5 CT
RX_DV 37 RX_DV/TESTMODE
R147 10K 4 6 RD- RX- 6
R148 10K RX-
16 TX_ER/TXD4
RX_ER 38 RX_ER/RXD4/RPTR AVDDT
C136 L10 742792093 R109 R111 C137
3V3 R110 10K 36 1 100NF 49R9 49R9 100NF 75 75
COL/RMII AVDDR C138 C139 C140 1% 1%
75
35 CRS/PHYAD4 7 NC 4
R149 1.5K 2 100NF 10µF 10µF
3V3 AVDDR 10V 10V
24 5
MDC MDC AVDDT
25 DM9161AEP C141 GND_ETH 1nF
MDIO MDIO 75
R112 0R 32 9 100NF C142 8 7
MDINTR MDINTR AVDDT
R113 10K 100NF
R114 10K 39 5 8
DISMDIX AGND
3V3 AGND 6
46 GND_ETH 3V3 J00-0061NL
AGND GND_ETH
J21 C143 100NF 41 DVDD BGRESG 47
RJ45 ETHERNET CONNECTOR

8
7
6
5
C144 100NF 30 R115 RR2
DVDD 3V3
6,80K 10K
C145 100NF 23 1% 1K
DVDD DS4 R116 FULL DUPLEX
BGRES 48

1
2
3
4
15 DGND LEDMODE 31
B 33 11 YELLOW 1K B
DGND LED0/OP0 DS5 GREEN R117 SPEED 100
44 DGND LED1/OP1 12
LED2/OP2 13
R118 0R 10 14 1K
PWRDWN CABLESTS/LINKSTS DS6 GREEN R119 LINK&ACT
NRST 40 RESET N.C 45

3V3

C146
10µF
10V

R120 0R R121 0R

GND_ETH

A A

C PP 10-JUI-08
B JPG 15-MAR-07
AINIT EDIT JPG 10-OCT-06
REV MODIF. DES. DATE VER. DATE
AT91SAM9263-EK SCALE
1/1 REV. SHEET
9
RMII ETHERNET C
11
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8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

1/4 VGA TFT LCD DISPLAY

IMAGE SENSOR CONNECTOR R123 C148
10K 100NF
D D
3V3 C149 54132-4097
100NF
X_RIGHT
40 Y_LOW
39 X_LEFT
C147 38 Y_UP
C150 10V 37 R122 10K
36 VCTRL
100NF 10µF
35 PCI
B0 LCDD18
34 B1 LCDD19
J23 33
Z17 TX09D71VM1CCA B2 LCDD20
32
1 2 31
3 4 B3 LCDD21
VDDISI 30
5 6 B4 LCDD22
CTRL1 CTRL2 29
7 8 B5 LCDD23
SCL SDA 28
9 10 ISI_MCK 27 B[0..5]
11 12 G0 LCDD10
ISI_VSYNC 26
13 14 G1 LCDD11
ISI_HSYNC 25
15 16 G2 LCDD12
ISI_PCK 24
17 18 ISI_D0
ISI_D1 ISI_D2 23 G3 LCDD13
19 20 22
ISI_D3 21 22 ISI_D4 G4 LCDD14
ISI_D5 ISI_D6 21 G5 LCDD15
23 24 20
ISI_D7 25 26 ISI_D8
19 G[0..5]
ISI_D9 27 28 ISI_D10 R0 LCDD2
ISI_D11 18 R1 LCDD3
29 30 17 R2 LCDD4
16
C 15 R3 LCDD5 C
ISI_D[0..11] 14 R4 LCDD6
13 R5 LCDD7
12
11 R[0..5]
10
9
8 DTMG
7
6 HSYNC
5
4 DCLK
3
2
1 3V3

J22 C151 C152

100NF 10µF
10V

3V3

R124
B TOUCH SCREEN CONTROLLER 100K B

MN19 R125 47R

X_LEFT 2 16
XP DCLK SPCK
Y_UP 3 14
YP DIN MOSI
X_RIGHT 4 12
XM DOUT MISO
Y_LOW 5 15 R126 0R
YM CS NPCS
13 R127 0R BUSY
BUSY
11 R128 0R IRQ
PENIRQ

R130 VREF 9 3V3

100K
7 IN3 VCC 1 R129 0R L11 4.7µH 220mA
8 IN4 VCC 10
R131 100K C154
TP71 TP72 100NF R132 C153
10µF
GND 6
C155 NOT POPULATED
AGND ADS7843E 100NF C156 R133 0R
100NF
TP73 TP74

TWO USER'S ANALOG INPUTS

Full-Scale Input Span 0 to VREF

A A

C PP 10-JUI-08
B JPG 15-MAR-07
AINIT EDIT JPG 10-OCT-06
REV MODIF. DES. DATE VER. DATE
AT91SAM9263-EK SCALE
1/1 REV. SHEET

LCD & ISI C 1011

This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

PA[0..31] PC[0..31]

PB[0..31] PD[0..31]
D PE[0..31] D

J24 J25

1 2 1 2
MCI1_CDA PA7 3 4 PA6 MCI1_CK/PCK2 RXD1/SPI0_NPCS3 PD1 3 4 PD0 TXD1/SPI0_NPCS2
MCI1_DA1 PA9 5 6 PA8 MCI1_DA0 RXD2/SPI1_NPCS3 PD3 5 6 PD2 TXD2/SPI1_NPCS2
MCI1_DA3 PA11 7 8 PA10 MCI1_DA2 EBI0_NWAIT/RTS2 PD5 7 8 PD4 FIQ/DMARQ2
TWCK/RF0 PB5 9 10 PB4 TWD/RK0 EBI0_NCS5/CFCS1/RTS1 PD7 9 10 PD6 EBI0_NCS4/CFCS0/CTS2
11 12 PB6 TF1/DMARQ1 EBI0_CFCE2/SCK2 PD9 11 12 PD8 EBI0_CFCE1/CTS1
SPI1_MOSI PB13 13 14 PB12 SPI1_MISO EBI0_NCS2/TSYNC PD11 13 14 PD10 SCK1
SPI1_NPCS0 PB15 15 16 PB14 SPI1_SPCK EBI0_A24/TPS0 PD13 15 16 PD12 EBI0_A23/TCLK
SPI1_NPCS2/TIOA2 PB17 17 18 PB16 SPI1_NPCS1/PCK1 17 18 PD14 EBI0_A25_CFRNW/TPS1
PB19 19 20 PB18 SPI1_NPCS3/TIOB2 PE17 19 20 PE16
PB21 21 22 PB20 TIOB0 PE19 21 22 PE18 TIOA0
PB23 23 24 PB22 23 24 PE22 ECRS/EBI1_NCS2/NANDCS
PB25 25 26 PB24 25 26
PB27 27 28 PB26 PC13 27 28 PC0 LCDVSYNC
PB29 29 30 PB28 LCDD17/ETX3 PC21 29 30 PC28 PWM0/TCLK1
PB31 31 32 PB30 31 32 PC20 LCDD16/ETX2
33 34 33 34
3V3 35 36 3V3 3V3 35 36 3V3
37 38 37 38
39 40 39 40

S3
5V
C C

USER'S GRID AERA

3V3 5V

+ $ ,
B B

3V3 5V

+ $ ,

A A

C PP 10-JUI-08
B JPG 15-MAR-07
AINIT EDIT JPG 10-OCT-06
REV MODIF. DES. DATE VER. DATE
AT91SAM9263-EK SCALE
1/1 REV. SHEET
11
C
EXPANSION CONNECTORS
11
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

8 7 6 5 4 3 2 1
 Section 6
Warning

6.1 BMS Signal Sampling

The following behavior and its consequences are related to an AT91SAM9263 device issue described in
the Errata section of the AT91SAM9263 datasheet (“BMS: BMS does not have correct state”). The text
below is a reminder of this issue and a Workaround proposal at the board level.
Description
The BMS signal, which is multiplexed with the PB3/AC97RX PIO needs to be sampled at a High Level
for the AT91SAM9263 microcontroller to boot out of the internal ROM.
At power up, the on-board AC97 device negates its “SDATA_IN” output pin and due to this fact, the
BMS_PB3/AC97RX pin needs to be isolated during the reset phase.
The MN20 gate, controlled by the NRST signal, achieves this, but with the default ERSTL value in the
reset controller (refer to the RSTC section in the AT91SAM9263 datasheet for more details), when the
VDDBU power supply is applied for more than 1.2 seconds before the VDDCORE power supply, the
AT91SAM9263 microcontroller samples the BMS signal one Slow Clock (SLCK) cycle after the NRST
signal rising (See Figure 6-1).
As a result, the BMS signal is sampled at a Low Level and the AT91SAM9263 boots out of the external
EBI device connected to NCS0.

AT91SAM9263-EK Evaluation Board Rev. B User Guide 6-1

6341D–ATARM–30-Sep-09
Warning

Figure 6-1. BMS Signal Sampling

SLCK

Any
MCK Freq.

Backup Supply
(VDDBU)
POR output Startup Time

backup_nreset
Processor Startup
= 3 cycles
processor_nreset

NRST
(nrst_out)

EXTERNAL RESET LENGTH

= 2 cycles

BMS_PB3/AC97RX

BMS signal sampling

Workaround:
At the first VDDBU power up or if this power supply has been shut down (J4-1 opened
(VDDBU/VDDBACKUP Jumper) or the CR1225 battery cell (J3) removed or changed), the following
power-up sequence has to be applied in order to boot out of the internal ROM:
1. Close J2 to force power on
2. Open J5 (Boot Mode Select Jumper)
3. Power on the board
4. Remove and replace J4-1 (VDDBU/VDDBACKUP Jumper)

6-2 AT91SAM9263-EK Evaluation Board Rev. B User Guide

6341D–ATARM–30-Sep-09
 Section 7
Revision History

7.1 Revision History

In the following table the most recent version of the document appears first.

Table 7-1.
Change
Document Comments Request Ref.
PE17 and PE19 information removed from ‘Peripheral Usage’ column in Table 3-5, “PIO Controller
6341D 6694
E,” on page 3-11
Section 1.5 ”NAND Flash Access Issue” on page 1-3 edited 6024
6341C
Row R30 and note (2) added to Table 4-1 on page 4-1 6057
Section 1.2, ” How to Identify the Kit BOM Revision”, added to this user guide.
Section 1.3, ” How to Identify the PCB Revision”, updated.
5626
Section 1.4, ” How to Identify the SAM9263 Silicon Revision”, added to this user guide
6341B Section 1.5, ” NAND Flash Access Issue”, added to this user guide.
Section 5.1, ” Schematics”, updated with rev C schematics. 5626
(“Audio AC97” schematic updated) 5082
Table 4-1, “Configuration Jumpers and Straps,” on page 4-1, added J5-7 and J29 5391
6341A First issue.

AT91SAM9263-EK Evaluation Board Rev. B User Guide 7-1

6341D–ATARM–30-Sep-09
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6341D–ATARM–30-Sep-09