The PIC18F452 Instruction Set

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ASEN 4519/5519 Lecture #5

PIC Architecture
Program Address Operand Address

Program Memory

15 bits CPU
Instruction

12 bits
Data

16 bits

8 bits

Operand Memory (SFR & RAM)

TBLPRTH

15 bits

TBLPTRL TABLAT

8 bits
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ASEN 4519/5519 Lecture #5

Reading data from program memory

Operand (data) memory is limited Static data such as strings or tables should be stored elsewhere The PIC18F452 provides a mechanism to access static data in flash program memory Due to Harvard architecture data must be accessed from the operand bus The following three registers are used
TBLPTRH:TBLPTRL table pointer high and low (address 15 bit bus) TABLAT table latch (data -8 bit bus)

Access is similar to indirect addressing

TBLPTR provides the address to access in program memory similar to FSR TABLAT provides the register for putting the data similar to the WREG There are 4 access modes
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ASEN 4519/5519 Lecture #5

Table pointer access modes

TBLRD*
Move the 8 bit value at location TBLPTRH:TBLPTRL to TABLAT. TBLPTR remains unchanged

TBLRD*+
Move the 8 bit value at location TBLPTRH:TBLPTRL to TABLAT. TBLPTR is incremented

TBLRD* Move the 8 bit value at location TBLPTRH:TBLPTRL to TABLAT. TBLPTR is decremented

TBLRD+*
TBLPTR is first incremented then the 8 bit value at location TBLPTRH:TBLPTRL is moved to TABLAT.
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ASEN 4519/5519 Lecture #5

Table pointer example

Freq_Hz movlw movwf movlw movwf TBLRD* movf db \x80FREQ Hz\x00 high Freq_Hz TBLPTRH low Freq_Hz TBLPTRL TABLAT, W

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STATUS register

Status register is a SFR, address 0xFD8 Bits 0-4 indicate status of WREG Not all commands change status register Conditional statements branch on value of status register bits

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Program Instruction Sequencing

PIC18F452 has 3 special addresses
0x0000 the reset vector 0x0008 the high-priority interrupt vector 0x0018 the low-priority interrupt vector

On power-up or reset the system vectors to 0x0000 When an interrupt occurs the system saves the current register information and vectors to either address 0x0008 or 0x0018 depending if a low-priority or high-priority interrupt occured

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ASEN 4519/5519 Lecture #5

The Program Counter

20 bit register
PCL, 0xFF9 PCLATH, 0xFFA PCLATU, 0xFFB

PCLATU is reserved for expansion The address PCLH:PCL points to the next instruction to execute in program memory The program counter is incremented by 2 bytes after each instruction fetch, because the instructions are 2 bytes wide.

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ASEN 4519/5519 Lecture #5

The Program Counter

PCLATU

PCLATH

20

16

15

8 Transfer on read of PCL

Transfer on write of PCL 20

PCL PCLU
16 15

PCLH
8 7 0

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ASEN 4519/5519 Lecture #5

The Program Counter

The program counter does not advance by 2 bytes on the following conditions
Reset, PCL=0x0000 Interrupt, PCL=0x0008 or 0x0018 Goto statement, vector to specified location Branch statement, vector to specified location if condition is satisfied Subroutine Call, vector to the location of the subroutine Subroutine return, vector to the last location before the subroutine call

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The Instruction Set

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Move Instructions
Mnemonic
movlw k movwf f (banked) movff fs,fd movf, f, F/W (banked) movlb k

Description
Move literal to WREG Move WREG to f

W
1 1

O
1 1

Stat
-

Move fs to fd, both using full 12 bit address Move f to F or WREG Move literal value to BSR<3;0>, where k=0,15

2 1 1

2 1 1

Z,N -

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Other move like Instructions

Mnemonic
lfsr i,k clrf f (banked) setf f (banked) swap f, F/W (banked)

Description
Load FSRi, i=0,1,2, with 12-bit address k Clear f, address f is set to 0

W
2 1

O
2 1

Stat
Z

Address f is set to 0xff Swap the high and low nibble in f put result in either F or WREG

1 1

1 1

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Bitwise operations
Mnemonic
bcf f, b (banked) bsf f, b (banked) btg f, b (banked) btfsc f, b (banked) btfss f, b (banked)

Description
Clear bit b in register f where b=0-7 Set bit b in register f where b=0-7

W
1 1

O
1 1

Stat
-

Toggle bit b in register f where b=0-7 Test bit b of register f, where b=0-7. If 1 then skip next instruction. Increment PCL by 2 Test bit b of register f, where b=0-7. If 0 then skip next instruction. Increment PCL by 2

1 1 1

1 1(2) 1(2)

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Byte operations
Mnemonic
rlcf f, F/W (banked) rlncf f, F/W (banked) rrcf f, F/W (banked) rrncf f, F/W (banked) incf f, F/W (banked) decf f, F/W (banked) comf f, F/W (banked) negf f (banked)

Description
Copy f into F or WREG; rotate F or WREG through carry bit (9-bit rotate left) Copy f into F or WREG; rotate F or WREG without carry bit (8-bit rotate left) Copy f into F or WREG; rotate F or WREG through carry bit (9-bit rotate right) Copy f into F or WREG; rotate F or WREG without carry bit (8-bit rotate right) Increment f putting result in F or WREG Decrement f putting result in F or WREG Complement f putting result in F or WREG

W
1 1

O
1 1

Stat
C,N,Z N,Z

1 1 1 1 1

1 1 1 1 1

C,N,Z N,Z C,DC,Z,OV, N C,DC,Z,OV, N Z,N

Change sign of a twos complement coded number

C,DC,Z,OV, N

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Rotate Left
Carry 0 11101010 WREG RLCF Carry 1 11010100 WREG
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Carry 0 11101010 WREG RLNCF Carry 0 11010101 WREG

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Rotate Right
Carry 1 11101010 WREG RRCF Carry 0 11110101 WREG
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Carry 1 11101010 WREG RRNCF Carry 1 01110101 WREG

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Logic operations
Mnemonic
andlw k andwf f, F/W (banked) iorlw k

Description
AND literal value into WREG AND WREG with f, putting result in F or WREG Inclusive-OR literal value into WREG

W
1 1 1

O
1 1 1

Stat
Z,N Z,N Z,N

iorwf f, F/W (banked) xor k xorwf f, F/W (banked)

Inclusive-OR WREG with f, putting result in F or WREG Exclusive-OR literal value into WREG Exclusive-OR WREG with f, putting result in F or WREG

1 1 1

1 1 1

Z,N Z,N Z,N

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AND Truth Table

A 0 0 1 1

B 0 1 0 1

A (AND) B 0 0 0 1

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IOR Truth Table

A 0 0 1 1

B 0 1 0 1

A (IOR) B 0 1 1 1

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XOR Truth Table

A 0 0 1 1

B 0 1 0 1

A (XOR) B 0 1 1 0

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Math operations - Add

Mnemonic
addlw k addwf f, F/W (banked) addwfc f, F/W (banked) daw

Description
ADD literal value into WREG ADD WREG with f, putting result in F or WREG ADD WREG with f and carry bit, putting result in F or WREG Decimal adjust sum of two packed BCD digits to correct packed BCD results in WREG

W
1 1 1

O
1 1 1

Stat
C,DC,Z,OV, N C,DC,Z,OV, N C,DC,Z,OV, N C

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Math operations - Subtract

Mnemonic
sublw k subwf f, F/W (banked) subwfb f, F/W (banked) subfwb f, F/W (banked)

Description
Subtract WREG from literal value and put result in WREG Subtract WREG from f putting result in F or WREG Subtract WREG and borrow bit from f putting result in F or WREG Subtract f and borrow bit from WREG putting result in F or WREG

W
1 1 1 1

O
1 1 1 1

Stat
C,DC,Z,OV, N C,DC,Z,OV, N C,DC,Z,OV, N C,DC,Z,OV, N

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Math operations - Multiply

Mnemonic
mullw k mulwf f (banked)

Description
Multiply WREG with literal value, putting result in PRODH:PRODL (WREG remains unchanged) Multiply WREG with f, putting result in PRODH:PRODL (WREG and f remain unchanged)

W
1 1

O
1 1

Stat
-

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Branch operations
Mnemonic
bra label goto label bc label bnc label bz label bnz label bn label bnn label bov label bnov label

Description
Branch to labeled instruction (within +1027/-1028? oneword instructions) Go to labeled instruction anywhere If carry bit (c=1), then branch to labeled instruction (within -128/+127? one-word instructions) If carry bit (c=0), then branch to labeled instruction (within -128/+127? one-word instructions) If zero bit (z=1), then branch to labeled instruction (within -128/+127? one-word instructions) If zero bit (z=0), then branch to labeled instruction (within -128/+127? one-word instructions) If negative bit (n=1), then branch to labeled instruction (within -128/+127? one-word instructions) If negative bit (n=0), then branch to labeled instruction (within -128/+127? one-word instructions) If overflow bit (ov=1), then branch to labeled instruction (within -128/+127? one-word instructions) If overflow bit (ov=0), then branch to labeled instruction (within -128/+127? one-word instructions)

W
1 2 1 1 1 1 1 1 1 1

O
2 2 1(2) 1(2) 1(2) 1(2) 1(2) 1(2) 1(2) 1(2)

Stat
-

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Unconditional Branch

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Branch if Not Zero

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Byte conditional tests

Mnemonic
cpfseq f (banked) cpfsgt f (banked) cpfslt f (banked) tstfsz f (banked) decfsz f, F/W (banked) dcfsnz f, F/W (banked) incfsz f, F/W (banked) iccfsnz f, F/W (banked)

Description
Skip if f is equal to WREG Skip if f is greater than WREG (unsigned compare)

W
1 1

O
1(2) 1(2)

Stat
-

28

Skip if f is less than WREG (unsigned compare)

1(2)

Test f, skip if zero

1(2)

Decrement f, putting result in F or WREG, skip if zero

1(2)

Decrement f, putting result in F or WREG, skip if not zero

1(2)

Increment f, putting result in F or WREG, skip if zero

1(2)

Increment f, putting result in F or WREG, skip if not zero

1(2)

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ASEN 4519/5519 Lecture #5

Subroutines
Mnemonic
rcall label call label call label, FAST

Description
Call labeled subroutine (within -1024,+1023 one-word instructions) Call labeled subroutine anywhere Call labeled subroutine anywhere; copy state to the shadow registers, WREG to WS, STATUS to STATUSS, and BSR to BSRS Return from subroutine Return from subroutine; restore state of the shadow registers, WS to WREG, STATUSS to STATUS, and BSRS to BSR Return from subroutine, put literal value in WREG Return from interrupt, reenable interrupts Return from interrupt, restore state of the shadow registers, WS to WREG, STATUSS to STATUS, and BSRS to BSR, reenable interrupts

W
1 2 2

O
2 2 2

Stat
-

return return, FAST

1 1

2 2

C,DC,Z,OV, N C,DC,Z,OV, N

retlw k retfie Retfie FAST

1 1 1

2 2 2

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Rcall Statement

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Table Read

Mnemonic
tblrd* tblrd*+ tblrd*tblrd+*

Description
Read from program memory value pointed to by TBLPTR into TABLAT Read from program memory value pointed to by TBLPTR into TABLAT, then increment TBLPTR Read from program memory value pointed to by TBLPTR into TABLAT, then decrement TBLPTR Increment TBLPTR then read from program memory value pointed to by TBLPTR into TABLAT

W
1 1 1 1

O
2 2 2 2

Stat
-

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Other Commands
Mnemonic
push pop clrwdt sleep reset nop

Description
Push the address of the next instruction onto the stack Discard address on to of the stack Clear watchdog timer Go into standby mode Software reset, set PCL to 0x0000, reset all registers and flags affected by MCLR No operation

W
1 1 1 1 1 1

O
1 1 1 1 1 1

Stat
C,DC,Z,OV, N -

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Homework
LECTURE WEDNESDAY 14-SEP-05 Read Chapter 5 of Peatman Read over Lab #2, will be on the web soon LAB FRIDAY 16-SEP-05 Lab #2

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