VLSI Content in B.

TECH
Subject 1:VLSI DESIGN UNIT I Introduction: Basic principle of MOS transistor, Introduction to large signal MOS models (long channel) for digital design. The MOS Inverter: Inverter principle, Depletion and enhancement load inverters, the basic CMOS inverter, transfer characteristics, logic threshold, Noise margins, and Dynamic behavior, Propagation Delay, Power Consumption. UNIT II MOS Circuit Layout & Simulation : MOS SPICE model, device characterization, Circuit characterization, interconnects simulation. MOS device layout: Transistor layout, Inverter layout, CMOS digital circuits layout & simulation. UNIT III Combinational MOS Logic Design: Static MOS design: Complementary MOS, Ratioed logic, Pass Transistor logic, complex logic circuits. Dynamic MOS design: Dynamic logic families and performances. UNIT IV Sequential MOS Logic Design & Clock Distribution: Static latches, Flip flops & Registers, Dynamic Latches & Registers, CMOS Schmitt trigger, Monostable sequential Circuits, Astable Circuits. Memory Design: ROM & RAM cells design Clock Distribution : Interconnect delays, Cross Talks, Clock Distribution. Introduction to low power design, Input and Output Interface circuits. UNIT V BiCMOS Logic Circuits & ASICs: Introduction, BJT Structure & operation, Basic BiCMOS Circuit behavior, Switching Delay in BiCMOS Logic circuits, BiCMOS Applications ASICS: Types of ASICs Design flow Economics of ASICs ASIC cell libraries CMOS logic cell data path logic cells I/O cells cell compilers. Subject 2:IC TECHNOLOGY UNIT-I INTRODUCTION TO TECHNOLOGIES: Semiconductor Substrate-Crystal defects, Electronic Grade Silicon, Czochralski Growth, Float Zone Growth, Characterization & evaluation of Crystals; Wafer Preparation-Silicon Shaping, Etching and Polishing, Chemical cleaning. UNIT-II DIFFUSION & ION IMPLANTATION: Ficks diffusion Equation in One Dimension Atomic model, Analytic Solution of Ficks law, correction to simple theory, Diffusion in SiO2 lon Implantation and lon Implantation Systems Oxidation. Growth mechanism and Deal-Grove Model of oxidation, Linear, and Parabolic Rate coefficient, the structure of SiO2 Oxidation techniques and system Oxide properties. UNIT-III CHEMICAL VAPOUR DEPOSTTION AND LAYER GROWTH: CVD for deposition of dielectric and polysilicon- a simple CVD system, Chemical equilibrium and the law of mass action, Introduction to atmospheric CVD of dielectric, low pressure CVD of dielectric and semiconductor, Epitaxy-Vapour

Phase Expitaxy, Defects in Epitaxial growth, Metal Organic Chemical Vapor Deposition, Molecular beam epitaxy. UNIT-IV PATTERN TRANSFER: Introduction to photo/optical lithography, Contact/proximity printers, Projection printers, Mask generation, photoresists, Wet etching, Plasma etching, Reaction ion etching. UNIT-V VLSI PROCESS INTEGRATION: Junction and Oxide Isolation, LOCOS methods, Trench Isolation, SOI Metallization, Planarization. Fundamental consideration for IC Processing, NMOS IC Technology, CMOSIC Technology, Bipolar IC Technology. Subject 3: HARDWARE DESCRIPTION LANGUAGES UNIT I Introduction To Hardware Design: Digital System Design Process, Hardware Description Languages, Hardware Simulation, Hardware Synthesis, Levels of Abstraction UNIT II Basics of VHDL: Writing Entities for Digital circuits like decoders, registers etc, Scalar Data types and Operations: Object types: constants, variables, signal and files. Data Types: scalar, integer, floating, physical, enumeration, type declarations, subtypes, expressions and operators for various types. Sequential statements: If, case, Null, Loop, Exit, Next statements, while loops, For loops, Assertion and report statements Composite Arrays: arrays, Array aggregates, unconstrained array types, strings, Bit vectors, Standard Logic Arrays, array operations and records UNIT III VHDL Programming: Behavioral Modeling: process statements, variable and signal assignments, inertial and transport delay models, signal drivers, multiple and postponed processes Dataflow Modeling: Concurrent signal assignment, multiple drivers, block statement Structural Modeling: component declaration, component instantiation, resolving signal values, and configuration: basic configuration, configuration for structural modeling, mapping library entities. Generics, generic (AND, NAND, OR, NOR, XOR and XNOR) gates, functions and subprograms, packages and libraries UNIT IV Synthesis: mapping statements to gates: Writing a test bench, converting real and integers to time, dumping and reading from text file Vhdl modeling of basic gates, half and full adder AOI, IOA, OAI, multiplexes, decoders (dataflow, behavioral and structural modeling), three state driver, parity checker, D, T, JK and SR flip flops, flip flops with preset and clear, modeling for multiplexer, priority encoder, ALU etc, modeling regular structures, delays, conditional operations, synchronous logic, state machine modeling, Moore and Mealy machines, generic priority encoder, clock divider, shift registers, pulse counter etc .FPGA Architectures and Technology,VHDL Synthesis for FPGA Implementation UNIT V SysyemC: Overview Of SystemC,Abstraction Models,Data Types,A Notion Of Time,Concurrency,Basic Channels, TLM-based Methodology.

Lab:VLSI LAB I.Design, simulation & Synthesis of different digital circuits with the help of software For VHDL/Verilog(Xilinx and Modelsim) and also test on FPGA Board. II. Design & simulation of following circuits with the help of software for Back Hand Design Tool (Tanner Tool/ Cadence IC Station) 1. Layout of CMOS inverter 2. Layout of NAND and NOR gates 3. Layout of One bit full adder simulation. 4. Layout of SR latches using NAND representations. 5. Layout of D flips flop.

VLSI Content in M.TECH

Subject 1: SYSTEM DESIGNS USING FPGA:
Introduction to ASICs:The custom de-sign alternatives Definitions of FPGAs, Differences from PLDs, MPGAs (Mask Programmable Gate Ar-rays), Tradeoffs in ASIC implementation using PALs, EPLDs, FPGAs, traditional gate arrays or fully custom design, Advantages of FPGAs, Overview of design flow. Logic design: Implementing combinational and sequential logic circuits with a certain building block only - for example MUXs, ROM or Look up Table (LUT), decoders,PALs, PLAs, etc. Symmetrical Array, Row-based, Hierarchical PLD, Sea of Gates and Sea of Tiles FPGA Architectures, Desirable Features of a Programming Technology, Programming Technologies in use in commercial FPGAs, Comparison of the commercial programming technologies, Logic Block,Architectures in Commercial FPGAs Design Entry Methods: Schematic capture, Introduction to VHDL, Verilog, Design Flow, Synthesis, Design translation steps, Basics on library based, LUT based and MUX based mapping schemes, Basics on Mincut, Simulated Annealing and General Force-Directed Relaxation, Basics on Global routing and Detailed Channel Routing. Basic Principles of Boundary Scan: IEEE Standard, Boundary Scan in Commercial FPGAs,PREP Benchmarks, Performance Metrics, Equivalent Gates, Programming Overhead, Testability.Security Issues Rapid Prototyping: Field Programmable,Interconnect Chips, Field Programmable Boards,Field Programmable BackplanesDynamically Reconfigurable Systems, Reconfiguring for System Diagnostics, Reconfiguring for Multipurpose hardware, Reconfigurable Computing.

Subject 2: HDLs FOR EMBEDDED SYSTEM:

Basics of VHDL, capabilities, hard ware abstraction, entity declaration, model analysis,simulation, identifiers, data objects, data types, operators. Modeling:Behavioral modeling, dataflow modeling, structural modeling, Connectivity:Generics and configurations, subprograms and overloading, packages and libraries. Advanced features:model simulation, hardware modeling examples

Subject 3: VLSI ARCHITECTURE FOR SIGNAL PROCESSING & COMMUNICATION SYSTEMS:

Introduction and preliminaries Course overview, VLSI signal processing design methodology DSP preliminaries: sampling, A/D and D/A conversion, DSP algorithm representations, filter structures, folding transformation Stochastic signal processing basics VLSI preliminaries: power, area, speed and noise immunity Inner receiver design techniques Retiming, look ahead pipeline, block/parallel processing, unfolding, transformation folding transformation, algebraic transformation, relaxed look ahead transformation Analysis of programmable general purpose architectures MP, MC, DSP, ASIC Typical CPU structures for high speed multiply and accumulate (MAC) High speed control and interrupt system architectures Bus systems and principles of memory technology Development tools and testing methodology Introduction in to real time signal processing (key component of real time hardware platforms) Decorrelating transforms Outer receiver design techniques, finite-field arithmetic basics, finite-field arithmetic architectures, Reed Solomon codes: introduction, Reed Solomon decoding algorithms and architectures Convolutional codes: introduction Viterbi algorithms and architectures Advanced topics and applications Turbo codes: algorithms Turbo codes architectures Encryption: introduction to algorithms Encryption: VLSI architectures Fault-tolerant signal processing techniques, Video compression algorithms and architectures Putting it all together: design of a broadband communication system VHDL design methodology for dedicated integrated systems, including FPGAs and ASICs

Subject 4: MEMORY DESIGN AND TESTING:

Introduction to Semiconductor Memories and Technologies; Basic Memory Elements, Circuits and Cells. 1. SRAM and DRAM Cell Design: Basic Structures, Modeling and Design Equations. 2. Sense Amplifiers; Voltage and Current Sense Amplifiers; Reference Voltage Generation; Voltage Converters. 3. Cache Memory Design. 4. Memory Testing; Reliability and Yield; Radiation Effects.