TSINGHUA SCIENCE AND TECHNOLOGY ISSNll1007-0214ll09/16llpp285-289 Volume 16, Number 3, June 2011

Enhanced Offset Averaging Technique for Flash ADC Design

Siqiang FAN1, He TANG2, Hui ZHAO2, Xin WANG2, Albert WANG2,**, Bin ZHAO1, Gary G ZHANG3
1. Freescale Semiconductor, Inc, Irvine, CA 92618, USA; 2. Department of Electrical Engineering, University of California, Riverside, CA 92521, USA; 3. Skyworks Solutions, Inc., Irvine, CA 92617, USA Abstract: This paper presents a new combined AC/DC-coupled output averaging technique for input amplifier design of flash analog-to-digital converters (ADC). The new offset averaging design technique takes full advantage of traditional DC-coupled resistance averaging and AC-coupled capacitance averaging techniques to minimize offset-induced ADC nonlinearities. Circuit analysis allows selection of optimum resistance and capacitance averaging factors to achieve maximum offset reduction in ADC designs. The new averaging method is verified in designing a 4 bit 1 Gs/s flash ADC that is implemented in foundry 0.13 m CMOS technology. Key words: analog-to-digital converter; flash analog-to-digital converters (ADC); integrated circuit (IC); offset averaging; resistor averaging; capacitor averaging

Introduction
High-speed ADCs are essential to high-performance systems, such as disk drive read channels, fiber optic receiver front-end and data communication links using multilevel signaling. Flash ADC structure is the architecture of choice for ADCs featuring very high sampling rates and low to moderate resolution. For highspeed ADCs designed in advanced integrated circuit (IC) technologies, a reduced power supply voltage is essential to prevent CMOS gate oxide breakdowns, which, in turn, requires smaller signal swings that can significantly affect the critical signal-to-noise ratio (SNR). As the signal quantization level decreases, the offset-introduced integral non-linearity (INL) and differential non-linearity (DNL) will become a severe problem in ADC designs. It is well-known that the static and dynamic offset reduction is a challenge in flash type ADC designs. Meanwhile, low-voltage
Received: 2010-01-05; revised: 2011-04-06

low-power ADCs are highly desired potable electronics to improve operation hours. Apparently, complex design tradeoffs among power dissipation, sampling speed, resolution, and chip size are challenging ADC design tasks. Though some offset averaging techniques have been demonstrated to effectively reduce the DNL and INL of flash ADCs where the averaging devices can be resistors or capacitors used to reduce the offset of the amplifiers, advanced flash ADCs require further offset reduction in designs. This paper presents an enhanced coupled resistor-capacitor offset averaging design technique to achieve better amplifier offset reduction in flash ADC circuitry.

1
1.1

Offset Averaging Techniques

Traditional resistance averaging

* To whom correspondence should be addressed.

E-mail: aw@ee.ucr.edu; Tel: 1-951-827-2555

A popular technique for reducing the offsets of amplifiers in ADCs is resistance averaging introduced by Kattmann and Barrow[1]. The resistance averaging concept is depicted in Fig. 1 for its typical circuit network, where outputs of the amplifiers are interconnected via averaging resistors. Figure 2 shows its

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equivalent model circuit. R1 is the load resistor of the amplifiers and R2 is the averaging resistor. The offset reduction is realized by the weighted averaging function of the averaging resistors R2 and the output impedance of R1. In an ideal case with an infinite resistor string network formed by R1s and R2s, the weighted averaging resistance, RX , is given by 1 1 2 RX = R2 + R2 + R1 R2 (1) 2 4

the capacitance averaging circuit network and its equivalent model circuit, respectively, where capacitance averaging is realized using a DC capacitor coupling network.

Fig. 3

Conventional capacitance averaging implementation

Fig. 1 Conventional resistance averaging implementation Fig. 4 Equivalent model circuit for the conventional capacitance averaging network

Fig. 2 Equivalent model circuit for conventional resistance averaging network

Further, reduction of the offset-induced INL can be calculated as[2]

2U ni RX ( R1 || RX + R2 )2 + ( R1 || RX )2 = 2U 0 RX + 2 R1 ( R1 || RX + R2 ) 2 ( R1 || RX )2
(2) The reduction of the offset-induced DNL is derived as 2 (U ni +1 U ni ) = 2U 0
RX R2 ( R1 + RX ) (3) 2 RX + 2 R1 R1 ( RX + R2 ) + RX ( R1 + R2 ) However, in a real implementation, since the resistance averaging network cannot be infinite, these formulas for offset reduction will be multiplied by a factor determined by the number of amplifiers operating in the linear region and the resistance averaging efficiency will be discounted. Beyond the linear range of the amplifiers, current clipping will result in errors[3,4]. 1.2 DC-coupled capacitance averaging
2

The capacitance averaging principle follows. In the tracking mode, the pre-amplifiers, which drive the distributed track and hold modes, generate an array of zero-crossing currents. Lateral capacitors C1 are connected to the adjacent nodes. In this mode, the main mismatching errors are the offset currents, which cannot be averaged by the network because the lateral capacitors appear as an open circuit to static currents. During the hold mode, the switches open and the random mismatching errors are averaged by charge redistribution across the capacitor network as shown in Fig. 4. The offset reduction can be estimated as follows. For an infinite capacitor string of C1s and C2s, the capacitance network can be replaced by a capacitor CX given by 1 2 1 CX = C2 + C1C2 C2 (4) 4 2 where C2 is the input parasitic capacitance of the next stage. Apparently, Eq. (4) is similar to Eq. (1), hence, capacitance averaging works similarly as resistance averaging. Therefore, Eqs. (3) and (4) can be used to estimate the offset-inducted INL and DNL for ADCs.
1.3 AC-coupled capacitance averaging and interpolation

Alternatively, the capacitance averaging technique may be used for averaging-based offset reduction[5], which is described in Figs. 3 and 4. Figures 3 and 4 show

Capacitance averaging can be alternatively realized using an AC-coupled capacitance averaging mode[6]. Figure 5 illustrates the conceptual circuit for the ACcoupled capacitance averaging technique where the input capacitor is split into two equal halves, each

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being connected to the two input voltage nodes, V0 and V1. When the amplifier is in reset mode, the two capacitors are charged to V0 and V1, respectively. During the amplification mode, the charges on the capacitors are redistributed and an output voltage at the average value of V0 and V1 is generated. Consequently, the mismatch error is reduced by the averaging effect.

Fig. 5 Two-AC-coupled capacitance averaging

Because the output voltage of the AC-coupled capacitance averaging is set at the middle of the two input voltage levels, a practical flash ADC can be designed using two different averaging structures as shown in Fig. 6. Figure 6a illustrates the first averaging method where an even number of the amplifier stages gives a correct output decision level while an odd number of amplifier stages gives a one half LSB offset. In the second averaging scheme depicted in Fig. 6b, the correct output decision level can be generated for both even and odd numbers of amplifier stages.

Fig. 7

Capacitance interpolation with averaging

that, while the DC-coupled averaging techniques can reduce offset-induced ADC nonlinearity effects without suffering a speed penalty[5,7], performance limitation exits. For example, DC-coupled resistor averaging leads to amplifier gain reduction, while capacitor averaging has limited averaging effect. Combining the AC-coupled averaging technique into the DC-coupled scheme will further improve the offset reduction result. This section discusses the new combined DC/ACcoupled offset averaging technique, which can further enhance the offset reduction efficiency.
2.1 Combined DC/AC-coupled offset averaging mechanism

(a) (b) Fig. 6 AC-coupled capacitance averaging circuit scheme in practical designs

In addition, since the output of the AC-coupled capacitance averaging network is at the middle of the two input voltage levels, the averaging may be improved by integrating the interpolation technique into the averaging network as shown in Fig. 7[2]. In the averaging and interpolation scheme, since the averaging factor is 1.5 at the edge, instead of 2, a dummy amplifier is normally added to resolve this problem.

New Enhanced Offset Averaging Technique for Flash ADC Design

From the proceeding discussions, it becomes obvious

Figure 8 shows a simple circuit scheme utilizing the new combined DC/AC-coupled offset averaging technique, which integrates the DC-coupled resistance averaging and the AC-coupled capacitance averaging methods together. The operational principle follows. When the switch is on, the input signal is fed into the amplifier array and the offset at the output of the amplifiers is averaged by the averaging resistor ladder with a factor which is determined by the ratio of the output resistor value to the averaging resistor value. The remaining offset is stored in the input capacitors of the nest stage amplifiers. When the switch is on, the stored charges in the averaging capacitors are redistributed and the remaining offset error can be further averaged by a factor of two. Hence, the offset voltage signal can be effectively reduced by both the DC-coupled resistor averaging and the AC-coupled capacitor averaging networks. The edge effect of the resistor

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ladder can be suppressed by using a termination technique to reduce the nonlinearity. In addition, the termination technique also provides some headroom, with which a dummy amplifier may be added at the edge of the amplifier array to make the AC-coupled capacitance averaging at the edge as good as that occurring at the middle.

flash ADC design case is around R1/R2 1-1.5. Beyond the optimal R1/R2 ratio point, too large an R1/R2 ratio would only make it difficult for layout design matching. To further analyze the combined AC/DC-coupled offset averaging method, let the input referred offset of the amplifier be Voffset , then, the output referred offset of the first stage amplifiers is given by 1 Vout,1 = Voffset Goffset (5) 2 where the factor of 1/2 comes from the capacitance averaging and Goffset is the single-stage offset gain. Further, the total offset at the input of the second stage amplifiers can be calculated as
2 2 Vin,2 = [Vout,1 + Voffset ]2 1

(6)

Fig. 8

Enhanced averaging technique

2.2

Combined AC/DC-coupled averaging analysis

Efficiency of the new combined AC/DC-coupled offset averaging technique is evaluated by simulation first. Figure 9 shows the relationship between the averaging effect and the resistance ratio of output resistor to averaging resistor selected in design, i.e., R1/R2. It is obvious that the ratio between the offset gain and the signal gain for the new averaging network should be as small as possible to minimize the offset effects. The simulation result given in Fig. 9 readily shows that as the resistance ratio, R1/R2, increases, the offset-to-signal gain ratio continues to decrease to a minimum value, which results in maximum mismatch reduction induced by amplifier offset error. The saturation trend suggests that an optimal design point can be obtained for the maximum offset reduction, which in our sample

Hence the output offset of the second stage amplifiers will be 1 (7) Vout,1 = Vin,2 Goffset 2 Therefore, the total input referred offset can be calculated from the total output referred offset by V (8) Voffset,in = offset,out n Goffset In order to guarantee no missing code in flash ADC designs, the total input referred offset for an ADC should be less than LSB. In practical ADC designs, an adequate design margin should be considered to accommodate any possible noises and charge injection introduced errors.
2.3 Applying new averaging in ADC design

The new enhanced AC/DC-coupled offset averaging technique was utilized in designing a 4 bit 1 Gs/s flash ADC for verification. The 4 bit 1 Gs/s ADC was designed and implemented in a foundry 0.13 m CMOS technology. Figure 10 shows the micro photo for ADC with its performance specs listed in Table 1.

Conclusions

Fig. 9

Averaging effect versus R1/R2 ratio

This paper presents a new combined AC/DC-coupled offset averaging design technique to enhance offset-induced nonlinearity effects in flash ADC designs. Detail theoretical analysis and operation principle were explained how the DC-coupled resistance averaging technique and the AC-coupled capacitance averaging technique work together to enhance the offset

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References
[1] Kattmann K, Barrow J. A technique for reducing differential nonlinearity errors in flash A/D converters. In: Proc. IEEE International Solid-State Circuits Con., San Francisco, CA, USA, 1997: 170-171. [2] Wang Z-Y, Pan H, Chang C-M, et al. A 600 MSPS 8-bit folding ADC in 0.18m CMOS. In: Tech. Digest, IEEE Symp. VLSI Circuits, 2004: 424-427. [3] Mulder J, Ward C M, Lin C-H, et al. A 21-mW 8-b 125-MSample/s ADC in 0.09-mm2 0.13-m CMOS. IEEE Fig. 10 Die photo for the 4 bit 1 Gs/s flash ADC Flash ADC performance summary Values 4 bit 1 Gs/s 1 Vpp 0.6 LSB 1 LSB 30 mW No 0.13 m CMOS Journal of Solid State Circuits, 2004, 39(12): 2116-2125. [4] Scholtens P C S, Vertregt M. A 6-b 1.6-Gsample/s flash ADC in 0.18-m CMOS using averaging termination. IEEE Journal of Solid-State Circuits, 2002, 37(12): 15991609. [5] Sandner C, Clara M, Santner A, et al. A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-m digital CMOS. IEEE Journal of Solid-State Circuits, 2005, 40(7): 1499-1505. [6] Jiang X, Chang F. A1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging. IEEE Journal of Solid State Circuits, 2005, 40(2): 532-535. [7] Pan H. A 3.3-V 12-b 50-MS/s A/D converter in 0.6-m CMOS with 80-dB SFDR [Dissertation]. University of California, Los Angeles, USA, 1999. Table 1

Specs Resolution Conversion rate Input range DNL INL Power Missing code Technology

reduction efficiency. Termination and dummy amplifier techniques are integrated into the new combined AC/DC-coupled averaging method. The new offset averaging method was experimentally verified in designing a 4 bit 1 Gs/s flash ADC implemented in a commercial 0.13 m CMOS. The prototype ADC demonstrates the ability of this new averaging architecture.