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Virtuoso NeoCircuit performs automatic circuit sizing and optimization for custom digital, RF, and mixed-signal circuits. Integrated with the Cadence Virtuoso custom design platform, Virtuoso NeoCircuit employs the designers simulator of choice to size, bias, and verify circuits interactively with a manual starting point or automatically without a starting point.

Spec-driven environment


The Virtuoso custom design platform is a comprehensive system for fast, silicon-accurate design and is optimized to support meet-in-themiddle design methodologies such as advanced custom design. The Virtuoso platform includes the industrys only specification-driven environment, multi-mode simulation with common models and equations, vastly accelerated layout, advanced silicon analysis for 0.13 microns and below, and a full-chip, mixed-signal integration environment. The Virtuoso platform is available on the Cadence CDBA database and the industry-standard OpenAccess database. With the Virtuoso platform, design teams can quickly design silicon that is right and on time at process geometries from one micron to 90 nanometers and beyond.

Worlds leading foundries

Multi-mode simulation Process design kits

Accelerated layout OpenAccess universal data hub

Silicon Design Chain

Silicon analysis

Advanced device modeling

Full-chip integration

Direct link to manufacturing


Figure 1: Virtuoso custom design platform

Virtuoso NeoCircuit enables designers to automatically size, bias, and verify analog and RF circuits including LNAs, mixers, opamps, bandgaps, comparators, charge pumps, and VCO s while using the designers simulator of choice. These basic building blocks are used to construct filters, ADCs, PLLs, DACs, etc. Circuit topologies, constraints, testbenches, alternative sized circuits, and layouts are then archived as a library of reusable analog IP.

Unsized/partially sized schematic

Gain PM UGF THD Offset 60dB 60 deg 400M 0.01% 0.1mV

Voltage Temperature Process (vth, u etc.) Mismatch ...

Virtuoso NeoCircuit sizing and DFM engines

Virtuoso Analog Design Environment

Increases design productivity up to 10x Delivers a high-capacity, highperformance solution Allows complete custom constraint capture Uses a unique simulation-based sizing/biasing approach Offers direct support of manufacturing variations Enables IP creation, design reuse, and technology migration

Sized design
Figure 2: Design centering

Centered design

HIGH CAPACITY Virtuoso NeoCircuit supports hierarchical schematics with hundreds of devices. It handles dozens of performance goals and environmental/process corners. COMPLETE CUSTOM CONSTRAINT CAPTURE Using Virtuoso NeoCircuit, designers can capture design constraints interactively, archive them on the schematic, check them automatically, and enforce them during sizing. UNIQUE SIMULATION-BASED SIZING/BIASING APPROACH Designers can size circuit topologies using their circuit simulation environment with Virtuoso NeoCircuit. Each candidate sizing solution is qualified during the optimization process, and it sizes either from a starting point or from scratch.
Your topology Your specifications Simple constraints

Spectre, Eldo, HSpice, or your simulator

Sized circuit Green = specs are met

Explore design space

Size design

Define specifications

Define device relationships

Figure 3: Sizing flow

IP CREATION, DESIGN REUSE, AND TECHNOLOGY MIGRATION With Virtuoso NeoCircuit, designers can change constraints to resize them for a technology migration, new performance specification, or engineering change order (ECO). UNIQUE SUPPORT FOR DESIGN EXPLORATION Virtuoso NeoCircuit automatically generates multiple alternative circuit sizing solutions. It also provides a graphical exploration environment for evaluating tradeoffs and analyzing sensitivity. FASTMOS SIMULATOR SUPPORT AND EXTRACTOR SUPPORT Virtuoso NeoCircuit is integrated with Virtuoso UltraSim Full-chip Simulator and most third-party FastMOS simulators, enabling large mixedsignal blocks to be sized quickly and efficiently. Virtuoso NeoCircuit is also integrated with most standard extraction tools and can resize devices in the presence of RC parasitics to bring designs back into specification.

SYSTEM REQUIREMENTS Sun, HP, and Linux hardware with a minimum of 512Mb of memory PLATFORM/OS Sun Solaris HP-UX Linux INTERFACES Simulator support for HSpice, ADS, and Eldo THIRD-PARTY SUPPORT Support for most FastMOS simulators Support for most industry-standard extraction tools

Collaborative approach and design infrastructure virtual teaming Proven methodology and flow tuned to your design environment Design and EDA implementation expertise Product and flow training to fit your needs and preferred learning style Over 80 instructor-led courses certified instructors, real-world experience More than 25 Internet Learning Series (iLS) online courses Cadence customer support that keeps your design team productive Cadence applications engineers provide technical assistance SourceLink online support gives you access to software updates, technical documentation, and more 24 hours a day, 7 days a week


Customer-focused solutions that increase ROI, reduce risk, and achieve your design goals faster


Email us at info@cadence.com, or log on to www.cadence.com

2004 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, SourceLink, and Virtuoso are registered trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders. 5641 07/04