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®

Tales from the Cube

SEPT 4
Issue21/2005
Issue 18/2008
Pg 90
Oil prices, technology,
and the cost
www.edn.com of ignorance Pg 10
Transimpedance-
amplifier stability is key
Pg 24
Prying Eyes Pg 26

VOICE O F T HE ENGINEE R Design Ideas Pg 71

HANDCRAFTED
ANALOG GETS
AUTOMATED ASSIST
Page 40

SHEDDING LIGHT ON
EMBEDDED DEBUGGING
Page 29

USING FPGAs IN
CONSUMER ELECTRONICS
Page 49

OPTIMIZE MEMORY-
SYSTEM DESIGN FOR
MULTIMEDIA APPLICATIONS
Page 59
Enter xx at www.edn.com/info
innovation

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©2008 National Instruments Corporation. All rights reserved. National Instruments, NI, and ni.com are trademarks of National Instruments.
Other product and company names listed are trademarks or trade names of their respective companies. 2008-9267-151-101
contents
9.4.08
Using FPGAs in
consumer electronics

49
In cost-sensitive con-
sumer-electronics
products, customiza-
tion is a highly desirable feature
for differentiating your product
from competitors’ offerings. The
inclusion of FPGAs can be afford-
able, even in low-range and mid-
range products, but still allows
customization through some
unique features.
by Phuttachad Thiencharoenwong,
Handcrafted analog SingMai Electronics
gets automated assist
Optimize memory-
40
EDA tools address
simulation, verification, system design
and layout for mixed-
signal designs. for multimedia
by Rick Nelson, Editor-in-Chief applications

59
The convergence of
video and communi-
Shedding light on cations in inexpensive
embedded debugging unified-memory architectures has
made DRAM the most important

29
Embedded debugging
gets a lot of attention and the highest-performance
for being a schedule target in any system.
and resource hog, but there may by David Lautzenheiser
be more to it than just fixing bad and Agha Hussain, Silistix
software. by Robert Cravotta,
Technical Editor

DESIGNIDEAS
R2
71 Platinum-RTD-based circuit provides high performance with few components
R1 R1

ⳮ 72 Proportional-ac-power controller doles out whole cycles of ac line



78 Extend monolithic programmable-resistor-adjustment range with active negative resistance
R4
R0 R␪ R3 78 1-Wire network controls remote SPI peripherals

SEPTEMBER 4, 2008 | EDN 5


¥!CTEL#ORPORATION!LLRIGHTSRESERVED3PARTANAND#OOL2UNNERAREREGISTEREDTRADEMARKSOF8ILINX )NC#YCLONEAND-!8AREREGISTEREDTRADEMARKSOF!LTERA#ORPORATION

7(!4$/7%(!6%4/$/ $2!79/5!0)#452%
/NLY!CTELGETSYOUTHISCLOSETOZERO!NYOTHERCLAIMSOFLOWPOWERSUPERIORITYAREJUSTTHAT!CCORDINGTOTHEIR
OWNDATA !LTERAšAND8ILINXšUSEBETWEENANDTIMESTHEPOWEROF!CTEL)',//š&0'!S DEPENDINGON
DEVICEANDMODE7ANTSPECIFICS6ISITUSTOGETTHEWHOLEPICTURE INCLUDINGAVIDEOOFACTUALMEASUREMENTS

MOREPROOFANDPICTURESATACTELCOMPOWER
contents 9.4.08

pulse
15 Video, graphics module drives dual displays
Dilbert 16

18 Beagle Board opens embedded development

15 AMD updates Stream software-development kit 20 Integrated ORing controller and MOSFETs run
fast and cool for redundant supplies
16 Touch-panel controller targets media-device
interfaces 20 HDD (and SSD) capacities: up, up, and away

16 Module targets embedded-system design 22 Voices: Pentek’s Rodger Hosking: next-genera-


tion-radio architecture
18 Power-supervision IC measures regulator-input
current, differential-output voltage

22 83
26

D E PA R T M E N T S PRODUCT
& COLUMNS ROUNDUP
10 EDN.comment: Oil prices, technology, and the 83 Power Sources: Switcher ICs, dc/dc converters,
cost of ignorance dual-output converters, dual low-dropout regulators,
and pc-power-supply devices
24 Baker’s Best: Transimpedance-amplifier stability
is key 87 Integrated Circuits: SOCs, 500-mA buck regula-
tors, digital-media processors, and logic-gate
26 Prying Eyes: Prying apart a portable audio player
optocouplers
90 Tales from the Cube: The case of the stolen
88 Computers and Peripherals: 8-Gbyte storage
capacitor
devices, LCD monitors, handset-audio filtering
devices, Mac memory kits, and more
EDN ® (ISSN#0012-7515), (GST#123397457) is published biweekly, 26 times per year, by Reed Business Information, 8878 Barrons Blvd, Highlands Ranch, CO 80129-2345. Reed Business Information, a division of Reed
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a registered trademark of Reed Elsevier Properties Inc, used under license. A Reed Business Information Publication/Volume 53, Number 18 (Printed in USA).

SEPTEMBER 4, 2008 | EDN 7


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O N L I N E O N LY READERS’ CHOICE 90
Check out these Web-exclusive articles: A selection of recent articles receiving
85
High-voltage, low-noise converters: high traffic on www.edn.com.

Efficiency (%)
Jim Williams’ prototype pictures Photo-sensing circuits: The eyes 80
Longtime contributor Jim Williams, staff of the electronic world are watching 75
scientist at Linear Technology, went all out Baker’s Best: When exploiting the light VOUT = 3.3V
and built 10 prototype boards for a recent sensitivity of silicon, the challenge lies in 70
article on high-voltage, low-noise convert- determining how to convert the low-level VOUT = 5V
65
ers. Check out both the article and the currents from the photo sensor into a
boards here. useful electrical representation. 60
➔ www.edn.com/080904toc1 ➔ www.edn.com/article/CA6582850
0 1 2 3 4 5 6 7 8 9 10 11 12
IOUT (A)
600KHz
K switching frequency

Determining end-of-life, ESR, and MIT researchers use plant-energy-stor-


lifetime calculations for electrolytic age system for solar-storage innovation
capacitors at higher temperatures ➔ www.edn.com/article/CA6583673
➔ www.edn.com/article/CA6588368
Simple toggle circuits illustrate
ESR calculations for electrolytic low power-MOSFET leakage
capacitors at lower temperatures ➔ www.edn.com/article/CA6582853
SupIRBuck
uppIR
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c Advantages:
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Virtualization and multicore x86 CPUs • Integrates IR’s high performance
Intel launches USB 3.0 extensible ➔ www.edn.com/article/CA6584878 synchronous buck control ICs
host-controller-interface draft spec
and benchmark HEXFET® trench
➔ www.edn.com/article/CA6587566 Magnetic measurement tools
attract attention technology MOSFETs
ESL: the state of the industry ➔ www.edn.com/article/CA6578134 • 8-10% higher efficiency
and what’s next
compared to monolithic Power IC
➔ www.edn.com/article/CA6588565 Intel, Samsung, TI, Toshiba maintain
top spots in IC Insights semi ranking two-stage solution
➔ www.edn.com/article/CA6584172 • High density compared to
EDN PRODUCT FEED equivalent discrete solution
Our always-open buffet of new ICs and
THIS WEEK IN GEEK
components.
➔ www.edn.com/productfeed EDN’s Friday tech roundup, available in For more information
the Now Hear This blog.
call 1 800 981 8699 or visit us
➔ www.edn.com/nowhearthis
at www.irf.com/dcdc
EDN This
www.edn.com/
productfeed week
Product in
fEEd gEEk
S M T W T F S

THE POWER MANAGEMENT LEADER


EDN.COMMENT
,,
BY RON WILSON, EXECUTIVE EDITOR

creating an on-demand public-transit


network that would function at a frac-
tion of the fuel consumption and con-
gestion generation of the behemoths.
Again, there is no new technology
here, and adequately suitable vehicles
are currently languishing in automo-
tive-dealer inventories.
Oil prices, technology, Or consider where the demand for
all that sweet, light crude oil comes
and the cost of ignorance from. The most dramatic increase
isn’t from sport-utility vehicles or cor-
he world has just had a graphic demonstration of the work- porate jets. It’s from diesel genera-

T
ings of supply and demand in the oil industry. Supply of tors because, in much of the develop-
ing world, local demand for electric-
sweet, light crude became insufficient for the demand, and ity—partly created by our desire for
its price shot up. In response to the higher prices, demand cell phones and TV sets—is soaring.
for gasoline in the United States dropped, and the price In countries that lack generation and
shot back down again. In light of this dramatic performance, distribution infrastructure, only local
it is worth asking whether quick, technically feasible applications of diesel generators can meet that de-
mand. Hence, the demand for diesel
electronics could significantly reduce
demand in the short term.
Estimates show soars—driving refineries to capacity
and creating a shortage of sweet, light
We are looking for feasible and fast that a third of the crude oil. (There is no shortage or
solutions, so converting the entire fuels vehicles in price premium for high-sulfur crude,
Western world’s vehicle fleet to fuel by the way. Few refineries can pro-
cells is out. So is covering two South- urban areas con- duce diesel from it.) So what would be
western states with photovoltaic cells sume go to waste the impact on demand if we focused
or building a set of experimental but our photovoltaic and storage efforts
full-scale fusion reactors. Relative- because of unnec- and subsidies not on wealthy North
ly quick measures do exist, however, essary acceleration. Americans’ rooftops, but on develop-
and, unsurprisingly, they focus not on ing-world towns and villages?
fundamental changes in society but would be trivial in comparison with Many such opportunities exist to
on increasing efficiency. the savings and within the resources use a little understanding, a little tech-
One example dear to the hearts of of even state-level governments with- nology, and a little capital to make a
many commuters is traffic control. In out huge national subsidies. The only significant decrease in fuel consump-
much of North America and, from shortage is in the skill to install and tion. And, as noted, a small decrease
the little we have seen, industrializing operate the networks and the knowl- in consumption can make a big differ-
Asia, the entire notion that you can edge to recognize the problem. ence in global inflation pressure. But
enhance rather than impede the flow Public transportation presents a rest assured that these things will not
of traffic by properly regulating traffic similar example. Most municipalities happen. Inefficiency is one of the costs
lights is an as-yet-unmade discovery. in the world wear about their necks nature imposes as the price of public
The cost of this ignorance is horren- as a token of honor an ever-mov- ignorance of technology.EDN
dous. Estimates show that a third of ing, constantly belching necklace of
the fuels vehicles in urban areas con- huge diesel buses, with a ratio of aver- Contact me at ronald.wilson@reed
sume go to waste because of unneces- age payload weight to vehicle weight business.com.
sary acceleration, almost entirely after that would embarrass a Hummer own-
a traffic control or jam has slowed the er. Municipalities could inexpensive-
vehicle. Technologically simple com- ly replace most of these monstrosities + Go to www.edn.com/080904ed
puterized sensor and control networks with fuel-efficient small vans, direct- and click on Feedback Loop to post
and known algorithms could cut this ed by a network of GPS (global-posi- a comment on this column.
waste by a large factor. The amount of tion-system) sensors, traffic monitors, + More at www.edn.com/edncomment
necessary capital equipment and labor requester terminals, and computers,

10 EDN | SEPTEMBER 4, 2008


More Q. Less Cu
29

Copper
63.546

These tiny new air core inductors


have the highest Q and current handling
in the smallest footprint.
Coilcraft’s new SQ air core inductors have unmatched Q
factors: most are above 200 in the 1-2 GHz range! That’s 3
times higher than comparably sized 0805 chip coils.
And with their extremely low
DCR, they can handle 4 to 8 times
more current: up to 4.4 Arms.
SQ air core inductors are perfect
for your LC filter and RF impedance
matching applications. They come in
15 values ranging from 6 to 27.3 nH,
Q factors are 3X higher than all with 5% tolerance.
standard chip inductors
These coils
are significantly smaller than exist-
ing air core inductors. We reduced
the footprint by using close-wound
construction and keeping the leads
close to the body. The square shape
cuts the height to as low as 1.5 mm
and creates flat top and bottom sur-
faces for easy automated handling
and stable mounting.
See how the ultra-high Q and
The square shape and narrow footprint current handling of Coilcraft’s
reduce board space by 60-75% over new SQ air core inductors can
conventional air core inductors.
maximize the performance of
your next design. For complete specifications and free
evaluation samples, visit www.coilcraft.com/sq

RCOMoPLHIANST
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Power That Gives You The Best Of
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Switcher Efficiency Combined With LDO Noise And Transient Performance

The MIC38300 is a 3A step down converter and the first The Good Stuff:
device in a new generation of HELDOTM products providing the ◆ 2.2A Continuous operating current
benefits of LDOs with respect to ease of use, fast transient ◆ Input voltage range: 3.0V to 5.5V
performance, high PSRR and low noise while offering the ◆ Adjustable output voltage down to 1.0V
efficiency of a switching regulator. ◆ Output noise less than 5mV
◆ Ultra fast transient performance
As output voltages move lower, the output noise and transient ◆ Unique Switcher plus LDO architecture
response of a switching regulator become an increasing challenge ◆ Fully integrated MOSFET switches
for designers. By combining a switcher whose output is slaved to ◆ Micro-power shutdown
the input of a high performance LDO, high efficiency is achieved ◆ Easy upgrade from LDO as power dissipation becomes an issue
with a clean low-noise output. ◆ Thermal shutdown and current limit protection
For more information, contact your local Micrel sales representa- ◆ 4mm × 6mm × 0.9mm MLF ® package
tive or visit us at: www.micrel.com/ad/mic38300.

© 2008 Micrel, Inc. All rights reserved. Micrel is a registered trademark of Micrel, Inc.
HELDO is a trademark of Micrel, Inc. MLF is a registered trademark of Amkor Technology.
www.micrel.com
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respective companies. 2008-9806-101-D
ELECTRONIC COMPONENTS custom SoCs | NAND memory storage solutions | displays | discrete devices | imaging and multimedia ICs | microcontrollers

“Sweating the details” redefined by Toshiba.


Toshiba sweats every detail in order to deliver expert, responsive technical
service/support for its electronic components. The Toshiba design centers
have a team of engineers dedicated to power analysis to ensure optimum
power management. Toshiba Virtual Prototyping—our exclusive system
for chip/package/system co-design for Custom SoCs—delivers a power-
optimized model usually in less than eight weeks. And we employ advanced
low-power design techniques like Multi-Vth, Clock Gating
and much more. This commitment to delivering unmatched
technical expertise is our formula for customer success.

Which equation below is the most


accurate estimate for power consumed
by flip flops on a chip? Use the legend
at transform.toshiba.com to solve the
equation and win a hoody sweat shirt (while supplies last).

Leila Ziai,
Staff Design Engineer,
Toshiba America Electronic
Components, Inc.

©2008 Toshiba America Electronic Components, Inc. All rights reserved.


pulse
EDITED BY FRAN GRANVILLE

INNOVATIONS & INNOVATORS

Video, graphics module drives dual displays FEEDBACK LOOP


“A young

W
ith advanced-sensor-fusion, image-
manipulation, and tactical-moving- graduate I once
map applications in mind, Aitech worked with told
Defense Systems recently introduced the me he got
M590 graphics and video PMC (peripheral-
component-interconnect-mezzanine-card)
into engineering
module that simultaneously outputs informa- for one reason—
tion from two independent data streams to to learn a bit
two analog or digital displays. The new M590 about engineer-
supports 2- or 3-D-video displays plus image Aitech’s new PMC drives dual 2- or 3-D-video ing so that he
capture with overlay and underlay features to displays from independent data streams at
resolutions as high as 1536⫻2048 pixels.
could go back to
provide man-machine interfaces with resolu-
tions as high as 1536⫻2048 pixels at 30- to school
200-Hz refresh rates and as many as 32 bits the M590 provides video overlay and underlay to get a law
per pixel. functions that generate images, superimpose degree and get
An AMD ATI (www.amd.com) M9 graph- an input from one of the various video formats, rich by suing big
ics processor with an on-chip 64-Mbyte and drive the result to a monitor. The module’s corporations over
frame-buffer array and dual RAMDAC (ran- software package supports all onboard capa-
dom-access-memory-digital-to-analog-con- bilities and features OpenGL drivers for both
engineering
verter) units power the M590, which performs VxWorks and Integrity real-time operating sys- patents.”
—Reader and frequent EDN
high-speed 2-D-line, 3-D-polygon, and tex- tems. The M590 is available in commercial-,
contributor Glen Chenier, in
ture acceleration. The module also supports rugged-, and military-temperature ranges and
EDN ’s Feedback Loop, at www.
multiple video-input and -output formats, in either conduction- or air-cooled versions. edn.com/article/CA6578140.
including NTSC (National Television System The price for an M590 starts at $3440 (OEM Add your comments.
Committee) and PAL (phase-alternating line) quantities).—by Warren Webb
for both interlaced and noninterlaced moni- 컄Aitech Defense Systems Inc, www.
tors. For advanced video-display applications, rugged.com.

AMD updates Stream software-development kit


To help increase the ease and efficiency of software development DirectX 11 builds on the performance of DirectX 10.1 for 3-D-
using its Stream-processing approach, microprocessor challenger graphics rendering and gaming control and includes new technol-
AMD (Advanced Micro Devices) recently announced an exten- ogies to ease the creation of general-purpose graphics-process-
sive set of upgrades for future versions of the Stream software- ing-accelerated applications that can run on any Windows Vista-
development kit. AMD intends that these upgrades will reduce powered platform. AMD is supporting efforts to develop OpenCL
the time and effort required to produce GPU (graphics-process- as an open standard and plans to evolve the Stream software-
ing-unit)-accelerated applications that run on multiple platforms, development kit to comply with OpenCL. The company is continu-
with expanding support for industry-standard APIs (application- ing to give developers the option of creating and using their own
programming interfaces) and enhanced support for C/C⫹⫹. The programming languages and high-level tools.
updates will add full support for DirectX 11, the next-generation —by Ann Steffora Mutschler
suite of advanced APIs from Microsoft (www.microsoft.com). 컄Advanced Micro Devices Inc, www.amd.com.

SEPTEMBER 4, 2008 | EDN 15


pulse

09.04.08
Touch-panel controller targets MODULE TARGETS
EMBEDDED-
media-device interfaces SYSTEM DESIGN
Building on its popular

A
tmel, in the form of function, eliminating the need
its recently acquired for an external LED controller.
The 2160 FPGA-based PXI (PCI ex-
tensions for instrumenta-
subsidiary, Quantum Atmel designed the device claims high tion), PC, and Compact-
Research Group, has intro- for use as a multimedia-HMI immunity to RIO (reconfigurable-in-
duced a touch controller that (human-machine-interface) put/output) platforms,
combines a slider control with controller in mobile phones and
EMI. National Instruments has
buttons, an integrated LED consumer electronics, such as announced a new line of
controller, and GPIO (general- personal media players. It oper- suppression) intelligently sup- single-board RIO modules
purpose-input/output) func- ates from 1.8 to 5.5V, and you presses signals from nearby that offers a lower-cost,
tions. The AT42QT2160, part can also use it in applications keys so that only the keys that integrated-hardware op-
of the company’s new QTouch such as digital still cameras, a user intends to touch register tion for embedded con-
series, uses charge-transfer PDAs (personal digital assis- a touch. trol and data-acquisition
technology to control as many tants), and handheld gaming The AT42QT2160 has three applications. The RIO-
as 16 touch keys with a slider devices. Like previous chips GPIOs with PWM capability and 96xx devices combine a
that you can configure to use using the charge-transfer tech- eight shared-output ports that real-time embedded pro-
two to eight of the touch-key nology, the 2160 claims high provide additional standard out- cessor, a reconfigurable
channels. If you need an ex- immunity to EMI (electromag- puts for the host without adding FPGA, and analog and
tra-long slider control, you can netic interference) through cost or using an extra I/O-ex- digital I/O on an 8.2⫻5.6-
add interpolation between spread-spectrum modulation pansion device. You configure in. PCB (printed-circuit
points with a resistive-touch- and filtering algorithms, cali- the device with an I2C (inter-in- board). Designers can
sensor element. bration of the device over its tegrated-circuit) interface. You use the company’s Lab-
The chip can also control as lifetime, and designer-defined might design touch-button- View software to config-
many as 11 LEDs through a sensitivity thresholds for indi- sensor electrodes of any arbi- ure the RIO hardware and
host-controlled PWM-output vidual keys. AKS (adjacent-key trary size greater than 6⫻6 mm the application’s embed-
and of arbitrary shape, as cop- ded firmware.
per pads on the PCB (printed- The modules feature
circuit board) or a flexible cir- a 266- or 400-MHz Free-
cuit. The chip senses touches scale (www.freescale.
to those pads through glass or com) MPC5200 proces-
plastic as thick as 2.5 mm. sor, the Wind River (www.
Samples of the AT42QT- windriver.com) VxWorks
2160 are available now in a real-time operating sys-
28-pin, 4⫻4-mm QFN pack- tem, and a Xilinx (www.
age; it sells for 98 cents xilinx.com) Spartan-3
(10,000). An evaluation board, FPGA. The onboard ana-
which comes with an I2C-to- log and digital I/O con-
USB converter to connect to a nects to the FPGA to pro-
PC, costs $82.50. vide low-level customiza-
Atmel’s QTouch controller integrates enough functions to control —by Graham Prophet tion of timing- and I/O-
a complete media device. 컄Atmel, www.atmel.com. signal processing. You
can expand the I/O ca-
pabilities using three ex-
DILBERT By Scott Adams
pansion slots for custom
hardware or any C-Series
I/O module. Prices for
the devices start at $1000
(100 or more). Watch a
demonstration video at
www.ni.com/singleboard.
—by Warren Webb
왘National Instruments,
www.ni.com.

16 EDN | SEPTEMBER 4, 2008


© Agilent Technologies, Inc. 2008

More measurements. More data. Less cost.


With up to 560 channels of data logging at a maximum scan rate of 1000 channels/sec,
an internal 6 ½ digit DMM with 22-bit resolution, and 0.03% accuracy, it’s no mystery why
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34980A are both at home with either data acquisition or functional test, with a broad
selection of plug-in modules.

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pulse
in nonvolatile memory with-
Power-supervision IC measures regulator-input in the IC. All family members
current, differential-output voltage have two comparators for de-
tecting levels or providing win-
which is accurate to ⫾1%; cur-

S
ummit Microelectronics’ commands on two dedicated dow comparisons, and they tar-
new SMM151 power- rent-sensing accuracy is ⫾2%. pins or the I2C bus. get applications in computing
supervision IC allows The part operates from 2.7 The IC allows users to pro- and datacom equipment, serv-
digital control and monitoring to 5.5V of power and has an gram limits for glitch-filter du- ers, wireless routers, and other
of any voltage regulator. The I2C (inter-integrated-circuit) ration, margin delays, and re- high-reliability systems.
device monitors input current interface that allows system sponse to fault conditions. A The SMM151EV evaluation
to the target regulator so there monitoring in real time with pa- sister part, the SMM152, also board works through a USB
is no added impedance to the rameters that you can change has four general-purpose I/O port with Summit’s Windows-
output rail. A differential pair using the I2C bus. The unit pro- pins. Developers can program based GUI (graphical user in-
that can accept 15V inputs vides fault- and ready-status the power-on state of these terface), which allows design-
performs the voltage sensing, outputs and accepts margin pins and store that information ers to set up the operating
parameters and then program
4 TO 15V
RS them into nonvolatile memory.
2.7 TO 5.5V
Once designers define the de-
vice’s functions, they can ex-
CAPC VDD GND
tract a hex file from the evalu-
VDD_CAP
CSⳮ COMP1
ation board that allows Summit
V1 to provide the part in volume
CS⫹ quantities.
MARGIN
The device operates in a
MUP COMP2
COMMANDS
MDN
0 to 70 or a ⫺40 to ⫹85⬚C
VREF
STATUS FAULT# temperature range and comes
OUTPUTS VIN
READY SMM151 in a 5⫻5-mm, 28-pad QFN
I2C SDA SMM152 VOUT⫹
package. The SMM151 and
INTERFACE SCL TRIM SEN⫹
TRIM SMM152 sell for $3.49 and
A0-A2
WP CAPM⫹ VOUTⳮ
$3.79 (1000), respectively.
(GPIO0) SENⳮ Samples and the SMM151EV
(GPIO1) CAPMⳮ
DC/DC CONVERTER
evaluation modules are avail-
(GPIO2) VM⫹ able, and volume production
(GPIO3) VMⳮ has begun.—by Paul Rako
컄Summit Microelec-
The SMM151 power-supervisor IC provides voltage and current measurement as well as margining tronics, www.summitmicro.
and supervisory functions. com/SMM151.
EDNBLOG

EMBEDDED WEBBLOG

Beagle Board opens embedded development system specifically configured


OFFERING DESIGNERS and introduced OMAP35x 2-D- and 3-D-graphics for the Beagle Board.
hobbyists a low-cost starting processors based on the acceleration capabilities A 132-pg hardware-refer-
point for device development, ARM Cortex-A8 core. plus a DSP optimized for ence manual is available for
Digi-Key, Texas Instruments, The design reduces multimedia processing. download at the Beagle-
and a group of volunteers cost and power require- Further simplifying de- Board.org Web site and pro-
have joined forces to cre- ments by eliminating most velopment, the board is com- vides complete module com-
ate an open, single-board- onboard peripherals, except pletely powered by the on- ponent descriptions, sche-
computer design that can be those provided by the pro- board USB interface used matics, and board-manufac-
adapted to a multitude of em- cessor, and incorporating for downloading the software turing documentation.
bedded projects. The module, standard expansion buses, from a laptop or desktop com- —by Warren Webb
dubbed the Beagle Board, is like high-speed USB 2.0 and puter. The open-source-soft- 왘www.edn.com/webblog.
a low-power, fanless design SDIO for application-specific ware-development communi- 왘For the full post, go to www.
incorporating TI’s recently I/O. The processor contains ty provides a Linux operating edn.com/080904b1.

18 EDN | SEPTEMBER 4, 2008


pulse
dundant-power architectures
Integrated ORing controller and MOSFETs and systems requiring opera-
run fast and cool for redundant supplies tion during input-voltage tran-
sients as high as 100V for 100
msec; and the high-speed, ac-

I
n their quest for near-100% voltages of 5V or lower; the
uptime, designers of high- 15V, 15A PI2123 suits ap- tive-ORing P12002 controller
availability-system applica- plications with bus voltages IC has a load-disconnect fea-
tions, such as telecom and of 9.6V or lower; and the 30V, ture that functions like that of
datacom servers, employ re- 12A PI2125 suits applications the PI2122 but works with in-
dundant-power systems: If with bus voltages of 12V. The dustry-standard, back-to-back
one power supply fails, a re- typical on-state resistances N-channel MOSFETs.
dundant supply can pick up the for the three parts are 1.5, 3, Picor’s Cool-ORing family of The PI2121, PI2123, and
load. Redundant- and backup- and 5.5 m⍀, respectively. Each devices integrates high-speed PI2125 come in 17-pin, 5⫻
ORing-MOSFET controllers
power supplies enter the load part can also work in parallel 7⫻2-mm-high, thermally en-
with low-on-state-resistance
along with ORing MOSFETs, to address higher current re- MOSFETs that achieve a typi- hanced LGA packages and sell
which ideally should have a quirements through a mas- cal dynamic response of 160 for $1.98 (10,000). The dis-
minimal on-state resistance ter/slave feature. The devices nsec and a typical on-state crete Cool-ORing controllers
and fast dynamic response to detect normal-forward, exces- resistance as low as 1.5 m⍀. are available in 3⫻3-mm, 10-
power source failures. sive-forward, light-load, and lead TDFN packages and sell
Picor’s Cool-ORing fam- reverse-current flow through thresholds using external re- for 84 cents for the PI2001 and
ily, comprising the PI2121, their internal MOSFETs, and sistor dividers. PI2003 and 92 cents (10,000)
PI2123, and PI2125 devices, they report fault conditions The family also includes dis- for the PI2002. An eight-lead
integrates high-speed ORing- through an active low-fault- crete versions of the ORing SOIC-package option costs
MOSFET controllers with low- flag output. A temperature- controllers. The high-speed, 76 cents for the PI2001 and
on-state-resistance MOSFETs sensing function indicates active-ORing PI2001 control- PI2003 and 83 cents for the
that typically achieve a dynam- a fault if the maximum junc- ler targets use with industry- PI2002 (10,000).
ic response within 160 nsec. tion temperature exceeds standard single or paralleled —by Margery Conner
The 8V, 24A PI2121 targets 160⬚C. You can program the MOSFETs; the PI2003 con- 컄Picor, www.vicorpower.com/
use in applications with bus undervoltage and overvoltage troller suits use in ⫺48V, re- picorpower.
EDNBLOG

BRIAN’S BRAIN

HDD (and SSD) capacities: up, up, and away tive? Although SSDs lag their
HDD counterparts on both
IT SEEMS LIKE just yester- Samsung’s products are absolute capacity and cost/
day that I was first writing to finally shipping in volume (as
Hitachi’s gigabyte metrics, suppliers
you about the world’s first 1- well that 1-Tbyte drives have accomplish- continue striving to at least
Tbyte, 3.5-in. HDD (hard-disk dipped below $150!). ment didn’t maintain pace with the rotat-
drive). Hitachi’s accom- Recent announce- ing-storage mainstay. Witness,
plishment didn’t remain ments show that ven-
remain sole- for example, Samsung’s 128-
sole-sourced long, of dors’ competitive juices sourced long, Gbyte SSD announcement.
course, given the hyper- have by no means of course. Samsung accomplishes this
competitiveness of the abated, even in the 2.5-in.-form-factor feat by
HDD industry. Seagate slightest. On July 9, means of MLC (multilevel-
launched a four-platter (250- Hitachi finally got its 1-Tbyte bit-packing peak for PMR cell, also known as 2-bit-per-
Gbyte/platter) configuration drive down to a three-platter (perpendicular-magnetic- cell) NAND-flash memory,
in June 2007, along with a configuration, the 7200-rpm recording) technology. That which roughly doubles the
Samsung paper launch of a Deskstar 7K1000.B. One same generation of magnetic amount of storage capacity
three-platter (333-Gbyte/ day later, Samsung released recording translates to 0.5- achievable for a given amount
platter) configuration in that the world’s first 1.5-Tbyte Gbyte, 5400- and 7200-rpm, of silicon area on a given pro-
same time frame. Western HDD, high-end member of 2.5-in. HDDs, which won’t cess lithography.
Digital waited until late July the 7200.11 product family, appear until some time in the —by Brian Dipert
2007 to unveil its own four- which was scheduled to enter fourth quarter. 왘www.edn.com/briansbrain.
platter configuration, and production in August. At 375 And what about the SSD 왘For the full post, go to www.
recent data suggests that Gbytes/platter, it hits a new (solid-state-drive) alterna- edn.com/080904b2.

20 EDN | SEPTEMBER 4, 2008


Analog ICs make the
HD experience what it is meant to be.

For HD audio, video, and interconnectivity that excites


Our newest Advantiv innovations and delights, put ADI’s Advantiv portfolio into action

Audio Processor for Advanced TV: ADAV4622 Crystal clear video. Rich, true-to-life sound. Deep color quality. And superior
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plug ’n play functionality. Those are just a few of the joys of using the latest
standards; simplifies designs for shorter time to market.
HDTVs, DVD players, DVRs, AVRs, camcorders, and set-top boxes that are
Class-D Stereo Power Stage: ADAU1513
Complete audio amplifier section; pop-and-click-free audio; built with Analog Devices’ technology inside. In virtually every aspect of
promotes seamless interconnectivity. HD delivery, designers who select from the Advantiv portfolio are benefiting
Video Decoder with 3D Comb Filter: ADV7802 from ADI’s audio and video signal processing expertise.
High quality images from composite input; vivid color;
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Low Power HDMI Transmitter with CEC: ADV7520NK to meet the demands of the toughest applications. Wherever user
Longer battery life; lighter and smaller designs; enables
experience defines the design, Analog Devices defines the possibilities.
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HDMI/DVI 1:1 Buffer: AD8195 To experience what Analog Devices can do for your design,
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www.analog.com/Advantiv-1
pulse
the complexity of the prod-
ucts and the need to provide
higher-level tools to our cus-
tomers. Our most capable FP-
GA designers started as hard-
VOICES ware engineers with a flair for
algorithms, DSP, and software
Pentek’s Rodger Hosking: tools. More than ever, techni-
cal writers need to be capable
next-generation-radio engineers with specific exper-
tise in the area of technology
architect ing power dissipation with new
silicon techniques.
they are documenting but not
so close to it that they over-

R
odger Hosking is vice president and co-founder of Pen-
These trends will support look the need to explain some
tek Inc, where he is responsible for new-product defi-
small, complete, system-level of the basics in our manuals.
nition, technology development, and strategic alliances.
solutions close to the antennas Customer-support engineers
With more than 30 years’ experience in the electronics indus-
and sensors. They will include need a special blend of tech-
try, he has authored hundreds of articles about software radio
acquisition, generation, upcon- nical expertise, patience, and
and digital-signal processing. He designed the first commercial
version and downconversion, empathy to help customers
direct-digital-frequency synthesizer and holds patents in fre-
modulation and demodulation, become successful, even if it
quency synthesis and FFT (fast-Fourier-transform)-spectrum-
analysis and detection, buff- is their first exposure to this
analysis techniques. Hosking has a bachelor’s degree in phys-
ering and forwarding, and lo- complex technology.
ics from Allegheny College (Meadville, PA) and both bachelor’s
cal supervisory and decision- Retaining engineers is dif-
and master’s degrees in electrical engineering from Columbia
making functions. High-speed ficult because each one is
University (New York).
gigabit links will connect these uniquely qualified and moti-
What are the technical chal- All of these factors lead to autonomous subsystems to a vated, but tasking them with
lenges that you face in high- longer development cycles central facility through dedicat- several areas of engineering
performance-data-acquisi- while the rate of new-technol- ed paths or over the Internet. responsibilities often proves to
tion- and software-radio- ogy-device introductions is in- be a successful strategy.
product development? creasing. This [combination of As a COTS-board manufac-
Complexity of the sili- factors] leads to shorter life turer, how do you prevent What motivated you to se-
A con devices, coupled cycles for each product, even the interoperability issues lect electrical engineering
with high component density though development costs are when designing for today’s and the high-tech industry
and power dissipation, pushes higher. rival fabric-interconnection as a profession?
the limits of PCB [printed-cir- standards? As a very small child, I
cuit-board] design, mechanical As you look ahead for the The most successful A was always fascinated
packaging, and thermal-man- next few years, which tech- A tactic has been to fol- with anything that had to do
agement technology. Gigabit nologies and applications low the standards as closely as with electricity. Later on, I be-
serial links impose strict layout present the most interest- possible and declare each lev- came an avid electronics hob-
rules for matching lengths and ing opportunities? el of compliance your product byist, building hundreds of my
impedances of differential-sig- FPGAs have created supports. A series of simple ex- own projects inspired by mag-
nal pairs. Testing and validation A a major shift in COTS- ample programs demonstrat- azine articles and books. For
of new designs requires not product offerings for data ac- ing operation of the basic mes- me, a career in electronics was
only hardware expertise, but al- quisition and software radio saging types can be extremely a no-brainer.
so a significant software effort by offering critical functions, useful for interfacing with prod-
because of the complexity and including fast and flexible I/O ucts from other vendors. What activities do you pur-
inaccessibility of hardware test resources, DSP engines, con- sue for relaxation outside
points. Drivers and software li- figurable logic and RAM, giga- Which engineering talents your high-tech work envi-
braries offered by the COTS bit serial interfaces, and built- are most important to Pen- ronment?
[commercial-off-the-shelf] ven- in microcontrollers. All of these tek, and how do you find and Outside work, I spend my
dors to support customer-de- features will become more retain them? A time running, rollerblad-
velopment efforts need to sup- powerful in next-generation Fifteen years ago, we ing, ballroom dancing, watching
port multiple operating-system FPGAs. Monolithic ADC and A had one software en- old movies, and listening to mu-
environments and require more DAC technology will contin- gineer for every three hard- sic from the ’30s and ’40s.
testing, qualification, and docu- ue to advance both resolution ware engineers. That ratio is —Interview conducted and
mentation than ever before. and sampling rates while tam- now exactly reversed due to edited by Warren Webb

22 EDN | SEPTEMBER 4, 2008


S P E C I A L A D V E R T I S I N G S E C T I O N

R A Q ’ s

Rarely Asked Questions


Lock Down That Noise — Don’t Let It Escape
Q. How can I prevent switching- Contributing Writer
mode power supply noise from Contributing Writer
James Bryant has been
devastating my circuit performance? John Ardizzoni is an
a European Applica-
Application Engineer
A. With great difficulty — but it can tions Manager with
be done. at Analog Devices in
Analog Devices since
the High Speed Ampli-
Switching-mode power supplies are 1982. He holds a degree
fier Group. John has
inherently the noisiest circuits imaginable. in Physics and Philoso-
been with Analog
A large current from the supply is being phy from the Univer-
turned on and off at high frequency with Devices for 4 years, he
sity of Leeds. He is also
very fast dI/dt. There are inevitably large received his BSEE from
C.Eng., Eur.Eng., MIEE,
fast voltage and current transients. than the basic 1/2SfC formula predicts; Merrimack College in
and if it shares its ground path with other and an FBIS. In addi-
1988 and has over 27
The only way to prevent interference circuitry the noise in the common ground tion to his passion for
years experience in the
to sensitive circuitry in the system is to impedance will be disruptive. engineering, James is
keep the transients within the converter. electronics industry.
a radio ham and holds
We cannot stop switching large currents Add to these effects the less important,
the call sign G4CLF.
inside it, but we can, and must, prevent but still damaging, consequences of
the transient currents and voltages from external currents induced by fast-chang-
escaping. Start by grounding all the ter- ing magnetic and electrostatic fields, and Have a question
minals of the converter at AC. even electromagnetic radiation, from Have a question
within the converter, and it is obvious that involving a
involving a perplexing
Capacitors block DC but have low imped- preventing converter noise is not simply
or unusual analogor
perplexing
ance at AC, so they should be ideal for a matter of placing a couple of random
this purpose. In theory, if we place a large capacitors on its input and output. problem? Submit your
capacitor between the converter input unusual
question to: analog
and its ground, the input will keep the Silencing a DC-DC converter requires sys-
raq@reedbusiness.com
problem? Submit
capacitor charged and the transient cur- tematically finding all the possible paths
rents will flow in the capacitor and not by which noise can escape from it, and
ensuring that they are all locked down. your question to:
from the power source. A similar output
The linked article discusses how this may For Analog Devices’
capacitor absorbs transients and sources
be done. Technical Support,
steady DC.
Call 800-AnalogD
raq@reedbusiness.com
Unfortunately when we actually build such Of course before we start we must
a system it is common to find much more choose or design the converter itself to For Analog Devices’
noise than we can tolerate in the input have minimal external noise. This is a Technical Support,
and output circuits - what can be wrong? separate issue which may be discussed in Call 800-AnalogD
a future RAQ.
If the capacitor is placed some distance
from the converter, the impedance, resis-
SPONSORED BY
tive and inductive, of its connection to To Learn More About SPONSORED BY
the converter will be large enough to pre-
Power Supply Noise
vent it from working properly; if it is cho-
sen badly it will have higher impedance Go to: http://rbi.ims.ca/5721-101

D E S I G N N E W S 0 0 . 0 0 . 0 0 [ w w w. d e s i g n n e w s . c o m ] 1
BAKER’S BEST
,,
BY BONNIE BAKER

RF CF

PHOTODIODE

ISC CRF
CPD
RPD
DPD
CCM
CDIFF AOL(j) VOU

CCM

NOTES:

Transimpedance-amplifier DPD = IDEAL PHOTODIODE.


ISC = CURRENT GENERATED BY LIGHT.
CPD = DEVICE CAPACITANCE.

stability is key RPD = DEVICE PARALLEL RESISTANCE.


CF = FEEDBACK CAPACITOR.
RF = FEEDBACK RESISTOR.
CRF = FEEDBACK-RESISTOR PARASITIC CAPACITANCE.
variety of precision applications sense light and convert

A
CCM = COMMON-MODE-AMPLIFIER CAPACITANCE.
CDIFF = DIFFERENTIAL-AMPLIFIER CAPACITANCE.
that information into a useful digital word. At the sys- AOL(j)= AMPLIFIER OPEN-LOOP GAIN.

tem’s front end, a preamplifier converts the photodiode’s


current-output signal to a usable voltage level. Figure 1 Figure 1 This transimpedance photo-
sensing circuit comprises a photodiode,
shows the front-end circuit of this system, which com- an operational amplifier, and a feedback
prises a photodiode, an operational amplifier, and a feed- network.
back network. The transfer function of this system is:
I SC × R F the photodiode’s parasitics and the circuit will oscillate or ring with a
VOUT = , operational amplifier’s input capaci- step-function input.
1 + 1 /(A OL (jω) × β)
tance, as well as RF, CRF, and CF in the One way to correct circuit insta-
where AOL(j) is the open-loop amplifier’s feedback loop. bility is to add a feedback capaci-
gain of the amplifier over frequen- Figure 2 shows the frequency re- tor, CF, or to change the amplifier to
cy;  is the system-feedback factor, sponse of the 1/ curve and the amp- have a different frequency response
equaling 1/(1ZIN/ZF); ZIN is the dis- lifier’s open-loop-gain response: fP1/ or different input capacitance. A
tributed input impedance, equaling (2(RPD||RF)(CPDCCMCDIFFCF conservative calculation that allows
RPD||j(CPDCCMCDIFF); and ZF CRF)), and fZ1/(2(RF)(CFCRF)). variation in amplifier bandwidth, in-
is the distributed feedback imped- The AOL(j) curve intersects the 1/ put capacitance, and feedback-resistor
ance, equaling RF||j(CRFCF). curve at an interesting point. The value places the system’s pole of 1/
A good tool for determining sta- closure rate between the two curves at half the frequency where the two
bility is a Bode plot. The appropriate suggests the system’s phase margin curves intersect:
Bode plot for this design includes the and, in turn, predicts the stability. ⎡ (CPD +C CM +C DIFF ) ⎤
amplifier’s open-loop gain and the 1/ For instance, the closure rate of the C F = ⎢2 × ⎥ⳮC RF ,
⎢⎣ 2πR F fGBW ⎥⎦
curve. System elements determining two curves is 20 dB/decade. Here,
the noise-gain frequency response are the amplifier contributes an approxi- where fGBW is the gain-bandwidth prod-
mately 90 phase shift, uct of the amplifier. In this design, the
and the feedback factor system’s phase margin is 65, and the
A
OL
20 dB/DECADE contributes an approxi- step function’s overshoot is 5%.EDN
mately 0 phase shift.
20-dB/DECADE
GAIN INTERCEPT By adding the 1/ phase R E FE R E NCE
(dB) f P shift from the AOL(j) 1 Baker, Bonnie, “The eyes of the
GAIN=1(C C C
D CM )/C .
DIFFphase shift, the system’s
F electronic world are watching,” EDN,
phase shift is 90, and Aug 7, 2008, pg 24, www.edn.com/
GAIN=1R /R .
F D its margin is 90, result- article/CA6582850.
1/ ing in a stable system. If
f FREQUENCY (Hz)
Z the closure rate of these Bonnie Baker is a senior applications engi-
Figure 2 The closure rate between the open-loop-gain two curves is 40 dB/de- neer at Texas Instruments and author of
frequency response and the feedback-gain response cade, indicating a phase A Baker’s Dozen: Real Analog Solu-
is 20 dB/decade. shift of 180 and a tions for Digital Designers. You can
phase margin of 0, the reach her at bonnie@ti.com.

24 EDN | SEPTEMBER 4, 2008


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PRYING EYES BRIAN DIPERT • SENIOR TECHNICAL EDITOR PRY FURTHER AT EDN.COM
+ Go to www.edn.com/080904pry
for an expanded version of this
article.

Prying apart a portable audio player


ree after $65 rebate with free shipping. That’s the deal

F that routed a refurbished Sandisk Sansa M250 from


Newegg to my front door last summer. I suspected it
would make a fine Prying Eyes patient, and, as it turns out, I
Above the SDRAM and an
intermediary piece of cush-
was right. Let’s see what’s inside, shall we? ioning foam are two 1-Gbyte
Samsung K9K8G08U0M
NAND-flash-memory devices
The system’s “brains” consist of an The Sansa M250 embeds on a double-sided daughter-
ARM9-based and USB2-support-inclusive a single battery-backed, 16- card. This modular arrange-
Telechips TCC770. The Sansa M250’s Mbit Elite Semiconductor ment gives Sandisk the flex-
built-in microphone for voice recording and M12S16161A SDRAM, ibility to leverage a common
subsequent playback likely harnesses the supplementing the 64 primary-PCB design across
CPU’s ADPCM (adaptive-differential-pulse- kbytes of SRAM within the multiple Sansa M200 family
code-modulation)-audio-codec support. Telechips TCC770. Among proliferations—having 512-
other functions, the SDRAM Mbyte, 1-Gbyte, and 4-Gbyte
probably acts as a “shadow” capacities—and to source
for the direct execution of NAND-flash memories in mul-
Texas Instruments’ TLV320AIC- system code that the NAND- tiple IC-density, architecture,
23B two-channel codec—that is, flash memory stores. and supplier variations.
ADC and DAC—with headphone
amplifier is another notable IC in
this design; however, the player
doesn’t fully harness the chip’s
24-bit maximum per-channel
sample size and 96-kHz peak
sample rate.

The Sansa M250 uses the Philips


(now NXP Semiconductors)
TEA5767HN FM radio IC for play-
back only—that is, the Sandisk unit
offers no support for live recording
and later listening. The lack of a
discrete antenna embedded within
the Sansa M250’s plastic case
probably indicates the use of the
headphone wire for this function.

The Telechips TCC770 advertises


limited-codec image-decoding sup-
port: JPEG pictures and MPEG-4
Simple Profile video clips. The
Sansa M250 collateral makes no
mention of image-file capabilities;
then again, the unit’s 128⫻64-pixel
monochrome LCD wouldn’t really
do them justice, anyway.

26 EDN | SEPTEMBER 4, 2008


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SHEDDING LIGHT ON
EMBEDDED
DEBUGGING
EMBEDDED DEBUGGING GETS A LOT OF ATTENTION FOR BEING A SCHEDULE AND
RESOURCE HOG, BUT THERE MAY BE MORE TO IT THAN JUST FIXING BAD SOFTWARE.

or each year of Embedded Systems Design’s annu- bugging tools are not merely extensions

F
al market survey of embedded-system developers, of programming tools that help develop-
ers correct mistakes or incorrect coding.
the single most requested area of improvement for There is a less obvious, almost implic-
design activities is debugging tools (Reference 1). it aspect of engineering—that designers
The percentage of respondents making this request must not only design systems that per-
has remained steady at around 32% throughout the form some desirable function, but also
three years of the survey. In contrast, the percent- eliminate or mitigate undesirable behav-
iors that may result from uncertainty and
age of respondents seeking improved programming variability in the environment, so that
tools has dropped from a high of 25% to 10%. De- the system behaves consistently across a
termining why the evolution of modern debugging tools is failing range of operating conditions. This hid-
to hit the mark as well as software-programming tools do is worth den side of engineering potentially pro-
vides insight into the challenges facing
exploring—especially when the surveys to create systems that perform and de- software-debugging tools, especially for
each year also confirm that the testing- liver a practical approach to a problem. embedded-system designers. In addition
and-debugging phase continues to be the Software-programming tools focus on to dealing with processor-architecture
one that consumes the largest amount— the creation side of software engineering. practical constraints for performance,
24%—of the project schedule. The third The survey results suggest that program- function, communication, latency, and
standout request for improvement in all ming tools are on the right path toward power consumption, embedded systems
three years’ surveys is the project-man- improving productivity for the creation often have to deal with real-world in-
agement function of scheduling (see of system code to solve problems. But the terfaces that may exhibit behaviors that
sidebar “COCOMO and evidence-based failure of debugging tools to trend down- are more difficult to predict or charac-
scheduling”). ward as a primary concern alongside pro- terize completely across the whole range
One explicit aspect of engineering is gramming tools suggests that software-de- of usage scenarios.

SEPTEMBER 4, 2008 | EDN 29


AT A G L A N C E
If debugging were only about finding  Engineering embedded systems gration and testing efforts by supporting
and correcting software-logic errors, an is not just about making them per- system-level fault injection and incre-
instruction-set simulator in conjunction form some behavior but preventing mental integration in parallel to other
with cycle-accurate simulators might them from exhibiting undesirable development activities. These types of
provide enough visibility into the be- behavior. systems can act as precursors or support
havior of embedded systems to support to hardware-in-the-loop simulations for
 Designers may be using debug-
debugging. Such simulators are avail- high-end, complex systems. These tools
ging tools as design aids because
able for most processor architectures and there are no other better means for
support prebuilt systems and assembling
software-development-tool suites. Sim- doing the job. a system from prebuilt parts or blocks.
ulators can also stop the system and ex- With additional tooling, they offer the
amine any parts of the simulated system.  Debugging embedded systems ability to build new components to inte-
Unfortunately, these types of simulators is a cross-disciplinary activity, cross- grate into the system.
usually cannot provide complete vis- ing hardware, software, and domain- One hurdle system-level simulators
expertise boundaries.
ibility into the exact interaction and la- face is cost, which can exceed by many
tency of the memory, bus architectures, thousands of dollars the price of avail-
peripherals, sensors, and actuators. Such yond the software-execution engine and able processor-centric simulators. It is
fidelity would make the simulators oper- simulate the interactions of the other possible that debugging tools are not fol-
ate even slower than they already do. parts of the system. These types of de- lowing the downward trend in the sur-
System-level simulators, such as the velopment tools can enable software de- veys with programming tools not be-
virtual-system-prototype tools from Vast velopers to work on a target before the cause they are failing to meet the func-
and the Simics virtual platform from physical hardware is available; they also tional needs of embedded-system devel-
Virtutech, have the potential to go be- can assist developers with system inte- opers, but rather because the higher-end

COCOMO AND EVIDENCE-BASED SCHEDULING


Realistic schedules are The COCOMO II model lease, or purchase. A key thought about the steps
keys to creating good incorporates changes in factor in continuing to im- necessary to complete
software. Deadlines that software development prove the predictive ac- a task. By keeping time
are too tight create avoid- over the years to estimate curacy of COCOMO II is sheets, you can compare
able stress sources that the cost, effort, and sched- good data. The COCOMO estimates with the actual
could lead to shipping ule when planning new II research group is asking results from each devel-
an incomplete project. software-development for help from the software oper and establish esti-
Recognizing that a dead- projects. The COCOMO II industry to collect data mate-scaling velocities
line is too tight forces you model is available to the from development proj- that will not only help you
to focus on the best or the public from the University ects; the data collection improve your estimates
most important features of Southern California will enable the availability over time, but also provide
first, and it helps you to Center for Systems and of a more accurate predic- you a model for Monte
make the right decisions Software Engineering tive model for estimating Carlo simulation to calcu-
about what to incorpo- Web site (Reference A). software-project costs. late and chart the proba-
rate into the final prod- COCOMO II comprises Another approach for in- bility that you will be able
uct. There have been a application-composition, corporating historical data to ship by any given date.
number of approaches to early-design, and post- into the schedule mod- Armed with the charted
helping project managers architectural submodels eling appears in a post- probable-shipping dates,
produce more accurate that provide increasing fi- ing by Joel Spolsky, chief you can explore how shift-
schedules that trade off delity according to how far executive officer of Fog ing the priorities of differ-
features, cost, and time the project-planning and Creek Software, on evi- ent features or including
for software-development -design process has pro- dence-based scheduling changes in scope may af-
projects. ceeded. COCOMO II can (Reference B). The article fect the schedule.
One such approach is assist with setting project describes the approach
COCOMO (constructive- budgets and schedules; for the model in a gen- R E FE R E NCE S
cost model), an algorith- making software-cost and eral fashion, although Fog A “COCOMO II,” http://

mic-software-cost-estima- schedule-risk-manage- Creek uses the model in sunset.usc.edu/csse/


tion model that applies a ment decisions; making its FogBugz commercial research/COCOMOII/
regression formula with trade-offs among software product. The first step is cocomo_main.html.
historical project data and cost, schedule, functions, scheduling in chunks that B Spolsky, Joel, “Evidence

current project character- performance, and qual- you measure in hours—for Based Scheduling,” Joel
istics. Software engineer ity factors; and deciding example, no more than on Software, Oct 26, 2007,
Barry Boehm first pub- which parts of a software 16 hours to ensure the www.joelonsoftware.com/
lished the model in 1981. system to develop, reuse, estimator has actually items/2007/10/26.html.

30 EDN | SEPTEMBER 4, 2008


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* CTLSH1-40M621H 1.0 40 Single, Schottky 2 x 1.5 x 0.4 TLM621H 6.7 3.1
mm mm
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CTLSH2-40M832 2.0 40 Single, Schottky 3 x 2 x 0.9 TLM832
CTLSH3-30M833 3.0 30 Single, Schottky 3 x 3 x 0.9 TLM833
CTLSH5-40M833 5.0 40 Single, Schottky 3 x 3 x 0.9 TLM833 SOT-223 TLM833

Transistors 45% 77%


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* CTLT7410-M621 1.0 40 Low VCE(SAT), PNP 2 x 1 x 0.8 TLM621

CTLT853-M833 6.0 200 High Current, NPN 3 x 3 x 0.9 TLM833 SOT-223 TLM833 TLM621H
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145 Adams Avenue, Hauppauge, NY 11788 USA • Tel: (631) 435-1110 • Fax: (631) 435-1824
debugging tools with the needed func-
tional support still exceed some critical THE LAST DECADE
cost threshold. It is interesting to note HAS SEEN SERIOUS
that this cost threshold is lower than
that for hardware-design tools, even EROSION IN ROYALTY-
though most software-development BASED OPERATING-
tools will likely support more of the ad-
ditional complexity in new systems. SYSTEM- AND
The last decade has seen serious ero- DEVELOPMENT-TOOL-
sion in royalty-based operating-system-
and development-tool-license models.
LICENSE MODELS.
The growing success of Linux as an op-
erating system in embedded systems is
due largely to the cost advantage of us-
ing open-source software. Additionally,
many embedded-system tools from sili-
con providers have adopted the open-
source Eclipse platform to host their
development tools, which substantially
reduces the cost of building these tools,
simplifies configuring their tools by the Cortex-M3 core supports a new real-
end user, and allows them to focus their time-trace capability. Trace enables re-
engineering effort on the features of the verse-order instruction execution, which
tools rather than the look and feel of the more simulators are supporting. The
host environment. This observation is Green Hills Software Multi Time Ma-
not to say that debugging tools have not chine debugging suite enables develop-
followed the same downward trend in ers to swap between on-chip debugging
pricing. At the extreme, many processor and simulator debugging to support sim-
vendors offer small evaluation kits that ulated reverse-order execution.
allow developers to experiment with IEEE-ISTO 5001-2003, the Nexus
the systems for much less than $100. In- 5001 Forum open industry standard for
deed, many development kits that cost a global embedded-processor-debugging
hundreds of dollars today include fea- method, provides a general-purpose in-
tures you would find a decade ago only terface for the software development
in much costlier tool sets. and debugging of embedded processors.
As on-chip-debugging circuitry ex- The initial focus of the Nexus 5001 Fo-
pands on contemporary processor archi- rum was automotive power-train appli-
tectures, the industry may continue to cations, but its result has evolved to be-
see the higher-end-debugging functions come a general-purpose standard. The
finding their way into lower-cost devel- Nexus 5001 Forum membership spans
opment-tool kits. Many processors, in- the semiconductor, development-tool,
cluding small, 8-bit processors, contain and automotive-electronics industries.
some proprietary on-chip-debugging cir- As the cost of silicon continues to drop
cuitry. “The on-chip-debug system is one and on-chip-debugging interfaces and
of the most complex circuits in the chip functions become standard, processor
because it has to non-intrusively inter- providers will likely flow high-end on-
connect with all of the subsystems,” says chip-debugging capabilities from high-
Dag Arne Braend, AVR-development- end processors to lower-end processors
tool director at Atmel. “And it has been to provide even more on-chip visibility.
difficult to justify incurring the extra This step will become necessary to gain
cost for this complexity for something design wins.
that many systems will never use in field
DESIGN AID
intersil.com/power
devices.”
Real-time trace appears to be the next John Lambert, chief executive offi-
emerging on-chip-debugging capabil- cer of Virtutech, offers an immediate
ity moving down the processor hierar- possible mitigating factor for the higher
chy. Processors using ARM cores with costs in favor of system-level-simulation
an ETM (embedded-trace macrocell) tools. “A development team usually ac-
enable the downloading of instruction quires our platform to support either the
and data traces from the processor. The front or the back end of its current proj-
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©2007 Lattice Semiconductor Corporation. All rights reserved. Lattice Semiconductor Corporation, L (& design), Lattice (& design), LatticeECP2M, LatticeECP2, LatticeSC, LatticeXP, TransFR, and specific product desig-
nations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries, in the United States and/or other countries. Other marks are used for identification purposes only, and
may be trademarks of other parties.
ect, but once the team uses the tool, it
more fully realizes its value and uses it at ONE REASON YOU
both ends of the design cycle in future MIGHT CALL THEM
projects,” he says.
This theory exposes another possi- DEBUGGING TOOLS
ble disconnect in what embedded-sys- INSTEAD OF DESIGN
tem designers mean when they say they
need better debugging tools. A primary AIDS IS THAT THE
Direct
function of debugging tools is to pro-
vide visibility into the state of the sys-
CAPABILITIES OF THE Online
tem during runtime. When a system in- TOOLS ARE UNUSABLE Ordering
cludes complex interfaces, sensors, and UNTIL THE SYSTEM-
actuators, a debugger may be the most
expedient tool available for examining
INTEGRATION PHASE
these external systems’ functions be- OF A PROJECT.
cause accurate signal generation for all
of the tightly coupled subsystems is a
major challenge. Therefore, one reason
you might call them debugging tools in-
stead of design aids is that the capabili-
ties of the tools are unusable until the
system-integration phase of a project,
when debugging is well under way.
Looking at debugging tools as design
Check real-time
aids provides a valuable perspective, es- A second example involved taking
pecially when working with closed-loop- the system-integration-test data and availability
control systems where the outputs affect running it through a spreadsheet pro-
the inputs of a system. It can be chal- gram to analyze whether the closed-
lenging to verify the behavior of closed- loop-control algorithm was performing
loop-control systems. I have used end- properly. Again, no amount of software
system software and sensor hardware to simulation or design effort could ac-
characterize and validate how an auto- count for actually hooking the equip-
matic-gain-control algorithm worked
with a sensor across a range of expect-
ment together and collecting the data;
it was more cost-effective to run the
Order with
ed circumstances (Reference 2). There
was no way to simulate this condition or
tests during integration than to try to
create one-time-accurate models of the
your credit card
even test for something like it in a pure prototype system. However, I did use
software-debugging environment be- the information I learned about the sys-
cause there is no accurate model for the tem behavior to build simulation mod-
sensor. As a result, I discovered an un- els for the next-generation-develop-
known characteristic of the sensor before ment work.
it was too late. Another characteristic of debugging
embedded systems is that problems are Ships within 2
+ For related blog posts about embed- not necessarily solely from software er-
ded processing, go to www.edn.com/ rors. However, because it is much more business days
blog/1890000189.html. cost- and schedule-effective to fix most
problems in software, designers usual-
+ For a related article about the
ly implement a software fix to resolve
Eclipse development platform, go to
problems. However, making and record-
www.edn.com/article/CA373866.
ing a fix as a software change belies the
+ For related material about flexible amount of cross-discipline cooperation
silicon, visit www.edn.com/article/ necessary to find, diagnose, and deter- intersil.com/ibuy
CA6558499. mine an acceptable resolution. In fact,
many embedded-system-debugging prob-
+ Go to www.edn.com/080904df
lems are cross-disciplinary, requiring un-
and click on Feedback Loop to post derstanding and expertise of the system
a comment on this article. hardware, software, and domain-specific
+ For more technical articles, go to constraints. This situation does not pose
www.edn.com/features. a problem if the person doing the system-
integration testing happens to be an ex-
pert in all three of these disciplines, but comes through the USB connection,
those types of people are rare indeed. which greatly simplifies the power set-
Because of the cross-disciplinary na- up for using those boards. The interfac-
ture of debugging embedded systems, es to send commands and collect data
debugging tools and engineering ser- between the embedded system and the
vices have an opportunity to fill a void. host system are now simpler to use, and
Just because a debugging tool provides a there is talk of using wireless interfaces
specific type of visibility into the system for debugging systems in the near future.
does not mean that developers will use Many development-tool sets provide
Precisely What that feature. David Kleidermacher, chief a preconfigured setup and allow devel-
technology officer at Green Hills Soft- opers to test the board to confirm that
You Need! ware, agrees. “Too many options in tools it and its tools are working properly in
require a larger learning curve for devel- a known circumstance. Reid Tatge, a
opers, [which] results in a low adoption technical fellow at Texas Instruments,
rate of many of those features,” he says. explains that a goal of the company’s de-
Developers tend to use the simplest fea- velopment tools is to make embedded
tures due to time pressure, and develop- development look like the development
ers adopt these advanced features more of “wintel” systems—those based on In-
as part of a lesson they learned from pre- tel microprocessors and Microsoft Win-
vious projects. Partly in response to this dows operating systems—to ease the
realization, Green Hills added an “al- learning curve for designers to use their
ways-on” trace capability to its Multi embedded processors.
Time Machine debugging tool; the trace Micrium’s ␮C/Probe aims to make
has become more useful to developers it easier for developers to quickly visu-
because the default condition costs the alize what is going on in their systems.
developer practically nothing, requires The tool consists of two pieces of soft-
no learning curve to use, and is more ware—one that runs on the host sys-
effective than explicitly turning on the tem and performs the data analysis and
trace-capture function. display and one that acts as a code stub
Another challenge facing develop- that you load on the target system. The
ers debugging embedded systems is set- stub manages I/O and resource queries
up and configuration of the testbench. as well as communication with the host
This issue is a low-cost, high-value con- system. Although it is an intrusive form
cern that many tool providers are trying of instrumenting the embedded-system
to address in their tool sets. The power code, it provides runtime access to the
supply for many evaluation boards now system without halting your system. The
tool is available for around $1000.
National Instruments’ LabView pro-
F O R M O R E I N F O R M AT I O N vides strong visualization support and
ARM Microchip includes a graphical-programming ca-
www.arm.com www.microchip.com pability. It also includes built-in mea-
Atmel Microsoft surement and analysis functions that it
www.atmel.com www.microsoft.com
organizes around application domains so
Cadence MIPS
www.cadence.com www.mips.com that developers can select which capa-
Eclipse National Instruments bilities to use. The debugging visualiza-
www.eclipse.org www.ni.com tions are well-suited for data-flow execu-
Fog Creek Software NEC of America tion models. Prices for tool sets that in-
www.fogcreek.com www.necam.com tegrate hardware, software, and domain-
Freescale Nexus 5001 Forum specific functions start at around $1000
www.freescale.com www.nexus5001.org
Green Hills Software Renesas
but can exceed $10,000 if you need to
www.ghs.com www.renesas.com add on a heavy amount of domain-spe-
intersil.com/pinpoint Hi-Tech Software Texas Instruments cific tools.
www.htsoft.com www.ti.com This type of pricing flexibility illus-
Intel Vast trates a challenge for many tool provid-
www.intel.com www.vastsystems.com
ers; customers want to pay for only the
Keil Virtutech
www.keil.com www.virtutech.com
right level of visibility based on different
Lauterbach Wind River
touch points. For example, some devel-
www.lauterbach.com www.windriver.com opers target an operating system and do
Micrium not concern themselves with the details
www.micrium.com of the underlying processor architecture.
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Other developers target the instruction- ta that can make it to the host system take advantage of those hidden resourc-
set architecture. Still others worry about for real-time and post-runtime analy- es. But it is a far cry from having a tool
lower-level interactions, such as those in sis. Additionally, processor vendors do that an expert can use in a limited sit-
the architecture layer, which connects not always expose features to the pub- uation to making that tool robust and
all of the resources in the system. lic that they implement on a chip; they usable across a wide range of scenarios
Even when the tools provide the vis- may choose to hide those features be- and expertise levels. Unfortunately, en-
ibility a designer needs, knowing what cause the features are experimental and gineering services are labor-intensive
to look for is another hurdle because vendors are not ready to provide robust, and expensive—far exceeding the cost
the communication link between the production-level support for them. In- threshold of most software-development
on-chip system and the host system lim- ternal tools and expert field-applica- budgets except in the most dire of trou-
its the amount and type of captured da- tion-engineering services, however, can bleshooting scenarios.
To continue evolving, debugging tools
require correlated input from hardware,
software, and domain experts. In some

Customize It. situations, there is a negative incentive


for customers of processor or tool pro-
viders to share their hard-learned les-
sons. If they share the key lessons with
tool developers, they may shorten the

Test It. learning curve necessary for competi-


tors and avoid incurring the scheduling
and engineering-expertise cost of learn-
ing how to make the embedded system
work in a certain way. The experience
of field-application engineers can help

Validate It. give tool developers the necessary in-


sight to make debugging tools more use-
ful in these cases.
Embedded systems have for decades
been implementing multiprocessor de-
signs, but new opportunities for tightly
coupled multicore and multiprocessor
systems continue to emerge. Addition-
ally, a growing number of embedded sys-
tems are using even more sensors in their
systems so that they can adequately take
on and manage more complex behav-
iors. These trends in emerging embed-
ded systems will require debugging tools
to deliver even stronger coherency and
When Efficiency & Reliability Are Mandatory related visualization features because the
interactions between the subsystems will
Get the Advanced® Difference continue to become more complex than
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com, Sept 2, 2007, www.embedded.
ball terminals for process yields comparable with
com/design/opensource/201803499.
direct device attach. Multi-finger contacts 2 Cravotta, Robert, “Valuing Uncertain-
and screw-machined terminals assure ty,” EDN, Jan 5, 2006, pg 38, www.edn.
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EDA TOOLS ADDRESS SIMULATION, VERIFICATION, AND LAYOUT FOR MIXED-SIGNAL DESIGNS.

nalog simulators and design-capture mandates better analog-design tools.

A
tools have a venerable history in the Mar Hershenson, vice president of
product development at Magma De-
EDA market, having long added some sign Automation’s custom-design-
Spice to their digital-simulation coun- business unit, describes analog design
terparts. When it comes to converting as it has occurred over the last 20
simulations to sine waves and silicon, years as the work of artists, with en-
however, analog-EDA tools fall short gineers manually designing op amps
and other analog functions. As if an-
of what has been possible in the digi- alog design weren’t difficult enough,
tal domain. That scenario is beginning she adds, integrating the analog and
to change. Tools are emerging from traditional digital-EDA the digital portions of a mixed-signal
providers that support the fabrication of analog functions in design can take weeks. Further, for
nanometer-geometry digital processes. In addition, foundry- every process node, analog-system
specific tool kits are easing the implementation of analog, RF, engineers must manually re-create
designs.
and high-voltage functions in analog processes. And even ICs that are function-
Designers cannot expect smooth log, during this year’s DAC (Design ally digital—that is, producing no
sailing, though; full automation of Automation Conference) keynote signals other than zeros or ones—are
analog- and mixed-signal design re- address (Reference 1). Not all prob- exhibiting behavior that requires
mains elusive. Even analog-Spice en- lems are amenable to digital compu- analog-design and -test techniques.
gines may run out of steam as chips tational solutions, however. You can’t That situation is particularly true of
become more complex, requiring readily “calculate” a 120V signal lev- the high-speed serial interfaces that
excessive times for full-chip simula- el, no matter how many 45-nm digi- let chips communicate with the out-
tion, even with fast-Spice implemen- tal transistors you throw at the prob- side world.
tations. Nevertheless, vendors are lem. And, apart from voltage and
working on multiple fronts to bring current levels, the need for analog IP AND ANALOG BEHAVIOR
automaton to the traditionally hand- functions isn’t going away. As Texas The term analog conjures up vi-
crafted analog-design task. Instruments Senior Vice President sions of op amps and data convert-
One way to deal with analog de- Gregg Lowe points out, the transi- ers, but, explains Navraj Nandra, di-
sign is to reformulate analog prob- tion to digital—for instance, music’s rector of marketing for mixed-signal
lems as computational ones. Justin transition from vinyl to MP3—re- IP (intellectual property) at Synop-
R Rattner, vice president and chief sults in an increase in analog content sys, “The speeds of today’s chips’ se-
technology officer at Intel, suggested (Reference 2). rial-digital-I/O lines ensure that an-
that approach, digitally assisted ana- The need for more analog content alog effects come into play” even in

40 EDN | SEPTEMBER 4, 2008


SEPTEMBER 4, 2008 | EDN 41
AT A G L A N C E
ostensibly all-digital parts. Complicat-  Full automation of analog- and geographically dispersed design teams
ing matters, he says, is that pure-ana- mixed-signal design remains elusive. having diverse skills.
log companies have the luxury of im- The Cadence approach, says Lewis, is
 Integrating the analog and the
plementing functions in processes opti- “to build an umbrella solution” that al-
mized for analog circuitry. In contrast, digital portions of a mixed-signal lows engineers to work in whichever do-
companies making digital chips want to design can take weeks, and, for main makes the most sense for them. To
every process node, analog-system
implement their high-speed I/O in stan- that end, Cadence works to break down
engineers must manually re-create
dard deep-submicron digital processes— designs.
the boundaries between analog and digi-
with all the attendant process-variation tal verification as well as analog and dig-
and signal-integrity issues.  Companies making digital chips ital implementation (Figure 2).
Synopsys addresses serial-I/O-de- want to implement their high-speed To allow each domain to understand
sign problems with its DesignWare IP I/O in standard deep-submicron the other without translation, the imple-
to implement functions, such as USB digital processes—with all the atten- mentation stage, for instance, brings Ca-
dant process-variation and signal-
2.0, DDR2/3 memory, SATA (serial- dence Virtuoso and Cadence Encounter
integrity issues.
advanced-technology-attachment), together under Si2’s OpenAccess, which
and PCIe (peripheral-component-in-  Mixed-signal design has tradi- Lewis describes as necessary but insuffi-
terconnect-express) 2.0 interfaces. The tionally involved forcing the analog cient for an effective mixed-signal flow.
DesignWare PCIe 2.0 product, for ex- domain within the digital domain or Cadence engineers have brought Vir-
ample, includes the PHY (physical-layer vice versa. tuoso and Encounter together, ensuring
interface), operating at 5 Gbps, as well the maintenance of digital connectivity
as a digital controller and verification IP. ing digitally assisted analog, Lewis says during analog editing and the locking of
Nandra notes that Synopsys has success- that forcing one domain into another is analog portions during digital-floorplan-
fully produced a USB 2.0 PHY in 65-nm becoming untenable. “At 65 and 45 and ning adjustment. Within the combina-
processes at fabs Chartered Semicon- 32 and 22 nm, you have this blurring of tion, Encounter supports PCells (pa-
ductor, Samsung, and IBM—all with a lines,” he says. “It’s not so obvious where rameterized cells), multipart paths, and
single GDSII (graphic-design-system II) the analog and digital pieces begin and guard rings. Lewis says that a customer
file with no modifications. end.” has reported a 25% reduction in overall
IP isn’t useful if it isn’t testable in the An isolated analog/digital approach is mixed-signal-design-cycle time.
lab or on the production floor. For lab no longer sufficient and must give way Magma based its approach on tech-
tests, Synopsys obtains split-lot samples to approaches that permit top-down de- nology it obtained with the February ac-
from foundries and evaluates them us- sign and that let customers mix method- quisition of Sabio Labs. Magma’s Hersh-
ing demo boards, performing eye-dia- ologies, according to Sandy Mehndirat- enson, who was formerly chief executive
gram-mask tests using bench-top os- ta, group director for custom ICs at Ca- officer of Sabio, says that the technology
cilloscopes (Figure 1). For production dence. Lewis adds that an effective de- accelerates mixed-signal- and analog-
test, Synopsys builds diagnostic IP into sign strategy must also support multiple design migration through Magma’s Ti-
its PHYs—essentially on-chip tan Chip Finishing and Titan
sampling oscilloscopes acces- Analog Migration platforms.
sible through a JTAG port, en- Titan employs a unified-da-
abling a conventional digital tabase architecture and sup-
tester to perform real-time eye- ports fast shape-based routing
diagram-mask testing. Nandra and full-layout editing; it in-
elaborates on the on-chip test cludes a complete encapsula-
technology in Reference 3. tion of Magma’s Talus digital-
design platform and Quartz
MIXED-SIGNAL FLOWS DRC (design-rules-checking)
The ultimate goal of main- and Quartz LVS (layout-ver-
stream-EDA companies is to sus-schematic) verification
bring what they might perceive tools. Titan can also instanti-
as the pushbutton ease of oper- ate PCells.
ation of digital-design flows to Magma integrates the Titan
analog- and mixed-signal de- Analog Migration platform
sign. Mixed-signal design, says with the company’s FineSim,
Steven Lewis, product-market- Figure 1 An eye-diagram-mask test illustrates the performance which in turn supports multi-
ing director at Cadence Design of Synopsys PHY IP for PCIe 2.0. You can directly observe CPU Spice simulation. Titan
Systems, has traditionally in- the diagram on an oscilloscope from a demo board; for pro- Analog Migration allows en-
volved forcing the analog do- duction test, an internal sampling-scope function makes the gineers to migrate their analog
main within the digital domain eye diagram available to a standard digital ATE (automatic- designs from one process node
or vice versa. Citing the com- test-equipment) system through a JTAG port. to another in a matter of hours,
ments of Intel’s Rattner regard- says Hershenson. Indicative of

42 EDN | SEPTEMBER 4, 2008


Microcontrollers
NEW Single-wire EEPROM Family
In a Tiny 3-lead Package!
The Microchip name and logo, the Microchip logo and MPLAB are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. UNI/O is a trademark of Microchip Technology Incorporated

Controllers
Digital Signal
in the U.S.A. and other countries. All other trademarks mentioned herein are property of their respective companies. © 2008, Microchip Technology Incorporated. All Rights Reserved.

Analog
EEPROMs
Serial
Microchip Technology’s new UNI/O serial EEPROM uses only ONE connection to GET STARTED TODAY!
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www.microchip.com/UNIO
Titan Chip Finishing’s speed, she said it
SYSTEM DESIGN
can open a 42-Gbyte file in 4 minutes
and can redraw a full chip in 8 seconds.
Mentor Graphics’ approach is to bring
together design-implementation and DESIGN SYNTHESIS
-verification tools into an analog/mixed-
signal-design flow that a data-manage-
ment system governs (Figure 3), accord- MIXED-SIGNAL VERIFICATION
ing to Min-Fang Ho, general manager of
Mentor’s custom-IC division. The De- ANALOG DIGITAL
AND RF MIXED-SIGNAL IMPLEMENTATION
sign Manager data-management tool al-
lows users to collaborate among multiple
sites or handle revision control. Other
components include Design Architect PARASITIC
TIMING
IC for schematic capture, IC Station and EXTRACTION
ANALYSIS
ICassemble layout and assembly tools, AND VERIFICATION

Eldo and ADiT simulators, and Calibre


physical-verification tools.
FLOW-SPECIFIC CHIP ASSEMBLY
Henry Chang, Mentor’s director of
marketing for analog- and mixed-signal
tools, elaborates on the simulation por- TOP-LEVEL VERIFICATION
tion of the flow. Eldo is a Spice-based
simulator, Eldo RF adds RF extensions, Figure 2 Breaking down the boundaries between analog and digital verification and
and ADiT is a fast Spice simulator that implementation is the goal of Cadence’s mixed-signal-design flow. The implementation
trades some accuracy for speed. Mentor’s stage, for instance, brings together Virtuoso and Encounter under OpenAccess, allow-
ADVance tool, he says, brings together ing each domain to understand the other without translation.
those simulators and combines them with
Mentor’s ModelSim digital simulator to
verify complete mixed-signal designs. transistors operating at 3.3, 20, 50, and components is a long and difficult pro-
IDMs (integrated-device manufactur- 120V on a single die, each transistor re- cess that can take a month at minimum
ers) and foundries also offer mixed-sig- mains within its safe operating range. and is not user-friendly,” says Hemon.
nal-EDA tools. Austriamicrosystems, The process needs acceleration through
for example, offers the HIT-KIT (high- LOOKING TO THE FUTURE parallel-processing support.
performance-interface-tool kit)—a util- As for what designers would like to Freescale engineers employ many pro-
ity comprising software programs and see from EDA companies, topping the prietary, in-house design-automation
libraries that support behavioral simu- list are multithreaded versions of Spice tools that provide leading-edge perfor-
lation, digital synthesis, schematic cap- that can take full advantage of multi- mance not available from commercial
ture, mixed-signal simulation, layout, core processors. Austriamicrosystems’ tools, but Hemon notes that a commer-
design verification, and back-annota- Mörth notes that, although some Spice cial tool could be a viable alternative
tion within Cadence, Mentor, and Syn- implementations use multiple cores, once an internal tool has lost its ability
opsys design environments. According they generally rely on a single core to to provide differentiation. Daniel and
to Thomas Riener, general manager of solve the set of matrix equations that
austriamicrosystems’ full-service-found- describe the simulated circuit. “You can F O R M O R E I N F O R M AT I O N
ry-business unit, the kits provide a con- buy more and more hardware, but it gets austriamicrosystems Intel
sistent user interface for the company’s to a point where that no longer helps,” www.austriamicro www.intel.com
internal designers and foundry custom- says Riener. “If you want to do a top- systems.com Magma Design
ers. Thomas Mörth, manager of design level simulation that takes three weeks, Cadence Design Automation
Systems www.magma-da.com
support at the foundry-business unit, it will continue to take three weeks no www.cadence.com Mentor Graphics
notes that the kits add custom features, matter how many CPUs you add to your Chartered www.mentor.com
such as the ability to verify that, with server farm.” Semiconductor OpenAccess
www.charteredsemi.
Steven Daniel, worldwide R&D man- com
www.openeda.org

+ Go to www.edn.com/080904cs ager of the analog, mixed-signal, and Design Automation


Samsung
www.samsung.com
and click on Feedback Loop to post
power division at Freescale Semicon- Conference
www.dac.com Si2
a comment on this article.
ductor, and Erwan Hemon, the world- www.si2.org
wide automotive-IC-creation manager Freescale
Semiconductor Synopsys
+ For more technical articles, go to at the same division, also would like to www.freescale.com www.synopsys.com
www.edn.com/features. see faster simulators. “Top-level simula- IBM Texas Instruments
tion of a full chip with analog and digital www.ibm.com www.ti.com

44 EDN | SEPTEMBER 4, 2008


ELECTRONIC COMPONENTS system-level IP | SERDES | embedded memory | system in package | embedded microprocessor | mixed-signal IP

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*Qualified Engineers only ©2008 Toshiba America Electronic Components, Inc. All rights reserved.
lan n in g an
P sed
rn e t -ba
Ethe
s t S ys te m?
Te SCHEMATIC CAPTURE
SIMULATION CONTROL
INTERACTIVE
ANALYSIS
DESIGN
VERIFICATION

TECHNOLOGY-
DESIGN KIT

Consider ICS's DATA SCHEMATIC/


SYMBOLS
DEVICE GENERATORS
SPICE MODELS INTERACTIVE
MANAGEMENT CONSTRAINT- PARASITIC
VXI-11 Interfaces DRIVEN
LAYOUT
DESIGN-RULE CHECK/
LAYOUT VERSUS SCHEMATIC/
PARASITIC-EXTRACTION FILES
DEBUGGING

TECHNOLOGY FILE
• The widest varity of VXI-11
interfaces from any vendor LAYOUT
PHYSICAL
INTERACTIVE VERIFICATION/
FLOORPLAN AND VERIFICATION EXTRACTION
ASSEMBLY

Figure 3 Allowing users to collaborate among multiple sites, Mentor Graphics’ Design
Manager data-management tool orchestrates an interactive analog/mixed-signal design
flow. Within the flow, Design Architect IC handles schematic capture and simulation
control; IC Station and ICassemble perform layout, floorplanning, and assembly; Eldo,
ADiT, and ICAnalyst handle design verification; and Calibre DRC/LVS and Calibre xRC
128 line digital I/O boards handle physical verification and extraction.
with optional relay drivers.
Hemon list several features they would velop complex device models that de-
want to see in commercial tools: support signers can efficiently simulate. Finally,
for high-voltage transistors, not just low- Ho notes, printability issues are affect-
voltage CMOS transistors; the ability to ing designs at 40 nm, and manufacturers
model ESD (electrostatic-discharge) ef- might btter address those issues at the
fects; and the ability to predict defect design stage rather than through RET
rates and aging effects. To capture de- (reticle-enhancement-technology) and
fects in the analog portion of mixed-sig- OPC (optical-process-correction) tech-
Standalone boxes with
nal silicon, Hemon says Freescale engi- niques.EDN
digital, relays, Modbus RTU neers would like to develop a test meth-
and GPIB interfaces. odology similar to the digital domain’s R E FE R E NCE S
IDDQ (integrated-circuit-quiescent-cur- 1 Nelson, Rick, “Analog—that com-

rent) test. Finally, they would like to see putes,” Test & Measurement World,
• VXI-11 means easy control test-program-generation support. June 11, 2008, www.tmworld.com/
from Linux, Unix and EDA vendors aren’t specific about article/CA6569252.
Windows PCs with C, what’s just over the horizon, but Ca- 2 Rako, Paul, “Analog maestro plays to

dence’s Lewis says his company is look- medical and other emerging markets,”
VB or LabVIEW. ing at bringing assertion-based approach- EDN Innovators 2008, June 2008, pg
es—common in the digital world—to 28, www.edn.com/article/CA6569192.
• The payoff is faster, less facilitate verification and test of mixed- 3 Nandra, Navraj, “On-chip test capa-

signal designs. bilities solve the analog-test problem for


costly designs! Mentor’s Ho says that efforts are un- high-speed serial interfaces,” EDN, Aug
der way to improve the communication 21, 2008, pg 43, www.edn.com/article/
of design intent from the schematic- CA6586230.
Celebrating 30 Years! capture and simulation area to the im-
plementation area. Such an approach
would invoke principles and guidelines You can reach
ICS that would facilitate automation of some Editor-in-Chief
ICS ELECTRONICS Rick Nelson
tasks but still provide flexibility. Chang at 1-781-734-8418
division of Systems West Inc. says that, to support mixed-signal design and rnelson@
and implementation at 45-nm process reedbusiness.com.
Visit www.icselect.com nodes, foundries and EDA companies
or call +1 925 416 1000 will need to work closely together to de-

46 EDN | SEPTEMBER 4, 2008


Cadence OrCAD Capture CIS with Digi-Key Integration
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an OrCAD Capture CIS user has access to over 1,000,000 parts in the Digi-Key
SI database with device parameters, RoHS compliance status, cost, quantity on
hand, and mechanical dimensions.
Streamline the part introduction process
Custom IC Often times a temporary part has to go through an extensive internal review
process by purchasing, manufacturing, and documentation groups before it can
be approved for use. Every new part introduced requires significant administrative
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©2008 EMA Design Automation, Inc. All rights


reserved in the U.S. and other countries. Cadence
and OrCAD, are registered trademarks of Cadence
Design Systems, Inc. Digi-Key is a registered
trademarks of DigiKey Corporation. All other
marks are the property of their respective owners.
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USB 2.0 Input Charger Manager LED
OTG/LBR
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Power
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# of Inputs/Outputs 2/2 1/1 1/1 1/1 Step-up (Boost) 2 or 4 2 or 3 1 or 2
Maximum Charge Current (mA) 1500 1250 900 210/525 Inverter (Buck-Boost) 0 or 1
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Using FPGAs
in consumer electronics
IN COST-SENSITIVE CONSUMER-ELECTRONICS PRODUCTS,
CUSTOMIZATION IS A HIGHLY DESIRABLE FEATURE FOR
DIFFERENTIATING YOUR PRODUCT FROM COMPETITORS’ OFFER-
INGS. THE INCLUSION OF FPGAs CAN BE AFFORDABLE, EVEN
IN LOW-RANGE AND MIDRANGE PRODUCTS, BUT STILL ALLOWS
CUSTOMIZATION THROUGH SOME UNIQUE FEATURES.

t may seem odd to be reading about analog-audio and -vid- manufacturers, such as Analog Devices (www.analog.com),

I
eo processing when the industry is currently focusing on which offers the AD9981. The ADC also performs synchro-
the analog transmission switch-off and the digital-broad- nization-separation and clock-generation functions and can
casting successor. However, for legacy reasons and because interface to CVBS (composite-video-broadcast-signal), YC
of the increase in demand from markets that have later (S-video), YPbPr (green/blue/red), and RGB (red/green/blue)
switch-off dates, such as East Europe, India, and South inputs. An external ADC usually achieves a better SNR (sig-
America, it is likely that analog decoding will be a require- nal-to-noise ratio) than that of an integrated alternative, but
ment well into the next decade. the cost of implementation is about 50% higher than that of
Several typical blocks constitute analog-front-end-acquisi- a standard-IC option. However, integrating additional func-
tion circuits (Figure 1). You generally achieve the SIF (sound- tions into the FPGA can mitigate this cost increase.
intermediate frequency) and video decoding through the use For example, it is common for recorders to allow users to
of one or two ICs from a number of manufacturers. The system record one channel while watching another or for televi-
requires external memory if it includes a 3-D comb filter, as sions to have picture-in-picture features. Such capabilities
well as, perhaps, a baseband-audio-stereo ADC. Repetitions of require two digital tuners, two analog tuners, two decoders,
these blocks exist in multituner-system configurations. and, therefore, two sets of ICs in the non-FPGA implementa-

CORES VERSUS ICs


3-D COMB MEMORY
Video- and audio-decoding IP (intel-
lectual-property) cores conceptually allow
the replacement of these ICs with FPGAs. YPBPR
Area-efficient implementations enable YC THREE VIDEO DECODER 1 BT656/1
OR FOUR (NTSC/PAL/SECAM)
you to incorporate the functions in cost- CVBS ADCs
effective FPGA products, such as Altera’s
BASEBAND VBI PROCESSING
(www.altera.com) Cyclone and Xilinx’s AUDIO .
(www.xilinx.com) Spartan families. One SIF DECODING
way to keep down the cost of the FPGA CVBS (NICAM, A2, BTSC, I2S/1
is to allow different FPGA images for differ- EIA-J)
SIF
ent standards, with the main control pro- TUNER 1
cessor downloading the appropriate image AUDIO ADC I2S
depending on the detected standard. Image
sets might comprise, for example, NTSC CVBS
BT656/2
VIDEO/SIF
(National Television System Committee) DECODER
I2S/2
and BTSC (Broadcast Television Systems TUNER 2 SIF
Committee) or PAL (phase-alternating line)
and NICAM (near-instantaneous com- NOTES: BTSC: BROADCAST TELEVISION NTSC: NATIONAL TELEVISION SYSTEM COMMITTEE.
panded-audio multiplexed). Using the main SYSTEMS COMMITTEE. PAL: PHASE-ALTERNATING LINE.
control processor to initialize the FPGA CVBS: COMPOSITE-VIDEO-BROADCAST SIGNAL. SECAM: SÉQUENTIEL COULEUR AVEC MÉMOIRE.
EIA-J: ELECTRONIC INDUSTRIES SIF: SOUND INTERMEDIATE FREQUENCY.
also offsets the cost of an EEPROM to hold ASSOCIATION OF JAPAN. VBI: VERTICAL-BLANKING INTERVAL.
the FPGA image. 2
I S: INTER-IC SOUND. YC: S VIDEO.
YPBPR: GREEN/BLUE/RED.
The FPGA does not incorporate signifi- NICAM: COMPANDED-AUDIO
NEAR-INSTANTANEOUS
MULTIPLEXED.
cant analog functions; an external IC must
perform the analog-to-digital conversion. Figure 1 Several key function blocks constitute a typical front-end-acquisition circuit.
Such ICs are available from a number of

SEPTEMBER 4, 2008 | EDN 49


ands
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bsite oducts CVBS IN DELAY +
ur we r ⳮ
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SURFACE Plug-in TABLE CHROMINANCE
Mount
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DELAYS

ofile DC-DC CONVERTERS NOTE: CVBS: COMPOSITE-VIDEO-BROADCAST SIGNAL.


Low Pr
Surface Mount • PC Board Mount
Single and Dual Output • Up to 10,000V Std.
Figure 2 Nontraditional comb-filter designs maximize image quality and still fit within the
memory budget available in small, cost-effective FPGAs.
SURFACE Plug-in
Mount

tion. However, you can embed two de- ing that requirement from the main con-
coders within one small FPGA, thereby troller. For example, a microcontroller
limiting the incremental cost to one ad- can issue a simple high-level instruction
ower DC-DC CONVERTERS
High P ditional ADC. To reduce area, it may to tune channels. Advantages of this ap-
Regulated, Up to 400 Watts
Up to 100 volts Standard
be possible to limit decoder options for proach include faster initial channel-ac-
Military
the secondary channel by, for example, quisition times and the ability to power
INdustrial
omitting SECAM (séquentiel-couleur- down more of the main controller under
avec-mémoire) decoding. The total cost standby conditions; this approach has
of the FPGA option, as a result, will be appeal in today’s “green” society.
similar to or even less than that of the You can incorporate additional func-
oltage DC-DC CONVERTERS IC option. tions for higher-end consumer products
High V Up to 10,000 VCD Output
Up to 300 Watts
by integrating the SDI (serial-digital-
NEW Dual Outputs New Regulated Output TUNER ALTERNATIVES interface) receiver. FPGAs now offer
Next, consider how to include addi- LVDS (low-voltage-differential-signal-
tional functions in the FPGA. The con- ing) receivers and clock-recovery cir-
ventional metal-“can” analog tuner con- cuits, which permit the implementation
tains two main functions: an RF tuner of an SDI receiver with just an exter-
and a demodulator. You can reduce the nal cable-equalizer IC. This approach is
AC-DC POWER SUPPLIERS cost of the tuner by alternatively per- considerably cheaper than using a com-
Linear • Switches • Open Frame forming demodulation digitally within plete SDI-receiver IC.
Low Profile • Up to 200 Watts
the FPGA. The video ADC can digitize IC-based video-decoder options usu-
the video IF. The cost savings from elim- ally also strip off the information in the
inating the need for a tuner will double vertical-blanking area of the signal, but
in the case of dual-tuner products. This they leave the processing of that por-
option also opens the possibility of us- tion of the signal for the main processor.
ing a silicon tuner, whose performance Again, having some specialized hard-
POWER FACTOR
is now adequate for most consumer ware and a local controller within the
CORRECTED MODULES
Universal Input • 47-440 hz products. The silicon tuner, with its FPGA permit, for example, closed-cap-
to 1000 Watts • 99 Power Factor all-region capability, brings possibilities tion decoding. Decoding closed-caption
for cost-effective, all-region consumer or Teletext subtitles is common in tele-
products with corresponding manufac- visions, but less so in PVRs (personal
turing-cost savings. Metal-can tuners, video recorders) and DVD (digital-vid-
conversely, are usually region-specific for eo-disc) recorders. However, superim-
unit-cost reasons. posing the subtitle on the output BT656
PICO Another FPGA-enabled possibility is
to add local intelligence through the in-
video, as an FPGA can do, allows the
recording of subtitles for deaf and par-
Electronics,Inc.
143 Sparks Ave. Pelham, N.Y. 10803-18889
tegration of a small microcontroller core tially deaf users. You could embed the
for front-end functions, thereby offload- decoded subtitles in the MPEG (Mov-
Call Toll Free 800-431-1064
E Mail: info@picoelectronics.com
FAX: 914-738-8225
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FPGA

PSEUDO-3-D COMB MEMORY


YPBPR
VIDEO DEMODULATION/
YC DECODER 1 BT656/1
CVBS (NTSC/PAL/SECAM)
VBI PROCESSING
BASEBAND (TELETEXT/CC DECODING)
AUDIO .
SIF DECODING
(NICAM, A2, BTSC, EIA-J) I2S/1

FOUR PSEUDO-3-D COMB MEMORY


CVBS/VIF ADCs
VIDEO DEMODULAION/
SIF DECODER 2 BT656/2
TUNER 1 (NTSC/PAL)

CVBS/VIF VBI PROCESSING

SIF DECODING
I2S/2
(NICAM, A2, BTSC, EIA-J)
TUNER 2 SIF
CONTROL MICROPROCESSOR

NOTES:
BTSC: BROADCAST TELEVISION SYSTEMS NTSC: NATIONAL TELEVISION SYSTEM COMMITTEE.
COMMITTEE. PAL: PHASE-ALTERNATING LINE.
CVBS: COMPOSITE-VIDEO-BROADCAST SIGNAL. SECAM: SÉQUENTIEL COULEUR AVEC MÉMOIRE.
EIA-J: ELECTRONIC INDUSTRIES SIF: SOUND INTERMEDIATE FREQUENCY.
ASSOCIATION OF JAPAN. VBI: VERTICAL-BLANKING INTERVAL.
I2S: INTER-IC SOUND. VIF: VIDEO INTERFACE.
NICAM: NEAR-INSTANTANEOUS COMPANDED- YC: S VIDEO.
AUDIO MULTIPLEXED. YPBPR: GREEN/BLUE/RED.

Figure 3 An FPGA-based design provides for feature customization and is cost-


feasible for low-end- and midrange-system configurations.

ing Picture Experts Group) metadata for perfect decoding of complex still frames.
a more elegant approach. However, for real-life images, the wide
aperture of the PAL-frame comb often
COMB IMPLEMENTATIONS means that the 3-D comb will fail on
Another potentially integrated func- moving images and thereby regress to
tion is an improved comb filter. Most line-comb mode. A field comb offers a
consumer products use a 2-D comb, good compromise between memory re-
which leaves undesirable decoding arti- quirements and performance. For PAL, a
facts that also consume valuable band- field comb requires 312 lines⫻1440 pix-
width if compressed. A good 3-D comb els⫻8 bits minimum⫽3.6 Mbits. Unfor-
can noticeably improve quality, but it tunately, this capacity is still too large to
FCC, IC, CE and requires an external-memory device. enable the use of integrated memory in
Telec Certified Available 3-D-comb-IC options use a
symmetrical frame comb, which for PAL
small, cost-effective FPGAs.
However, it is possible to implement
requires four frames⫻625 lines⫻1440 a pseudo-3-D comb that fits within
pixels⫻8 or 10 bits⫽36 Mbits, thereby the memory requirements of even the
necessitating an external-memory de- smallest FPGAs. Normally, three comb
vice, usually an SDRAM. You can halve modes are available to the decoder: the
this requirement by using an asymmet- 3-D comb, a 2-D line comb, and a sim-
rical comb, which has the advantage of ple mode that is either a lowpass or a
requiring no compensating audio delay. notch filter. The decoder chooses the
You can halve it again for PAL by us- appropriate comb mode, basing its deci-
ing PAL modifiers in the comb architec- sion on signals that indicate failure con-
ture. An additional halving of memory ditions, such as motion, which prevents
budget can occur with the use of a field the 3-D comb from operating, or diago-
comb. nals, which prevent the 2-D comb from
A single-tap, 262-line comb for NTSC operating. An often-assumed priority is
or a 312-line comb for PAL gives excel- that 3-D is always the preferred mode
lent results, although it does not permit and that simple mode is the least desir-
Highest Speed, μ Power ULDO
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PSRR vs. Frequency


90
High PSRR: 65dB (1kHz), 48dB (1MHz) 80
70
Stable with 1μF output capacitor
60
C=10μF
100μA Supply Current
PSRR (dB)

50
Ultra-low dropout voltage: <90mV 40
30
Wide input voltage range: 1.0V to 5.5V 20
Adjustable VOUT range: 0.5V to 4.0V 10 VIN=1.5 V
0 VOUT=1.2V
IOUT=0.1A C=1μF
-10
0.1 1 10 100 1000 10000
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MP8801 150mV (150mA) 150mA 2.7V - 6.5V 1.25V Adj/Fixed TSOT23-5
MP8802 230mV (250mA) 250mA 2.7V - 6.5V 1.25V Adj/Fixed TSOT23-5
MP2002 290mV (500mA) 500mA 1.35V - 6.5V 0.5V Adj QFN8 (2x3)
MP89046 360mV (600mA) 600mA 2.5V - 6.5V 0.5V Adj QFN8 (2x3)
NEW MP2005 <90mV (800mA) 800mA 1.0V - 5.5V 0.5V Adj QFN8 (2x3)

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ISO9001:2001
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able mode. However, this a color-under technique for
prioritization is not always + Go to www.edn. recording. The luminance

Mountble)
true; on flat areas of color, com/ms4302 and information FM-modulates
rf ac e for example, simple mode click on Feedback onto an approximately 3.5-
Su
-H ole Availa nd is often the best mode, as Loop to post a com- MHz carrier, whereas the
(Thru sformers a measured by highest SNR ment on this article. chrominance information,
Tran nductors or least visible artifacts. The along with the luminance
I g imme
diately reason for this seeming dis-
+ For more feature
information it contains, re-
Catalo articles, go to www.
o’s full com parity is that the wide aper- modulates onto a carrier
See Pic onics.
electr
ico ture of the 3-D comb means edn.com/features.
with a frequency of approx-
w w w. p that clock jitter can leave a imately 600 kHz to avoid
residual subcarrier; just 1 nsec of clock problems recording at higher frequen-
Low Profile from jitter across an 80-msec tap distance can cies. Because of this remodulation of the

.19"ht. result in this scenario. chrominance component onto another


You can, therefore, consider a comb carrier, this approach loses the phase re-
architecture in which the 2-D and sim- lationship with the original subcarrier.
ple modes decode an image wherever It’s therefore no longer possible to comb
possible. Such an approach uses the 3-D the higher-frequency component of the
comb only when neither the simple nor signal to separate the luminance and
Audio Transformers the 2-D modes can operate. To create chrominance. The system therefore dis-
Impedance Levels 10 ohms to 250k ohms, this design, the system stores in memo- cards the higher-frequency information,
Power Levels to 3 Watts, Frequency Response
±3db 20Hz to 250Hz. All units manufactured
ry a 1-bit positional flag along with the resulting in a low-resolution image.
and tested to MIL-PRF-27. QPL Units available. frame- and field-delayed data for that Most comb filters use a complemen-
flag position. On the subsequent frame or tary-baseband comb. Composite-video
Power & EMI Inductors field, the design can then choose a 3-D- demodulation occurs using a lowpass-fil-
Ideal for noise, spike and Power Filtering
Applications in Power Supplies, DC-DC comb aperture for these positions in ad- tered, phase-locked subcarrier waveform
Converters and Switching Regulators
dition to the 2-D and simple modes. A to produce the chrominance outputs.
number of tested images, including the Combing the chrominance signals then
Pulse Transformers ubiquitous Snell and Wilcox moving- removes the luminance components;
10 Nanoseconds to 100 Microseconds. ET
Rating to 150 Volt Microsecond, Manufactured zone plate, reveal that 3-D is rarely nec- remodulating and adding chrominance
and tested to MIL-PRF-21038.
essary under these constraints. It is still produces a clean chrominance-only sig-
Multiplex Data Bus necessary to determine whether the 3-D nal, centering on and in phase with the
Pulse Transformers comb is failing. It fails, for example, if subcarrier frequency. Subtracting this sig-
Plug-In units meet the requirements substantial motion is in the image, espe- nal from the composite video produces
of QPL-MIL-PRF 21038/27.
Surface units are electrical equivilents cially if you use a frame aperture. A con- clean luminance.
of QPL-MIL-PRF 21038/27. siderably reduced memory requirement You can use a variant of this comb
is the benefit, however. architecture, wherein the remodula-
DC-DC Converter
A 1-bit plane is necessary for the 3-D tion and the subtraction from the com-
Transformers
Input voltages of 5V, 12V, 24V And 48V. comb aperture. For example, a 312-line posite source occur before the comb fil-
Standard Output Voltages to 300V (Special field comb needs 312⫻720⫽224,640 ter (Figure 2). This technique produces
voltages can be supplied). Can be used as self
saturating or linear switching applications. All bits. Also, at the flagged locations in simple chrominance components and a
units manufactured and tested to MIL-PRF-27.
which both the 2-D and the simple clean, notched luminance. Combing the
400Hz/800Hz modes fail, the design needs memory to chrominance components to produce
Power Transformers store the delayed information. Surpris- combed-chrominance outputs and then
0.4 Watts to 150 Watts. Secondary Voltages 5V ingly, this memory budget is limited to subtracting them from their simple ver-
to 300V. Units manufactured to MIL-PRF-27
Grade 5, Class S (Class V, 1550C available). just 32 kbytes and still produces substan- sions leaves you with the high-frequency-
tial improvements in the decoded im- luminance signal. Remodulating it and
age. In other words, for a large range of adding it to the notched luminance ef-
images, there are just 32,000 pixels for fectively fills in the information missing
-
Delivery eek See EEM which the 3-D comb is essential. This from the notch. The advantage of this ar-
to onew
stock or send direct combined amount of memory is avail- chitecture is the ability to add the high-
for FREE PICO Catalog able even in small FPGAs, allowing the frequency luminance to the notched lu-
Call toll free 800-431-1064 pseudo-3-D comb to operate on at least minance using a different phase of the
in NY call 914-738-1400 one decoder channel. subcarrier. Remodulating the high-fre-
Fax 914-738-8225 quency luminance, the original phase re-
PICO Electronics,Inc.
143 Sparks Ave. Pelham, N.Y. 10803
MEMORY BUDGET lationship reconstructs the original wave-
A modified comb architecture yields form with a higher bandwidth.
E Mail: info@picoelectronics.com another improvement in decoding qual- You base adjustment of the phase of
www.picoelectronics.com
ity. VCRs (videocassette recorders) use the second remodulator on information

54 EDN | SEPTEMBER 4, 2008


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you derive from a highpass filter. You can determine the cor-
rect phase for the addition of the luminance signals by de-
tecting the improved sharpness of the luminance signal for
particular subcarrier phases. This approach is possible using a
highpass filter, a square-law function to rectify the highpass-
filter output and increase the weighting to the slope of the
signals, and an accumulator to measure the amount of edge
detail in the image. Correct phase adjustment is an iterative
process, albeit a satisfactory one because the phase changes
at a slow rate. The additional phase offset adds to the subcar-
rier phase you derive from the input signal. This method can
substantially improve the perceived sharpness of any VCR
source and reduce the discrepancy between the performance
of the VCR and that of the DVD. It is ideal, for example, in
transcriptions.
Incorrect timing of luminance and chrominance is common
with some video sources, such as VCRs. Noncoincidence of
vertical edges leads to a lack of clarity in the resultant video
image, specifically with regard to smearing of vertical edges.
Many video decoders offer a YC-delay control, which allows
the user to vary the comparative delay. However, the prob-
lem with this manual-control method is that the user needs
to know the delay to be able to compensate for it, effective-
ly rendering the control redundant. Such adjustment is dif-
ficult to do visually, especially for an unskilled user, and it
requires specific video-test patterns to properly perform the
adjustment. The delay can also vary over time, especially for
mechanical mechanisms, such as VCRs. However, the FPGA
can incorporate methods not available in off-the-shelf IC de-
coders to automatically, periodically retime the luminance
and chrominance.

AUDIO APPROACHES
Audio acceptance occurs in either an SIF (sound-interme-
diate frequency) from the tuner, such as NICAM or BTSC,
or baseband stereo from the composite- or component-video
inputs. ICs demodulate and decode the SIF signal; similarly,
IP cores that perform these functions are available for FPGAs.
As mentioned, the FPGA can take advantage of different
configurations for different standards to reduce the area im-
pact, and it can incorporate additional decoders for multitun-
er products.
IC options may integrate the baseband-audio ADC with
the video decoder. However, this approach usually results in a
worse SNR than that of an external-IC alternative. However,
it is possible to also use one of the video ADCs for the audio.
By substantially oversampling the audio and then decimating
the result, you can theoretically achieve the additional need-
ed bits without using an external device, leading to further
cost savings (Figure 3).EDN

AU T H O R ’ S B I O G R A P H Y
Phuttachad Thiencharoenwong is sales director for
SingMai Electronics. Before emigrating to Canada,
she ran her own civil-engineering company, ODP
Engineering, in Thailand and Singapore and previ-
ously sold electronic components in Thailand.

56 EDN | SEPTEMBER 4, 2008


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B Y DAVID L AU TZE N H E I SE R A N D AGH A H U S S AI N • S I L I S TI X

Optimize memory-system
design for multimedia
applications
THE CONVERGENCE OF VIDEO AND COMMUNICATIONS
IN INEXPENSIVE UNIFIED-MEMORY ARCHITECTURES HAS
MADE DRAM THE MOST IMPORTANT AND THE HIGHEST-
PERFORMANCE TARGET IN ANY SYSTEM.

RAM efficiency has become a severe challenge system functions that use DRAM, as well as interactions with

D
for video-processing-SOC (system-on-chip) de- the controller logic that manages DRAM operation.
signers. This evolution is the result of many fac- Figure 1 shows how the key processing functions that supply
tors. Continued advances in process technology and manipulate DRAM data communicate with the DRAM
have enabled higher integration levels. Domi- controller. In traditional SOCs, this communications network
nant consumer-pricing pressures have replaced is usually a hierarchy of clock-based, processor-oriented bus-
higher-margin communications infrastructure and high-end es. In more modern SOC architectures, the interconnect is a
computing as the market drivers. In the consumer markets, separate system for managing traffic, using architectures such
the adoption of much-higher-bandwidth-consuming stan- as a synchronous-star crossbar, clock-based NOC (network on
dards, such as HD (high-definition) video, in consumer equip- chip) or a clockless, asynchronous NOC.
ment has created enormous bandwidth requirements. At the High DRAM efficiency is important for multimedia pro-
same time, however, low-cost chip-to-chip bandwidth gener- cessing, particularly for devices that process HD data streams.
ally lags behind the on-chip speed increases that on-chip pro- A number of factors affect the efficiency of this processing.
cess technology and architectural advances enable. Though these factors vary from system to system, you need to
All of these pressures eventually focus on the SOC-to- carefully consider them when developing the architecture of a
DRAM interface. With the convergence of video and com- multimedia system.
munications in inexpensive unified-memory architectures, The DRAM controller needs maximum visibility of the IP
DRAM has become the most important and the highest-per- (intellectual-property) core making a request. The controller
formance target in any system. cannot always infer the needed information from the request:
As SOCs have integrated more functions on a single chip, The system must explicitly communicate the information to
the additional cost along with the loss of digital-logic perform- the controller, allowing the controller to determine the im-
ance associated with integrating DRAM on that chip has portance of the new request relative to other requests already
forced consumer-multimedia-device manufacturers to employ under way.
DRAM as one or more separate chips. As this trend contin- In older bus-based systems, differentiation among potential
ues, it highlights the cost of the DRAM as a major component requesters was not part of the request. The controller had to
of overall system cost. To minimize system cost for a given per- infer it by some other means. For example, in AHB (advanced-
formance level, efficient use of DRAM becomes
critical. If, through intelligent SOC design, a
system can use slower and therefore lower-cost GENERAL- OTHER IP CORES
PURPOSE
DRAM or fewer DRAM devices, then that sys- CPU
tem can significantly increase its performance-
to-cost figure of merit. Consequently, in recent
VIDEO- DRAM
years, DRAM-access performance and use have PROCESSOR CONTROLLER
pushed past 50% to more than 80% in consum- DRAMs
er digital devices.
DISPLAY
CONTROLLER
MAXIMIZING DRAM EFFICIENCY OTHER IP CORES
You can increase DRAM efficiency, but only
by considering a number of complex interac-
tions in the overall system design. Key among Figure 1 Key functions in a video-processing SOC include various processor
these interactions are communication with and and controller cores, including the DRAM controller for external memory.
the information that flows between the various

SEPTEMBER 4, 2008 | EDN 59


high-performance-bus)-based systems, mul-
tiple AHBs allow the controller to prop-
erly weigh one request against another.
These multilayer systems can use various
QOS (quality-of-service) algorithms at the
DRAM controller to extract the highest ef-
ficiency from the DRAM channel and still MBURSTLENGTH
satisfy the needs of the system.
In more modern protocols, such as OCP MBLOCKSTRIDE
(Open Core Protocol) or AXI (Advanced
Extensible Interface), various fields in the MBLOCKHEIGHT
request packet identify the requester and,
potentially, the specific task from the re-
quester, using OCP tags or AXI identifiers.
Tags let the on-chip communications and
its targets reorder responses to noncon-
flicting memory addresses within a single Figure 2 A 2-D block-transfer command has, along with the data comprising multiple
thread, ensuring that the system respects same-length lines, information about the number of lines in the block and the offset
write ordering. Tagged transactions are between adjacent lines.
useful for advanced CPU architectures. To
maximize DRAM efficiency, the intercon-
nect between requester and DRAM controller must convey way can confuse the DRAM controller. A request that arrives
all possible information about the request. early and that the system does not recognize as a priority re-
Modern DRAM controllers have command queues that quest wastes storage. If the system recognizes it as a priority
hold outstanding requests from the multiple initiators a system request, then it may disturb the scheduling and reduce DRAM
might contain. To ensure that the controller has maximum efficiency. The network should be invisible to the DRAM and
flexibility in selecting command sequences and other impor- deliver requests as quickly as possible.
tant information, the controller queue should always contain The best approach is to deliver the raw state of the system
multiple requests from which to make the best scheduling de- without overwhelming the DRAM controller, so there is a
cision. For the on-chip network, there should be no barriers to single point of resolution between the state of the DRAM de-
delivering all possible requests as soon as possible, again with vices and the needs of the system. Any other approach may
the maximum information about the requests. introduce an opportunity for losing information or for parts of
One way to manage system traffic is to add traffic-shaping the system to make the wrong decisions, both of which reduce
and traffic-ordering logic to the interconnect in front of the DRAM efficiency.
DRAM controller to assist the controller in DRAM manage- In some systems, the interconnect may modify the nature
ment. However, as only the DRAM controller knows the state of the request such that when it arrives at the DRAM con-
of the DRAM devices and pending requests from other system troller, it is late for an opportune scheduling window, or it
functions, request scheduling should be the job of the DRAM may lose or subvert some aspect of the request. For example,
subsystem. Any attempt to reorder or tailor requests in any in some time-multiplexed systems, the nature of the alloca-

OCP 2.2 INTER- OCP 2.2


CONNECT DRAM
INITIATOR IP CORE INITIATOR GATEWAY GATEWAY TARGET DRAMs
OCP 2.2 FABRIC CONTROLLER
ADAPTER ADAPTER OCP 2.2

(a)

OCP 2.2 INTER- OCP 2.2


CONNECT DRAM
INITIATOR IP CORE INITIATOR GATEWAY GATEWAY TARGET DRAMs
OCP 2.2 FABRIC CONTROLLER
ADAPTER ADAPTER OCP 2.1/
AXI/
OPTIONAL NATIVE
HARDWARE
(b)

Figure 3 A 2-D block transfer using a synthesized self-timed interconnect fabric may pack MBurstSeq into IP and deliver it to a target
adapter (a) or convert MBurstSeq into multiple burst requests in optional hardware at the initiator adapter (b).

60 EDN | SEPTEMBER 4, 2008


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tion algorithms causes a large transfer to break
TABLE 1 GUIDELINES FOR MAXIMIZING DRAM EFFICIENCY
into a series of smaller transfers. At any point in
servicing one of the smaller requests, the DRAM What you need to maximize DRAM- Desired attributes of synthesized-
controller could have an opportunity to manipu- controller efficiency communication networks
late the DRAM controls to achieve additional Maximum visibility to requesting intellec- Interconnect carries source identifica-
efficiency if it knew that another, similar request tual-property core needs tion and priority if desired
was coming. Without that insight, the DRAM Controller has a large number of requests Bandwidth of interconnect is typically
controller might close a bank or allow an inter- from which to choose much greater than endpoint capability
vening read to reverse the bus state, reducing Single point of system to match state of Interconnect is completely “endpoint-
efficiency. DRAM to system needs transparent”
For many DRAM controllers, the ability to re-
Interconnect does not modify information Initiator request is delivered unaltered
order memory-access requests, even from a single
requester, is critical for efficient operation. For Requests can be reordered Adapters have a reordering capability
maximum efficiency, the SOC architecture must for endpoints that lack it
incorporate some mechanism at the target that
allows for this reordering across initiators, even if the request- a high-level, architectural description with several attributes
ing IP core does not support it. that help optimize DRAM operation.
Interconnect synthesized in this way can inherently carry
ADDRESSING DRAM-EFFICIENCY ISSUES the identification of the requesting IP core, even if the pro-
One way to deal with the need to fully inform the DRAM tocol at the requesting end does not explicitly support such
controller is to synthesize, either through a formal manual identification. For example, an AHB initiator, which does
process or using an automated tool, an interconnect struc- not have an explicit identification capability, may receive
ture you base on the requirements of the individual requester an SID (source identification) during interconnect synthe-
blocks. In this instance, think of synthesis in the general sense sis. The interconnect carries this SID from the AHB initia-
as a translation from one level of abstraction to another and tor to the DRAM controller, and the controller can then use
not in the specific sense as producing a gate-level netlist from the SID in its algorithms to maximize efficiency. For proto-
an RTL (register-transfer-level) description. Such an automat- cols such as those that have explicit identification fields, the
ed tool may synthesize self-timed interconnect networks from system may carry the ID information intact to the DRAM

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controller. If the system architect wishes to TABLE 2 IMPLEMENTATION TRADE-OFFS BETWEEN THE TWO
include additional system-level priority or TYPES OF MBURSTSEQ=BLCK COMMAND TRANSFERS
similar information about the requester, the Implementation A Implementation B
interconnect-synthesis process may provide
optional fields for this information. This situ- Pros Cons Pros Cons
ation is more desirable than dealing with bus- DRAM controller A limited set of Works with a Larger area for
es that require the chip designer to translate has maximum com- DRAM control- wider set of initiator adapter
all information into a form that the bus pro- mand information lers support DRAM controllers
MBurstSeq=BLCK
tocol can understand.
If the synthesis creates self-timed commu- Better use of Initiator adapter Easier to con- Overhead of mul-
nications networks, the bandwidth of these interconnect; less must have more struct systems tiple burst requests
overhead of multiple intelligence and with mixed over interconnect;
structures is generally much greater than that
burst commands must support a endpoints DRAM controller is
of the DRAM controller. In addition, because wider set of target “missing” informa-
of the nature of the aggregation that might oc- adapters tion about the
cur in the path to DRAM, such a system can request
deliver all possible incoming requests bound
for DRAM at maximum wire speed. This method ensures that avoid blocking or eliminate the need for large buffers to ab-
any request arrives at the DRAM controller as soon as possible sorb a large data burst at the DRAM controller. Such a modi-
and is not, for example, caught in the interconnect waiting for fication to the request stream needs to happen at the initiator
a clock edge. to match the burst sizes the target DRAM can handle. In this
In general, requests to the interconnect should be complete- approach, however, the interconnect should not be a factor
ly contiguous. The system should deliver a long, unmodified in the burst-chopping decision and should carry whatever re-
request from an initiator to the DRAM controller in whatever quest the initiator sends.
form it began. The interconnect should not modify any of the Along with the communications network, the synthesis
information. process should also generate adapters—logic that services the
In some cases, the initiator, rather than the interconnect, needs of endpoints—with optional reordering capability. This
should modify requests. For example, the system designer may approach allows a mixed system, such as one with both AHB
choose to incorporate burst chopping during a write request to and OCP initiators, to fully support reordering, allowing the

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DRAM controller to operate as efficiently as pos- + Go to www.edn. the 2-D burst request, manages the incrementing
sible. For an endpoint, such as one that uses AHB, com/ms4283 and movement from one line to the next based on the
a reordering adapter manages the order of requests, click on Feedback stride, and determines the end of the burst based
making them appear to the endpoint as always in Loop to post a com- on the height.
order, even if the DRAM controller, for efficient ment on this article. Figure 3 shows two implementations of a 2-D
operation, chooses to reorder particular requests. block transfer that are receiving support from a
+ For more feature
Table 1 summarizes these DRAM-efficiency is- self-timed interconnect fabric of the type synthe-
articles, go to www.
sues and how interconnect synthesized by a for- sized by Silistix tools. Each implementation shows
edn.com/features.
mal process can addresses them. a single path, from the initiator to the DRAM con-
troller; however, the initiator needs to access oth-
A 2-D BLOCK TRANSFER er paths in the system, including, possibly, other endpoints.
An example of a function that can improve DRAM efficien- In Figure 3a, the key system flow is between an OCP 2.2-
cy is a 2-D block transfer. This transfer is a special form of an capable initiator that can issue an MBurstSeq⫽BLCK com-
SRMD (single-request-multiple-data) command that passes mand and a similarly OCP 2.2-compliant DRAM controller
across an interface from an initiator, through the interconnect, that can directly accept the MBurstSeq⫽BLCK command.
to a receiving target. With respect to OCP, the only publicly Thus, the DRAM controller has the registers and logic to
available protocol that currently supports this capability, the store and manipulate the burst for its stride and height. In this
2-D block transfer is a special burst type, MBurstSeq⫽BLCK. implementation, the adapters at each of the critical endpoints
In addition to the starting address and length (in the case of would need to be OCP 2.2-compatible.
2-D, the length of each line), this 2-D transfer request trans- When it receives the MBurstSeq⫽BLCK burst type, the ini-
mits a height (the number of lines in the block) and a stride tiator adapter packs that request into the internal format that
(the offset from the beginning of one line to the beginning of the synthesized interconnect uses and delivers it intact with
the next) at the same time. Figure 2 shows the structure of a the additional fields to the target adapter. The target adapter
2-D block transfer as the OCP 2.2 protocol defines it. unpacks the information from the internal format and supplies
At the receiving end—typically the DRAM controller but it across the OCP 2.2 interface exactly as the initiator adapter
possibly a video display in a write-only video-processing sys- received it. As the DRAM controller supplies data, the target
tem—special hardware stores the additional information for adapter associates that data with that request and delivers it
back to service the command.
In Figure 3b, the same OCP 2.2-capable initiator makes
Super-Grip CR-2032 the request, but there is no OCP 2.2-capable DRAM control-
ler. The DRAM controller in this case might have an AXI
Battery Holders interface or an older OCP-compliant interface that does not
support the MBurstSeq⫽BLCK burst type. The controller
For Handheld and Portable Devices might also be a customer-specific core that uses a native inter-
face instead of a standard protocol. In either case, the opera-
tion of the implemented circuitry is the same.
When the initiator adapter receives an OCP 2.2 MBurst-
Seq⫽BLCK burst type, the adapter determines that the target
is not OCP 2.2-capable and stores the stride and height infor-
mation in additional hardware. The system architect would
specify this hardware during interconnect synthesis, based on
a desire to support the OCP 2.2 MBurstSeq⫽BLCK burst type
for the initiator despite not having an OCP 2.2-compliant
Special
gold-plated DRAM controller. The initiator adapter would decompose
contacts the 2-D block transfer into the proper number of convention-
In the past, CR-2032 batteries – used in portable, handheld al burst transfers and begin issuing them across the intercon-
and other devices – were often subject to battery ejection. nect to the DRAM controller. If the DRAM controller uses a
No more. MPD’s super-strong, super-grip CR-2032 battery
holder is virtually ejection-free, providing the confidence nonstandard interface, the interconnect can alert the DRAM
essential for today’s active lifestyle. controller that multiple burst requests of this type are inbound.
Key Features • Special gold-plated contacts & construction The system could also unroll 2-D bursts at the target and au-
lock the coin-cell in place • Dual beams assure contact
• Break-resistant, lightweight LCP plastic withstands high tomatically deliver them to the endpoint DRAM controller,
temperature • Shock/vibration resistant • Thru-pin and surface which has the same effect. Depending on the algorithms the
mounting • Available Tape & Reel • No tool to remove battery controller uses, this information alone may improve the effi-
For details: write, call, fax or visit our website
ciency of servicing an MBurstSeq⫽BLCK type of burst.
For systems in which the OCP 2.2-capable initiator needs
to issue 2-D block transfers to both OCP 2.2-compatible and
non-OCP 2.2-compatible endpoints, the same options apply.
The initiator adapter should be able to identify, from the na-
www.batteryholders.com ture of the request and its knowledge of the endpoint types,

66 EDN | SEPTEMBER 4, 2008


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which endpoints can directly accept the 2-D block command form. The Silistix tools can generate an OSCI- or CoWare-
and which ones must use the optional hardware. This ap- compatible SystemC model of the synthesized interconnect
proach involves slightly more hardware overhead to service and a timed or an untimed version of the model for early sys-
both types with OCP 2.2 MBurstSeq⫽BLCK burst types but tem verification.
allows efficient management of mixed systems. Using 2-D block transfers improves both DRAM and network
Design teams must consider various trade-offs when evalu- efficiency; it improves network efficiency by aiding traffic flow
ating the two implementations. Table 2 shows these trade-offs on the network. These types of transfers improve the efficien-
relative to the two 2-D block transfer in Figure 3. cy of both synchronous and asynchronous, self-timed networks
For either option, it is important to model the traffic inter- but are particularly beneficial for the asynchronous variety. It is
actions relative to the DRAM controller in a more abstract possible, by examining the kinds of transfers the blocks in an
SOC require, to synthesize a network that
can enable a DRAM controller to most
efficiently mediate between the needs of
the blocks and the behavior of DRAM
PC-based Oscilloscope chips. It can happen nearly independent-
ly of the individual characteristics of the
Ideal for ATE or OEM Applications blocks and the controller, as long as the
architecture respects the separation be-
tween the processing and the transport
functions.EDN

AU T H O R S ’ B I O G R A P H I E S
David Lautzenheiser is the vice
president of marketing at Silistix.
Before joining Silistix, he was in
private practice, assisting innova-
tive small companies with com-
pany and product-strategy issues and plan-
BASE-8
TM
ning and executing company and product
launches. Previously, Lautzenheiser success-
Introductory price $2895 fully launched new companies and products
as vice president of marketing at both Son-
ics and LightSpeed Semiconductor. Lautzen-
heiser began his marketing career at Xilinx,
Easily and cost effectively integrated into your custom application. where he led the introduction of the first
FPGAs. He holds a bachelor’s degree in
Ultrasonics electrical engineering from Washington Uni-
Disk Drive Testing versity (St Louis).
Laser Optics
and many more Agha Hussain recently joined
Silistix as the company’s chief
system architect. Previously, he
Key Features
was an application architect at
• 1 digitizing channel with 8-bit vertical resolution* Sonics, working in the digital-me-
dia and wireless areas for applications such
• 500 MS/s maximum sampling rate*
as DVD, DTV, cell phones, and WiMax.
• 200 MHz bandwidth In addition, he was a co-founder and vice
• Timing synchronization with external trigger input president of hardware platforms for Net-
• Optional memory upgrades available work Utilities and worked in a variety of
roles at Integrated Device Technology. His
• Programming-free operation with GageScope® oscilloscope software
interests and experience include synthesis,
• SDKs available for LabVIEW, MATLAB, C/C# and more timing and performance analysis, chip in-
• Custom on-board eXpertTM (FPGA) signal processing functionality available terconnect, DDR memory, and silicon-bus
*Higher channel counts, sampling rates and AWG available
protocols. Hussain has a bachelor’s degree
from Nardirshaw Edulji Dinshaw Universi-
ty of Engineering and Technology (Karachi,
Pakistan) and a master’s degree in engineer-
www.gage-applied.com/BASE-8 ing from the University of Southern Califor-
1-800-567-GAGE nia (Los Angeles).

68 EDN | SEPTEMBER 4, 2008


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NMTECHNOLOGYINDEVICESSHIPPINGTODAY

'ETSTARTEDONYOUR6IRTEX DESIGN6ISITwww.xilinx.com/iseFORAFREEDAYEVALUATION
OFANY)3%®$ESIGN3UITEPRODUCT

www.xilinx.com/virtex5

©2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc.The PowerPC name and logo are registered trademarks of IBM Corp. and used under license.
All other trademarks are the property of their respective owners
Ohm’s Law Still Applies
VOUT = ISET x R

• Outputs May Be Paralleled for • Output Adjustable to 0V • Stable with 2.2μF Ceramic Output Capacitor
Higher Current and Heat Spreading • Wide Input Voltage Range: 1.2V to 36V • Minimum Load Current: 0.5mA
• Output Current Up to 1.1A (LT3080) • Low Dropout Voltage: 300mV • Current Limit with Foldback and
• Single Resistor Programs Output Voltage • <1mV Load Regulation Overtemperature Protected
• 1% ISET Accuracy • <0.001%/ V Line Regulation

Our LDOs Work Down to 0V


®
Our expanding LT 308x family of next-generation linear regulators is an excellent choice for modern circuit designs. Their
outputs are adjustable with a single resistor down to 0V. Devices can be easily paralleled for higher output current or to
spread the heat. In addition, they provide high accuracy outputs, fast transient response, overcurrent and temperature
protection and low output noise across the 10Hz to 100kHz range.

LT308x Family Easily Paralleled for Heat Spreading Info & Free Samples

Part No. IOUT Package www.linear.com/308x


1-800-4-LINEAR
MSOP-8E,
LT3080/-1 1.1A 3x3 DFN-8,
TO-220,
SOT-223-3

LT3085 500mA MSOP-8E,


2x3 DFN-6
3x3 DFN-8,
LT3082* 200mA SOT23-8,
SOT-223
* Future Product. Contact Linear Technology Marketing for
more information. , LTC, LT and LTM are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of
their respective owners.
EDITED BY MARTIN ROWE

designideas
AND FRAN GRANVILLE

READERS SOLVE DESIGN PROBLEMS

Platinum-RTD-based circuit D Is Inside


provides high performance 72 Proportional-ac-power
controller doles out whole cycles
with few components of ac line
78 Extend monolithic program-
Jordan Dimitrov, Toronto, ON, Canada mable-resistor-adjustment range
The standard way of using an additional current to the sensor that with active negative resistance
 RTD (resistance-temperature- relates to the temperature you are mea- 78 1-Wire network controls remote
detector) sensor is to include it in a suring. With proper design, the circuit SPI peripherals
bridge followed by a differential am- can provide good linearity and stabil-
plifier. The problem is that two non- ity over a wide range of input tempera- 왘What are your design problems
linearities—one from the sensor and tures. The output voltage, VO, depends and solutions? Publish them here
another from the bridge—affect the on circuit components in the follow- and receive $150! Send your
transfer function. Some approaches ing way: Design Ideas to edndesignideas@
are available that attempt to avoid the Y reedbusiness.com.
problem, but they tend to be bulky and VO = VREF × 1 ×
Y2 왘To see all of EDN's Design
expensive (references 1, 2, and 3).
R Θ (Y0 + Y2ⳮY3ⳮY Y4 )ⳮ1 Ideas, visit www.edn.com/design
An alternative circuit proposes add- , ideas.
ing only one extra resistor to the dif- R Θ [ Y1 + Y3ⳮR 2Y4 (Y0 + Y1)] + 1
ferential amplifier but provides neither
design guidelines nor results (Refer- where YI⫽1/RI and I=0 to 4. in the first and doing some rearrange-
ence 4). This Design Idea fills the gap. For positive temperatures, a second- ments, you get:
Although circuit analysis is somewhat degree polynomial of the following form ΘⳮB
complex, performance is good, and the can approximate RTD characteristics: V0 = 2 × K × Θ = f (Θ)KΘ,
Θ ⳮBΘⳮC
circuit uses few components.
R Θ = R 0 (1 + α × Θ + β × Θ2),
Besides the platinum RTD, R⍜, the where B, C, and K are constants and
circuit features only six precision resis- where R0 is sensor resistance at 0⬚C, f(⍜) is a function of temperature. Fig-
tors, an op amp, and a voltage refer- ␣ and ␤ are coefficients, and ⍜ is the ure 2 shows the general shape of f(⍜).
ence (Figure 1). R4, the extra resistor measured temperature. The output voltage depends linearly
for the differential amplifier, delivers After replacing the second equation on temperature when f(⍜) is as close
as possible to a con-
VREF stant. This situation
R2
is most true around
R1 R1 the minimum point

f(⌰) of f(⍜).
VO Some additional

␣/␤ relations provide
⌰, ⬚C
that the output volt-
age is 0V at temper-
R4 ature 0⬚C, the con-
R0 R␪ R3 version coefficient
is 10 mV/⬚C, the
minimum of func-
tion f(⍜) is in the
Figure 1 This generic RTD circuit needs few Figure 2 The general shape of function f(⍜)
middle of the mea-
components. varies with temperature.
surement span, and

SEPTEMBER 4, 2008 | EDN 71


designideas
the current through R⍜ causes adjustment at 550⬚C to match
TABLE 1 EXPERIMENTAL RESULTS
negligible self-heating of the the magnitudes of the posi-
sensor. Measurement range ⳮ100 to ⫹600°C tive and the negative errors.
Figure 3 shows the circuit Nominal sensitivity 10 mV/°C You can also extend the tem-
that meets these requirements. Basic accuracy (nonlinearity) Well below ⫾1°C perature range to start from
The sensor is a DIN-IEC 751 ⫺100⬚C instead of 0⬚C with-
Ambient-temperature effect 0.05°C/10°C
platinum RTD. Microsoft (www. out exceeding the basic non-
microsoft.com) Excel software Power-supply effect 0.1°C/V linearity. The three-lead con-
fits 13 points of 0 to 600⬚C in Cable effect (three-lead connection) 0.7°C/⍀ nection to the sensor signifi-
steps of 50⬚ from the RTD’s cal- Power-supply range ⫾12 to ⫾18V
cantly reduces the influence of
ibration table. The spreadsheet connection-cable resistance,
software determined R0 to have Consumption (600°C input) 9 and ⳮ3 mA RC, on accuracy.
a value of 100⍀, ␣ to have a Operating temperature ⳮ40 to ⫹85°C Table 1 shows the results of
value of 3.908⫻10⫺3⬚C⫺1, and evaluating this circuit’s per-
␤ to have a value of ⫺5.801⫻10⫺7⬚C⫺2 coefficient is 50 ppm/⬚C. You can use formance with a calibrated, precision-
with an R2 factor of one. two trimming potentiometers, VR1 and decade resistance and a calibrated,
All the circuit’s resistors have toler- VR2, to independently adjust zero and 4.5-digit multimeter with readings
ances of 0.02%, and the temperature span readings. You should perform span at ambient temperatures of 24 and
68⬚C; power supplies of ⫾12, ⫾15,
VR1 R2
2.46k
and ⫾18V; and cable resistances of 0
100
15V and 5⍀.EDN
15V
2 R1
6
R1 R E FE R E NCE S
10k 10k

1 Bryant, James, Walt Jung, and
REF01H VR2
5
100k OP07C
Walter Kester, Op Amp Applications,
R0 VO
100 ⫹
Analog Devices, 2002.
4 2 Villanucci, Robert S, “Design an

RTD interface with a spreadsheet,”


RC RC ⳮ15V
RC EDN, Feb 7, 2008, pg 57, www.edn.
com/article/CA6526816.
R4
R3 3 Moghimi, Riza, “Low-error platinum
R␪ 28.4k
2.67k
RTD circuit has shutdown capability,”
EDN, Sept 14, 2000, pg 186, www.
edn.com/article/CA47186.
Figure 3 The full circuit needs trimming potentiometers VR1 and VR2 to adjust 4 Gutnikov, VS, Integrated Electron-
zero and span, respectively, and a three-lead cable for sensor connection. ics in Measuring Devices, Leningrad,
RC is the cable’s resistance. 1980.

al manner is neither easy nor simple.


Proportional-ac-power controller This Design Idea borrows from the
delta-sigma-modulator concept. The
doles out whole cycles of ac line controller sends cycles of the ac line
to the load as the delta-sigma modula-
Richard Rice, Oconomowoc, WI tor determines. For example, when the
In industrial and process con- greater temperature precision using input-control voltage is 15% of full-
 trol, it is often necessary to ac- proportional power control. With this scale, only 15 of 100 ac cycles arrive at
curately control the temperature of a method, the controller monitors the the load. Likewise, at 85%, 85 of 100
process. You control most heating el- temperature, proportionally varying the arrive (Figure 1). The control-voltage-
ements using the “bang-bang” meth- heater power to keep the temperature input stage, IC1A, is an inverting ampli-
od—turning the power to them on and as close as possible to the setpoint. A fier with a gain of negative one. This
off at a predetermined setpoint. The PID (proportional-integral-derivative) stage makes the control-voltage range
temperature of the heated substance control loop usually accomplishes this over the positive side of 0V. In this ex-
constantly hunts back and forth around function. Varying the ac power to the ample, the control-voltage input rang-
the setpoint. You can achieve much heating element in a linear-proportion- es from 0 to 2V full-scale. The control

72 EDN | SEPTEMBER 4, 2008


Triple LED Driver in 4mm × 5mm QFN Supports LCD
Backlights in Buck, Boost or Buck-Boost Modes and
Delivers 3000:1 PWM Dimming Ratio
Design Note 449
Hua (Walker) Bai
Introduction Integrated PMOS Drivers Improve PWM Dimming
By integrating three independent LED drivers, the LT®3496 Ratio to 3000:1
offers a highly efficient, compact and cost-effective A high PWM dimming ratio is critical in many display
solution to drive multiple LED strings. All three drivers applications, especially in high end LCD panels. Beware,
have independent on/off and PWM dimming control, and though, the definition of dimming ratio varies among
can drive different numbers or types of LEDs. High side suppliers. When comparing dimming ratios, pay close
current sensing and built-in gate drivers for PMOS LED attention to the PWM dimming frequency and linearity
disconnect allow the LT3496 to operate in buck, boost, of the LED average current at different PWM duty cycles.
SEPIC or buck-boost modes with up to 3000:1 True Color For instance, the LT3496’s high 3000:1 PWM dimming
PWM™ dimming ratio. ratio can be achieved at a 100Hz PWM frequency—high
The LT3496 is offered in a single 4mm × 5mm QFN or enough to keep the display flicker-free over the entire
FE28 package. The efficiency of each driver can exceed dimming range.
95%. L, LT, LTC and LTM are registered trademarks and True Color PWM is a trademark of
Linear Technology Corporation. All other trademarks are the property of their respective
owners.

PVIN
12V C1
L1 1μF L2 L3
15μH 50V 15μH 15μH
PVIN
C1 TO C3
42V MAX CAP1 CAP2 CAP3 1μF
200mΩ 200mΩ 200mΩ s3 D1 D2 D3
LED1 LED2 LED3 C2 CAP1 C3 CAP2 C4 CAP3
1μF 1μF 1μF
TG1 M1 TG2 M2 M3 TG3 50V 0.5Ω 50V 0.5Ω 50V 0.5Ω

LED1 LED2 LED3

0.5A 0.5A 0.5A TG1 M1 TG2 M2 TG3 M3


C4 C5 C6
0.47μF 0.47μF 0.47μF
7.15M 7.15M 7.15M
7 LEDs 200mA 7 LEDs 200mA 7 LEDs 200mA
L1 L2 L3 OVP1 OVP2 OVP3
10μH D1 D2 10μH 10μH D3
191k 191k 191k

SW1 SW2 SW3 TG1-3 SW1 SW2 SW3 TG1-3


VIN CAP1-3 OVP1-3 CAP1-3 OVP1-3
LED1-3 VC1-3 VIN
3.3V OR 5V LT3496 3.3V OR 5V LED1-3 VC1-3
VIN VREF LT3496
22k VIN VREF 18.2k
PWM1-3 PWM1-3 FADJ PWM1-3 PWM1-3 FADJ
SHDN SHDN GND CTRL1-3 470pF SHDN SHDN GND CTRL1-3 1nF
C7, 1μF C5
DN449 F01 DN449 F02
1μF
C1-C3, C7: MURATA GRM31MR71H105KA88 L1-L3: TAIYO YUDEN NP04SZB 100M 6.3V C1: TAIYO YUDEN UMK325BJ105MH L1-L3: SUMIDA CDRH3D14/HP-150
C4-C6: MURATA GRM188R71C474KA88 M1-M3: ZETEX ZXMP6A13F C2-C4: MURATA GRM21BR71H105K M1-M3: ZETEX ZXMP6A13F
D1-D3: DIODES DFLS160 D1-D3: ROHM RB160M-60

Figure 1. Triple Buck Mode Can Drive 3x 500mA LED Strings Figure 2. Triple Boost Mode Can Drive 200mA LEDs

09/08/449
Buck Mode Circuit Drives Three 500mA LED Strings Buck-Boost Mode Circuit Survives Load Dump Events
Figure 1 shows a triple buck mode LED driver. Each chan- In automotive applications, load dump is a condition un-
nel drives 500mA of current to its LEDs. Each string can der which an IC is expected to experience 40V transient.
have from eight to twelve LEDs, depending on type. The In such applications, the LED string voltage often falls
2.1MHz switching frequency minimizes the solution size in the middle of the 8V to 40V input supply range, thus
by allowing the use of low profile inductors and capaci- requiring buck-boost mode.
tors. The overall size of the circuit is less than 16mm ×
In a buck-boost circuit, the switch voltage is the sum of
16mm, with a maximum height of 1.5mm.
the input voltage and the LED voltage. Therefore, it is
Efficiency can be above 95% for a LT3496 buck mode necessary to turn off the internal power switch before
driver. A further reduction in the parts count is possible the input voltage gets too high. The LT3496 circuit in
by removing M1, M2 and M3. However, the dimming ratio Figure 4 drives four LEDs, at 200mA per channel. The
drops without those MOSFETs. To improve the efficiency, circuit monitors the Schottky diodes’ cathode voltage
the VIN pin should be biased from a 3.3V or 5V supply. (VSC). The OVP logic turns off the main switch when VSC
Energy to the LEDs is supplied by PVIN. OVP protection is above 38V, preventing the switch voltage from rising
is omitted in Figure 1. further. Since no IC pin experiences absolute maximum
voltage, the circuit survives the load dump event.
Boost Mode Circuit Drives Three 200mA LED Strings
Figure 2 shows a triple boost mode driver that delivers Conclusion
200mA to each LED string from a regulated 12V. Figure 3 Multiple output LED drivers, such as the LT3496, offer
shows the superior PWM dimming performance of the excellent current matching, efficiency and space sav-
circuit. The LED current reaches a programmed 200mA ings. The flexibility to operate in buck, boost or buck-
in less than 500ns. The efficiency of this circuit is 90% boost mode makes the LT3496 feasible in many rugged
at a 2.1MHz switching frequency. Unlike the buck mode applications.
driver, the boost mode and buck-boost mode drivers
always require an OVP circuit at the output for open LED PVIN, 8V TO 16V
protection. 40V TRANSIENT

C1
1μF TG1 M1 TG2 M2 TG3 M3
50V L1 L2 L3
7.15M 7.15M 7.15M
15μH 15μH 15μH
PWM LED1 OVP1 LED2 OVP2 LED3 OVP3
5V/DIV 0.5Ω 191k 0.5Ω 0.5Ω
191k 191k
(100Hz)
CAP1 CAP2 CAP3

IL
200mA 4 LEDs 200mA 4 LEDs 200mA 4 LEDs
500mA/DIV

ILED D1 D2 D3
VSC VSC VSC
200mA/DIV
C3 C5 C7
DN449 F03
2.2μF 2.2μF 2.2μF
0.5μs/DIV PVIN 25V PVIN 25V PVIN 25V
SW1 SW2 SW3 TG1-3
Figure 3. Achieving Greater Than 3000:1 PWM VIN CAP1-3 OVP1-3
3.3V OR 5V LED1-3 VC1-3
Dimming Ratio with a PMOS Disconnect VIN
LT3496
VREF 18.2Ω
PWM PWM1-3 FADJ
SHDN SHDN GND CTRL1-3
C8 1nF
1μF
6.3V
C1: TAIYO YUDEN UMK325BJ105MH L1-L3: SUMIDA CDRH3D14/HP-150
C3, C5, C7: TAIYO YUDEN TMK212BJ225MG M1-M3: ZETEX ZXMP6A13F
D1-D3: ROHM RB160M-60TR DN449 F04

Figure 4. Triple Buck-Boost Mode Can Drive


200mA LEDs While Surviving Load Dump

Data Sheet Download


www.linear.com For applications help,
call (408) 432-1900, Ext. 2759

dn449 LT/TP 0908 246K • PRINTED IN THE USA


Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 O FAX: (408) 434-0507 O www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008
One Supervisor Monitors All

27 Pin-Selectable Thresholds, Pushbutton Input, Adjustable Watchdog & Reset Timers


Your preferred parts list just got a lot shorter. The versatile LTC®2917 single voltage supervisor family uses three tri-state
voltage select pins to choose up to 27 selectable thresholds from 0.5V to 12V or higher. It’s no longer necessary to qualify
and stock a different supervisor for every voltage rail. With ±1.5% threshold accuracy, operation up to +125°C, a 6.2V shunt
regulator for high-voltage operation, and low 30μA supply current, one supervisor truly monitors all.

Pin- and Resistor-Selectable Voltage Supervisors Info & Free Samples

Part No.
Voltages Threshold
Features Package (mm)
www.linear.com/2917
Monitored Selection

LTC2915 1 Pin-Selectable
27 Pin-Selectable Thresholds, Pin-Selectable
TSOT23-8, 3 x 2 DFN-8 1-800-4-LINEAR
Tolerance: 5%, 10% or 15%
Pushbutton Input, 5% Tolerance,
LTC2916 1 Pin-Selectable 9 Pin-Selectable Thresholds TSOT23-8, 3 x 2 DFN-8
Watchdog, 27 Pin-Selectable Thresholds,
LTC2917 1 Pin-Selectable Pin-Selectable Tolerance: 5%, 10% or 15% MSOP-10, 3 x 2 DFN-10
Watchdog, Pushbutton Input, 5% Tolerance,
LTC2918 1 Pin-Selectable MSOP-10, 3 x 2 DFN-10
9 Pin-Selectable Thresholds Telecom,
LTC2904/LTC2905 2 Pin-Selectable
27 Pin-Selectable Thresholds, Pin-Selectable
TSOT23-8, 3 x 2 DFN-8 Datacom and
Tolerance: 5%, 10% or 15%
Industrial Brochure
LTC2909 3 3 Resistors Undervoltage/Overvoltage Monitor TSOT23-8, 3 x 2 DFN-8

LTC2900/LTC2901/ 4 2 Resistors
Watchdog, Individual Supply Comparator Outputs, MSOP-10, 3 x 3 DFN-10/
LTC2902 Pin-Selectable Tolerance: 5%, 7.5%, 10% or 12.5% SSOP-16 www.linear.com/48vsolutions
LTC2908 6 2 Resistors 2 to 5 Adjustable Inputs, Tiny Package TSOT23-8, 3 x 2 DFN-8
Pushbutton Input, Watchdog, Individual Supply
LTC2930/LTC2931 6 2 Resistors Comparator Outputs, Pin-Selectable Tolerance: 3 x 3 DFN-12/TSSOP-20
LTC2932 5%, 7.5%, 10% or 12.5%
, LTC, LT and LTM are registered trademarks and μModule is a
LTC2910 8 2 Resistors 8 Adjustable Inputs SSOP-16, 5 x 3 DFN-16 trademark of Linear Technology Corporation. All other trademarks
are the property of their respective owners.
designideas

LINE 1
R6 VCC
TO AC LOAD
249k
R2 (HEATER)
100k VCC
C1
R11
R1 0.22 ␮F R8 R23 R12 R13
100k 180
100k 390 180 180
VIN R4 1 6
⫺ R9
IC1A 100k R7 LED1
⫺ IC 1k
CONTROL VOLTAGE ½TL072 100 2 4
1B 3 ⫹ SCR1
0 TO 2V ⫹ ½TL072 C2
IC2A 1 2 5 IC4 0.1 ␮F
OP AMP ⫹ VCC D1 Q1 R10
R3 ½LM319W MOC3011 250V
R5 6 100
49.9k OP AMP 4 IC3A Q1
VCC 71.5k ⫺ COMPARATOR Q1
R18 2 74HCT74 2N3906
R17 1k D FLIP-FLOP LINE 2
100k VCC 1
R15 R1
100k 4
R14 S1 C1
1k 8 ⫹ 3
IC2B 6 60-Hz CLOCK
R16 ½LM319W
4.7k 9 COMPARATOR
⫺ 7
VCC
5V

IN IC4 OUT
LM317
16V AC +
LINE 1 C3 ADJ R20 +
CT 470 ␮F C4 C5
500 mA R19 243 33 ␮F 0.1 ␮F
750
T1 8V AC D2 D3
R21
120V AC 750
+ +
C6 C7 C8
D1 D4 220 ␮F R22 33 ␮F 0.1 ␮F
8V AC ADJ 243
IN IC5 OUT
LINE 2 LM337
VEE
⫺5V

Figure 1 This ac controller borrows from a sigma-delta converter to output a number of whole cycles of ac-line power according
to an input-control voltage.

voltage’s input impedance is 100 k⍀. PNP transistor Q1 and optoisolated IC2B switches high during the positive
The next stage, IC1B, is an integrator. SCR (silicon-controlled rectifier) IC4 half-cycles of the ac line and low during
The integrator output ramps either up drive load-switching SCR1 into con- the negative half-cycles. Resistor R15
or down depending on the polarity of duction whenever the flip-flop provides provides a small positive bias, causing
the input current. The speed at which feedback current to the integrator. In- the edges of the 60-Hz clock to occur
it ramps depends on the magnitude of dicator LED1 lights when the load SCR slightly early—which is better than late
the input current. The integrator is the is on. The secondary of transformer in this case. If you turn off the SCR too
heart of the delta-sigma modulator. It T1 detects the zero crossings of the ac- late, its self-latching nature may cause it
forces a balance, on the average, be- power line; these crossings provide the to stay on for an extra half-cycle when
tween the control-voltage current in 60-Hz clock. The output of comparator it should have been off.
R4 and the feedback current in R6. In Both comparators IC2A and IC2B use
other words, the duty cycle of the out- a small amount of hysteresis to promote
put of IC3A, a CMOS D-type flip-flop, IF YOU TURN OFF fast, clean switching. The remaining
must match the control-voltage per- THE SCR TOO LATE, components generate the regulated 5
centage of full-scale. and ⫺5V power supplies. Transformer
Comparator IC2A detects whether
ITS SELF-LATCHING T1 and optoisolator IC4 provide isola-
the integrator’s output is positive, thus NATURE MAY CAUSE tion from the ac-power line.
requiring more feedback current, or This Design Idea works well for an
negative, thus requiring less feedback
IT TO STAY ON FOR application such as a spa-heater control
to maintain the balance. The output AN EXTRA HALF-CYCLE but does not work for light-dimming or
of the comparator switches between 0 WHEN IT SHOULD motor-speed control because the out-
and 5V. The flip-flop latches the com- put power is pulsating in nature. You
parator’s decision on the next rising HAVE BEEN OFF. can easily adapt the design for 240V-ac
edge of the 60-Hz clock. or 50-Hz operation.EDN

76 EDN | SEPTEMBER 4, 2008


Industry’s first RS-485 transceivers
RSRO
YEGAIN EE IN
F
G with an LDO and AutoDirection
EN
ESS
SUCC

LDO provides isolated power for optocouplers,


AutoDirection eliminates third optocoupler

VREG
VSYS UNREGULATED ISOLATED
POWER SUPPLY

+ VCC
RO
LDO 8
1 R

RE B
MCU AND
RELATED 2 7
DETECT
CIRCUITRY
CIRCUIT
VREG A
3 6

VSYS DI GND
4 D 5

MAX13412E/MAX13413E

UʘÌi}À>Ìi`Ê "Ê>œÜÃÊ܈`i]ÊÈ6Ê̜ÊÓn6Ê
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6 to 28   1.49
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†1000-up recommended resale. Prices provided are for design guidance and are FOB USA. International prices will differ due to local duties, taxes, and exchange rates. Not all packages are
offered in 1k increments, and some may require minimum order quantities.

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www.maxim-ic.com/shop www.avnet.com www.maxim-ic.com/MAX13412E-info


For free samples or technical support, visit our website or call 1-800-998-8800.
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. © 2008 Maxim Integrated Products, Inc. All rights reserved.
designideas
Extend monolithic programmable- devices, unlike humble mechanical
potentiometers, have relatively large
resistor-adjustment range minimum programmable resistance.
Although you can adjust a typical
with active negative resistance trimming potentiometer down to a
fraction of 1⍀, solid-state-potentiom-
W Stephen Woodward, Chapel Hill, NC eter substitutes usually bottom out at
A variety of solid-state, in-cir- eter. These replacements have many 10s, 100s, or even 1000s of ohms. This
 cuit-programmable replace- obvious advantages, such as auto- limitation can sometimes be problem-
ments exist for the traditional elec- matic adjustability, miniaturization, atic and frequently precludes use of
tromechanical trimmer potentiom- and immunity to vibration. But these the solid-state option in some design
applications.
HGND R1ADJ The Rejustor family of devices, which
Microbridge (www.mbridgetech.com)
e
recently introduced, provides an ex-
I ⳮI
REFFECTIVE = R1 R R1 RF treme example of this effect. You can
RⳮRC =RⳮRM. program a typical Rejustor over only
V a narrow span of 30%. For example,
VC ⳮ
you can program a 10-k⍀ Rejustor to
RM=MINIMUM VMⳮVC=0, no lower than 7 k⍀, imposing a seri-

PROGRAMMED IF RC=RM. ous and obvious obstacle to general-
RESISTANCE. RF
purpose application of these devices.
ⳮIC Figure 1 suggests a generally appli-
VC=IC⫻RC. RC cable workaround that works not only
with Rejustors, but also with all adjust-
VREF able resistances. It uses an op amp in
a negative-resistance topology that, in
Figure 1 This circuit uses an op amp in a negative-resistance topology that, effect, subtracts RMIN (minimum pro-
in effect, subtracts the minimum programmable resistance from the total grammable resistance) from the total
programmed resistance. programmed resistance.EDN

1-Wire network controls


output accordingly. If the current da-
remote SPI peripherals ta bit is the same as the previous bit,
toggle IC3’s Data 0 output. The circuit
Michael Petersen, Maxim Integrated Products, Colorado Springs, CO
automatically generates a clock pulse
Many 1-Wire-compatible pe- exclusive-OR gates, creates CLK. each time and requires only one 1-Wire
 ripherals are available, but, for The edge detector and one-shot command for each data bit sent. When
those that lack the 1-Wire capability, IC4A, IC4B, and IC4C combine the out- data transmission is complete, send a
the circuit in Figure 1, pg 80, illus- puts of IC2 and IC3—Data 1 and Da- final 1-Wire command to set the IC1
trates one way to implement it. The ta 0—to create a clock signal for the output high.
example controls a remote LED display SPI. This one-shot clock-generation This circuit allows a 1-Wire network
by the 1-Wire network through an SPI circuit improves the data rate by re- to control a remote temperature dis-
(serial-peripheral-interface)-compat- quiring only a single 1-Wire transac- play, but similar techniques can pro-
ible display controller. tion per SPI bit, instead of the three vide an interface to I2C (inter-inte-
To produce the three-wire SPI that transactions—data, clock low, and grated-circuit)-compatible devices and
a MAX7221 display controller re- clock high—that would be necessary to other SPI peripherals, such as ADCs
quires for the CS (chip-select), DIN if you directly use the IC3 output as a and DACs. You can also produce a bi-
(serial-data), and CLK (clock) signals, clock signal. directional-data capability by adding
the 1-Wire network serially addresses To transmit data to the SPI inputs, a fourth DS2405. Note that the SPI
three DS2405 1-Wire switches. The first set the output of IC1 low. Then, data rate and updates to the peripheral
first switch directly creates CS; the transmit the data bits using the follow- are relatively slow, but speed is not an
second switch directly creates DIN; ing rules: If the current data bit differs issue for many remote-monitoring ap-
and the third switch, aided by three from the previous bit, set IC2’s Data 1 plications.EDN

78 EDN | SEPTEMBER 4, 2008


Is your design
copy-proof?
F
RSRO
YEGAIN G
EE IN
EN
ESS
SUCC

Protect your R&D investment with a proven, low-cost* authentication solution. Options range from
customization of the 64-bit factory-lasered serial numbers to secure crypto-strong FIPS 180-1/2 and ISO/IEC
10118-3 SHA-1 based challenge and response for bidirectional authentication.

Printer
toner/ink Secure Consumer
electronics
cartridges
IC
solutions
for
Medical instrument
probes/sensors
UÊ-ÞÃÌi“ÊVœ«ÞÊ«ÀœÌiV̈œ˜
Configuration
UÊ7É-7ʏˆVi˜Ãiʓ>˜>}i“i˜Ì bitstream
For a tutorial on
FPGA protection
UÊ/>“«iÀ«ÀœœvÊvi>ÌÕÀiÊÃiÌ̈˜}à www.maxim-ic :
.com/FPGA

UÊ->viÌÞɵÕ>ˆÌÞÊ>ÃÃÕÀ>˜Vi

Communications
equipment
m
Maximu on
enti c a ti
auth on
prote c ti

Maxim’s authentication solutions—the key to copy-proofing applications


Part Description Interface Authentication Feature
DS28CN01** 1kb EEPROM with SHA-1 I2C/SMBus™ Bidirectional SHA-1 challenge and response
DS28E01-100** 1kb EEPROM with SHA-1 1-Wire® Bidirectional SHA-1 challenge and response
DS2401/DS2411 64-bit ROM serial number 1-Wire Customized 64-bit ROM
DS28CM00 64-bit ROM serial number I2C/SMBus Customized 64-bit ROM
DS2431 1kb EEPROM 1-Wire Customized 64-bit ROM, WP/OTP modes
DS2460** SHA-1 coprocessor I 2C Secure storage of system secrets
SMBus is a trademark of Intel Corporation.
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
*Authentication solutions starting as low as $0.15 for consumer-electronics volumes. Prices provided are for design guidance and are FOB USA. International prices will differ due to local duties,
taxes, and exchange rates. Not all packages are offered in 1k increments, and some may require minimum order quantities.
**Data sheet provided under NDA.

DIRECT ™

www.maxim-ic.com/shop www.avnet.com www.maxim-ic.com/Protect


For free samples or technical support, visit our website or call 1-800-998-8800.
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. © 2008 Maxim Integrated Products, Inc. All rights reserved.
designideas
5V

R1 R2 R3 IC4C
4.7k 4.7k 4.7k IC4B
DATA 0 IC4A
DATA 1 R4 74HCT86
74HCT86
CS 74HCT86 100

PIO PIO PIO


C1
IC1 IC2 IC3
0.01 ␮F
DS2405 DS2405 DS2405
DATA DATA DATA
GND GND GND
1-WIRE

5V DIGITS
DIGIT ZERO ONE TO SIX DIGIT SEVEN
CS DIN CLK SEG A
V+
SEG B
R5
SEG C
ISET IC5 SEG D
MAX7221 SEG E
SEG F
SEG G
SEG DP
GND GND DIG 7 DIG 6 . . . DIG 1 DIG 0

Figure 1 Three 1-Wire switches—IC1, IC2, IC3; three XOR gates, IC4; and the associated components enable a 1-Wire
network to control this display through the SPI peripheral IC5.

a leap ahead
in linear magnetic encoders
plug & play
Linear and Off-axis
Magnetic Encoder ICss
High resolution
25μm – AS5304
15μm – AS5306

High speed
20m/s – AS5304
12m/s – AS5306

Optical encoder compatible


user interface

West Coast (408) 345-1790 · East Coast (919)


919) 676-5292
www.austriamicrosystems.com

80 EDN | SEPTEMBER 4, 2008


Ultra-low-power 12-/10-/8-bit
RSRO
F
ADCs run on two AA batteries*
for 1.8 years at 100ksps
YEGAIN EE IN
G
EN
ESS
SUCC

400
-μMAX
1ä 350

MAX SAMPLE RATE (ksps)


300

m 250
m Ý xm
3

T F
1ä- 200

150

m 100
m Ý 3m
3

50

0
8 10 12 1.6V to 3.6V supply
RESOLUTION (BITS) UÊÇxäμÊ>ÌÊ{ääŽÃ«Ã
VDD UÊÈÓÇμÊ>ÌÊÎääŽÃ«Ã
UÊÓ£äμÊ>ÌÊ£ääŽÃ«Ã
+

UÊ£ä˜Ê>ÌÊ- Ê

AA
AA

/9*
Ê/7"ÊÊ -
, Ê
1,6 LOGIC SCLK

/Ê£ääŽÃ«ÃÊ­Ó£äμ®]ʳÓxn

3.0
1.6V OPERATION—
2.8 13 TIMES LONGER AIN+/AIN0
2.7
2.6 RUNTIME T/H
12-/10-/8-BIT
DOUT
-*TM‡É+-*TM-/
THAN COMPETITIVE
AIN-/AIN1
SAR 
,"7, TM‡É -*‡
2.4
compatible
VOLTS

2.7V ADCs
2.7V
2.2 ÃiÀˆ>Êˆ˜ÌiÀv>Vi
2.0 REF
1.8 ÝÌiÀ˜>
GND ÀiviÀi˜Viʈ˜«ÕÌ
1.6
0 100 200 300 400 500 600 700 /ܜÊȘ}i‡i˜`i`ʜÀ
DAYS œ˜iÊ`ˆvviÀi˜Ìˆ>Êˆ˜«ÕÌ

t1.6V to 3.6V low-power operation tUnipolar or bipolar operation


t0 to VDD external reference input tOne differential or two single-ended inputs

Resolution No. of Speed INL DNL SINAD Price†


Part Package
(Bits) Channels (ksps) (LSB) (LSB) (dB) ($)
MAX1391/94 8 400 49 1.15
MAX1392/95 10 1 diff/2 SE 350 ±1 ±1 61 10-TDFN/μMAX® 1.81
MAX1393/96 12 300 70 2.48

*3300mAh AA alkaline battery (LR6).


SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
μMAX is a registered trademark of Maxim Integrated Products, Inc.
†1000-up recommended resale. Prices provided are for design guidance and are FOB USA. International prices will differ due to local duties, taxes, and exchange rates. Not all packages
are offered in 1k increments, and some may require minimum order quantities.

DIRECT ™

www.maxim-ic.com/shop www.avnet.com www.maxim-ic.com


For free samples or technical support, visit our website or call 1-800-998-8800.
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. © 2008 Maxim Integrated Products, Inc. All rights reserved.
productroundup PERSPECTIVE

POWER SOURCES

PADS® PCB Design Solutions


Switcher ICs allow for compact
notebook-adapter designs
 With an ultralow-profile package, the TOPSwitch-HX IC power-package
family suits use in 65W adapters for notebook computers and 20 to 100W
Turn your next PCB design
into a vision of the artist
power supplies for LCD monitors and flat-panel TVs. The switcher ICs meet Energy
Star 2.0 specifications for external adapters and target reference designs, such as the within when you use the PADS
DER-196, for a 65W notebook adapter measuring slightly larger than a standard complete PCB solution.
deck of playing cards. An L-shaped lead bend allows the vendor’s eSIP package to lie
flat against the PCB with the heat-sink pad facing up. Combining a 700V switch- If you're looking for a way to
ing-power MOSFET with controller and supervisory functions, the 2-mm-high IC reflect your true inner genius,
also provides space for a heat sink. Available in eSIP-L packages, the TIP260LN,
the TOP261LN, and the TOP262LN IC power packages suit 20 to 100W power PADS offers an easy-to-use,
levels and cost $1 (10,000). intuitive, and powerful solution
Power Integrations, www.powerint.com
to help you create your
next PCB masterpiece — at a
2W dc/dc converters er series has a pin-compatible power-up-
most affordable price. To look
feature a variety of input grade path from the vendor’s 1W NMR
series. Galvanic isolation allows you to deeper into the world around
and output voltages configure the devices to provide an iso- you, download our latest
 Aiming at isolating and convert-
ing dc-power rails, the isolated,
lated negative rail in systems having on-
ly positive rails. Requiring no external tech paper at
2W NMG single-output-dc/dc-convert- heat sink, the converter operates over www.mentor.com/rd/padspaper3
a ⫺40 to ⫹85⬚C temperature range.
The series provides either 5 or 12V in- or call 800.547.3000
put voltages; 5, 9, 12, or 15V output
voltages; a claimed 88% efficiency; and
1-kV-dc isolation voltages. Available in
19.5⫻7.5⫻10-mm SIP packages, the
NMG series costs $8 (1000).
Murata Power Solutions,
www.murata-ps.com

© 2007 Mentor Graphic Corporation. All Rights Reserved.


EFFICIENT
POWER
While the world around you goes green, CUI and V-Infinity can keep you one
step ahead of the efficiency curve. CUI offers a large selection of EISA 2007,
CEC Level IV, and Energy Star compliant external power supplies with RoHS
compliance and UL approvals. Efficient internal power supplies from V-Infinity
include compact switching regulators and open frame switching power supplies.

EMT series
switching power supply
30 W output power
interchangeable blades
ac power cord inlet
USB style series Energy Star / CEC / EISA 2007 compliant
switching power supply
insulation resistance 50 M Ohm at 500 V dc
2.5 & 5 W output power
no-load power consumption 0.5 W max.
USB type A receptacle output
universal input
Energy Star / CEC / EISA 2007 compliant
UL/cUL, CE, FCC; TUV/GS, C-Tick approvals
insulation resistance 100 M Ohm at 500 V dc
V78 series RoHS compliant
no-load power consumption 0.5 W max.
dc switching regulator
universal input
pin compatible with 78XX linear regulators AC-AC series
UL/cUL approvals
500 and 1000 mA output current models linear power supply
RoHS compliant
efficiency up to 96% 3 – 12 W output power
no need for a heatsink 6ft. cord length - custom lengths available
wide input range
VMS-160 & VMS-365 series
output voltage tolerance: ±5 % at rated load
switching power supply
thermal shutdown class 2 power supply
VMS-160: 160 W output power in a 2”x 4” footprint
low ripple and noise Energy Star / CEC / EISA 2007 compliant
and 18.2 W/in³ power density
non-isolated no-load power consumption 0.5 W max.
VMS-365: 365 W output power in a 3”x 5” footprint
short circuit protection North American wall plug
and 19 W/in³ power density
single output voltages of 5, 12, 24, and 48 V dc UL/cUL approvals
90% typical efficiency RoHS compliant
medical approvals
universal input (90 – 264 V ac)
built-in active PFC function
12 V auxiliary fan output EISA 2007- The Energy Independence and
Security Act of 2007 was passed by Congress
in December of 2007 and addresses minimum
efficiency standards for external power supplies
Energy Star- Energy Star is a joint program of manufactured on July 1, 2008 and after. This law
the US Environmental Protection Agency (EPA) stipulates the energy efficiency criteria for adapt-
and the US Department of Energy (DOE) aimed
ers in active mode depending upon their power
at preserving the environment through energy
rating. The stipulated energy consumption for
CEC Level IV- The California Energy Com- efficiency. Adapters meeting the Energy Star
guidelines are up to 30% more efficient than non- all adapters in no-load mode must be less than
mission has mandated requirements for power
supplies used with certain types of products. compliant versions and must meet both active 0.5 W according to EISA 2007. Compliance with
The most current requirements are the same and no-load minimum efficiency requirements set these requirements is mandatory.
as the EISA 2007 requirements and are forth by the EPA and DOE. Compliance with these
referred to as either “Tier 2” or “Level IV.” requirements is voluntary.

available through

V
visit: www.cui.com/efficient or www.v-infinity.com/efficient call: 800.275.4899
productroundup SIMULATE IT.
POWER SOURCES
Dual-output converters low quiescent current make it suitable in
meet military standard applications requiring continuous pow-
er-up. The family allows the use of small
704B-F ceramic output capacitors to reduce re-
 The MTC15 and MTC30 dual-
output converters join the ven-
quired board space. The MIC5313 and
15 come in 2⫻2-mm MLF-10 lead pack-
dor’s MTC series of fully encapsulated ages, and the MIC5314 and 16 come in
COTS (commercial-off-the-shelf), 4 to 2.5⫻2.5-mm MLF-12 lead packages.
35W dc/dc converters. Providing a ⫾12 Operating over a ⫺40 to +125⬚C tem-
or a ⫾15V-dc output and a 15.5 to 40V- perature range, the MIC5313/4/5/6 cost
dc input range, the converters target $1.29 (1000) each.
military and avionic platforms requir- Micrel, www.micrel.com
ing a 28V-dc in-
put. The con- The secret to successful
verters suit 10V PC-power-supply high-speed PCB design.
transients for 10 device meets
sec and 50V dc
for 1 sec, meeting 80 Plus Gold standard Simulate fast driver edges and
military standard
704B-F. They can  With 90% efficiency, the Green-
Chip PC chip set meets the Ecos
new bus technologies with
draw as much as Consulting and 80 Plus Program require- HyperLynx® – the most
80% of the out- ments for certification for a reference
widely used high-speed PCB
put power from design. The PC-power-supply reference
the positive or device features a secondary-side-con- simulation software.
the negative out- trolled-switch concept and an active-
put, as long as they do not exceed the clamp reset with an integrated switch, HyperLynx provides both
maximum output power. A feedback lowering the breakdown-voltage demand
pre- and post-layout analysis
loop constantly monitors the outputs in for the power components. The chip set
order, providing a high degree of load fits standard ATX-size boxes. Compris- of signal integrity, flight times,
regulation. The 15W MTC15 dual-out- ing the TEA1771, the TEA1781, and
put unit costs $203. the TEA1782 chips, the GreenChip PC crosstalk, multi-gigabit
XP Power, www.xppower.com chip set sells for $4 to $5. SERDES technologies and
NXP Semiconductors, www.nxp.com
EMC, and is compatible
Dual low-dropout with all major PCB design
regulators claim high DC/DC-converter series
conversion efficiency provides as much as 165W flows, including PADS.®
output-voltage tracking To find out more, download
 The low-input-voltage-capable
MIC5313/4/5/6 family integrates
two low-dropout regulators operating  Adding eight dc/dc converters to
the Senpai series, the FPMS12T
the latest hands-on
from a 1.7V input voltage at a 37-␮A and the FPLS12T nonisolated point- high-speed tutorial from
total quiescent-current consumption. of-load converters operate over a 6 to
To regulate low-voltage rails and pro- 14V-dc input bus with a 0.75 to 5.5V-dc www.mentor.com/rd/tutorial
vide improved conversion efficiency, programmable-output voltage. The con-
or call 800.547.3000.
the family’s design allows very low-drop- verters incorporate an output-voltage-
out voltages. The dual regulators supply tracking function, enabling various se-
as much as 300-mA output currents and quenced-power-up and power-down sce-
consume 37-␮A quiescent current with narios when using multiple converters.
both channels on. The device’s low qui- The FPMS12T devices deliver 55W of
escent voltage, low input voltage, and output power at a 600W/in.3 power den-

© 2006 Mentor Graphics Corporation. All Rights Reserved.


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A division of
productroundup PADS
POWER SOURCES IT’S EVERYWHERE
sity, and the FPLS12T converters deliv- mm SIP package, the FPMS12T offers 6,
er 165W of output power at a 560W/in.3 8, and 10A output-current models; the
power density. The devices feature little FPLS12T comes in a 50.8⫻13.6⫻7-mm
or no derating up to 85⬚C. An output- SIP package in 10, 16, 20, 25, and 30A
voltage-tracking function supports se- output-current models. Prices for the
quential, simultaneous, and ratiometric FPMS12T converters start at $7; prices
sequenced-start-up and -shutdown sce- for the FPLS12T series start at $11.
narios. Available in a 25.4⫻12⫻4.95- FDK Corp, www.fdk.com

INTEGRATED CIRCUITS
SOC supports range of grated dual-power monitor, a fixed 3.3V
output, or an adjustable output voltage
options for fax machines of 1.2V to the input voltage. The regu-
 Targeting use in fax machines
with ink-jet-, laser-, or thermal-
lator provides soft-start, current limiting,
and thermal shutdown, drawing a 1-mA
printing capabilities, the SX9543X current during shutdown. Claiming 93%
SOC provides direct printer control and efficiency, the device integrates a 100%
USB interfaces. Features include dual- duty cycle, extending operation in low-
voice ADCs and DACs; multiple voice dropout conditions. A pin-selectable ® ®
inputs and outputs, including a speaker peak-current limit reduces component PADS and HyperLynx
amplifier; a cross-point switch; and ad- size by adjusting inductor selection. Op- Available through Value Added Resellers
ditional ADCs for scanner and other erating over a ⫺40 to ⫹85⬚C industri-
analog-sensor inputs. Powered by a 180- al-temperature range, the regulator also
MHz, 32-bit RISC processor, the device provides 37-␮A operation when deliv- PADS resellers are full-service
includes a 120-MHz, DSP-based image ering 500-␮A output current. Available
companies that provide sales,
processor and three 288-MHz, flexible- in a 4⫻4-mm MLPQ-12 package, the
I/O processors. The I/O processors en- AS7620 dc/dc converter costs $1.36. tech support and customized
able connections to a variety of periph- austriamicrosystems,
services in your region. These
erals, such as scanners, printers, memory www.austriamicrosystems.com
cards, and LCDs. The SOC comes in an resellers are our partners; they
exposed-pad QFP-176, and prices range understand your needs and
from $7 to $15. Digital-media processor
can help you grow your
Conexant Systems, integrates video-process-
www.conexant.com business. PADS resellers provide
ing subsystem
solutions that will improve the
500-mA buck regulator  Powered by an ARM926EJ-S core
operating as fast as 270 MHz, the quality of your designs on time
provides an integrated DM335 digital-media processor inte- and within budget. Visit
grates a video-processing subsystem,
dual-power monitor enabling a 720p, high-definition video www.mentor.com/rd/buypads

 Suiting 24V utility-metering, sen-


sor-interfacing, and other industri-
display in portable-system applications.
Measuring 13⫻13⫻0.64 mm, the pro-
or call us at 800.547.3000
to find your local reseller.
al-motion-control and battery-powered- cessor comes in a BGA-329 package.
data-acquisition equipment, the AS7620 The TMS320DM335 digital-media pro-
hysteretic 32V step-down regulator pro- cessor costs $10.48. The TMDSEVM355
vides early-power-fail warning and pow- digital-video-evaluation module costs
er-good signals to microcontrollers. The $495.
500-mA buck regulator provides an inte- Texas Instruments, www.ti.com

Copyright 2005 Mentor Graphic Corporation. All Rights Reserved.


Mentor Graphics is a registered trademark of Mentor Graphics Corporation.
All other company and/or product names are the trademarks and/or
registered trademarks of their respective owners.
productroundup
INTEGRATED CIRCUITS
Logic-gate optocouplers logic-gate optocouplers meet the qualifi- free, coplanar packaging reduces pack-
cations for the UL1577 standard. The 25- age capacitance by more than 30%. The
have high bandwidth Mbps-bandwidth devices feature 13-mA FOD0710, FOD0720, and FOD0721
 Aiming at Profibus, DeviceNet,
CAN, and RS-485 industrial-com-
supply currents, 4.5 to 5.5V supply volt-
ages, and 20-kV/␮sec minimum com-
optocouplers cost $2.21, $2.44, and $2.67
(1000), respectively.
munication standards, the FOD0710, mon-mode-noise-rejection ratings. The Fairchild Semiconductor,
FOD0720, and FOD0721 high-speed vendor claims that the devices’ lead- www.fairchildsemi.com

COMPUTERS AND PERIPHERALS


Tiny, 8-Gbyte storage LCD monitor capable, providing 720p and 1080p from
DVI-D (digital-visual-interface digi-
device has gold plating connects to HDMI tal). Using HDCP, the display provides
 The 8-Gbyte STU8GPCG 24-car-
at-gold-plated storage device weighs  The MultiSync EA (enterprise-ad-
vanced) series includes the 26-in.
a 92% color gamut. The EA261WM
desktop-LCD monitor costs $679.99.
less than 4.7g. Measuring 31.3⫻12.4⫻ EA261WM desktop-LCD monitor. Fea- NEC Display Solutions,
3.4 mm, the device comes in a gold-plated tures include a WUXGA (wide-ultra- www.necdisplay.com
steel case. Available from www.newbiiz. extended-graphics array), 1920⫻1200-
com or www.newegg.com, the STU8- pixel resolution, 400-cd/m2 brightness,
GPCG storage device costs $40. a 1000-to-1 contrast ratio, a four-port Graphics cards provide
Super Talent Technology, USB hub, and a 5-msec response time. as much as 1024 Mbytes
www.supertalent.com Using an adapter, the device is HDMI-
of frame-buffer memory

Software  The XLR8 GeForce 200 series in-


cludes the GTX 260 PCIe 2 and
the GTX 280 PCIe 2 graphics cards.
Development The GTX 260 features 896 Mbytes of
Tools GDDR3 frame-buffer memory, a 576-
MHz core clock, and a 1242-shader
clock. The card has a 111.9-Gbps mem-
The Leader in Microcontroller Development Solutions ory bandwidth, 36.9 billion/sec tex-
ture-fill rate, and 2000-MHz effective

ARM
C/C++ Development Kit including ULINK®2 Adapter data rate. The GTX 280 provides 1024
best-in-class compilers, genuine Keil for target debugging Mbytes of GDDR3 frame-buffer memo-
μVision®, and royalty-free RTX RTOS. and Flash programming. ry, a 602-MHz core clock, and a 1296-
www.keil.com/arm
shader clock. The 280 has a 141.7-Gbps
memory bandwidth, 48.2 billion/sec

Cx51
A/D I/O Ports Run-
Control texture-fill rate, and 2214-MHz effec-
Timers Interrupts Debug tive data rate. The GTX 260 PCIe 2 and
Channel
www.keil.com/c51 the GTX 280 PCIe 2 graphics cards cost
PWM Flash $649.99 and $399.99, respectively.
ROM

C166
PNY Technologies, www.pny.com
UART
CPU
RAM

2
I C/SPI
DMA
RTC www.keil.com/c166 Discrete device combines
handset-audio filtering
Ethernet SD USB CAN
Out-of-the box support and ESD protection
for more than 1,400
Keil RTOS and Middleware components are specifically
Microcontroller devices.  Combining handset-audio filtering
and ESD protection, the EMIF06-
optimized for embedded systems and include TCP/IP, Flash File
system, USB and CAN support.

Call 1-800-348-8051 for a free demo CD. www.keil.com


COMPUTERS AND PERIPHERALS
AUD01F2 device suits portable con-
sumer headsets, including mobile
phones and MP3 players. The ven-
dor claims a 77% reduction in board
ble-precision, floating-point hardware
implementation delivers more than
200 Gflops. The FireStream 9250 and
the supporting software-development
product
space, compared with previous discrete
products. Available in a 2.42⫻1.92-
mm flip-chip package, the EMIF06-
AUD01F2 costs 55 cents (1000).
kit cost $999.
Advanced Micro Devices,
www.amd.com
mart
STMicroelectronics, www.st.com This advertising
Mac memory kit suits is for new and
Mac Pro desktops
Stream processor current products.
breaks 1-Tflop barrier  The fully buffered Mac memory
kit comes in a 4-Gbyte, 2⫻2-
 Occupying a single PCI slot, the
FireStream 9250 Stream proces-
Gbyte module. The 800-MHz memo-
ry kit targets recent Mac Pro desktop
sor breaks the 1-Tflop barrier. The de- systems. The 4-Gbyte Mac memory
vice has 150W power consumption, kit costs $250.
with as many as 8 Gflops/W. A dou- Corsair, www.corsair.com

A DV E R T I S E R I N D E X

Company Page Company Page


Actel Corp 6 Maxim Integrated Products 77
Advanced Interconnections 38 79, 81
Agilent Technologies 17 Melexis Inc 19
Altera Corp 61 Memory Protection Devices 66
Analog Devices Inc 21 Mentor Graphics 83
23 85, 87
C-3 Messe Muenchen GmbH 63, 65
Ansoft Corp 58 Micrel Semiconductor 12
austriamicrosystems AG 80 Microchip Technology 43
Bourns Inc 3 Mill Max Manufacturing Corp 55
BuyerZone 86 Monolithic Power Systems 53, 64
Central Semiconductor Corp 32 Mouser Electronics 8
Cirrus Logic Inc 2 National Instruments 4, 13
Coilcraft 11 NewarkInOne 25
CUI Inc 84 Noritake Co Inc
Cypress Semiconductor C-4 Electronics Division 28
Digi-Key Corp 1 Pico Electronics 39
Digi International-Rabbit 52 50, 54
EMA Design Automation 47 Radicom Research 89
Express PCB 56 Stanford Research Systems Inc 62
GaGe 68 Summit Microelectronics 48
ICS Electronics 46 Sunstone Circuits Inc 82
International Rectifier Corp 9 Tektronix 31
Intersil 33, 35 Tern 89
36, 37 That Corp 56
Keil Software 88 Toshiba America 14
Lattice Semiconductor 34 45, 57
LeCroy Corp C-2 Vicor Corp 51, 67
Linear Technology Corp 70, 75 Xilinx Inc 69
73, 74 EDN provides this index as an additional ser-
MathWorks Inc 27 vice. The publisher assumes no liability for errors
or omissions.

SEPTEMBER 4, 2008 | EDN 89


TALES FROM THE CUBE BY GLEN CHENIER • TEETER TOTTER TREE STUFF

told this colleague that this fix was not


The case of the stolen capacitor doable: I needed that capacitor for my
regulator. His reply was that our proto-
types worked without the capacitor on
my regulator and that it was too labor-
intensive to attach another capacitor
during the assembly rework. (Another
“Oops!” ensued.) I did not press the
point; after all, it was his circuit card,
and, as group leader, he made the final
decisions.
Six months went by with no prob-
lems. Then reports suddenly started
coming in from the field that new-pro-
duction cards would not work when
customers installed them into systems.
The clincher occurred when a field en-
gineer called us to ask whether it was
normal to have a 10-MHz sine wave
riding on the 12V rail. We investigat-
ed, and found that the production de-
partment had changed to a new vendor
of the voltage regulators. The new units
were some no-name brand for a few
pennies less and with no vendor logos
or markings on the parts. What’s worse,
the production department did not
keep the necessary records to indicate
the original manufacturer. Neverthe-
less, these regulators really did require
t was the usual team project: a group leader with overall

I
some input stabilizing capacitance.
responsibility for the end product, with assistant designers The result was the addition of ca-
working on specialized subsystems. I was designing the fiber- pacitors that we should have included
optic-communications links for the product, and, not want- during the initial rework, even though
it was too labor-intensive. Yet, it would
ing the noisy 5V digital-VCC supply to contaminate my sen- have been far less-labor intensive than
sitive analog circuits, I elected to linearly regulate the 12V the resulting recall of the cards.
down to a reasonably clean 5V to keep my analog circuits hap- I learned a good lesson from that ex-
py. The data sheet instructed me to include 10 ␮F of stabilizing perience. Even though it was ultimate-
capacitance at the input to my voltage regulator. Read on to ly not my responsibility, I should have
insisted that the team leader include
learn the very good reason for this inclusion. the additional capacitor. I have since
In the week before shipping the sulted; hot-plugging caused a glitch on applied this lesson to later team-design
product, a horrendous problem emerged. the 12V rail, in turn causing another issues, and some people now think of
Hot-plugging a card into the live back- colleague’s PLL (phase-locked loop) to me as an ornery old curmudgeon, but
plane caused a glitch on the system’s 5V hiccup. This glitch did not bother my the resulting designs always worked
rail and caused the main processor card 12 to 5V regulator because it had lots properly.EDN
to restart. Oops! I managed to arrive at of filtering on the output side.
a Band-Aid solution to that problem by So, the team lead came up with a You can reach design consultant Glen
attaching tantalum capacitors and fuses “fix” that resulted in the insertion of Chenier at glen@teetertottertreestuff.
DANIEL VASCONCELLOS

across the 5V rail on the backplane at a resistor that effectively separated the com. Like him, you can share your
every card slot. I then suggested that we capacitor from my regulator and stole Tales from the Cube and receive $200.
should perhaps also look at the hot-plug my regulator’s input capacitor for use in Contact edn.editor@reedbusiness.com.
effect on the 12V rail. the PLL-filtering function. When I saw
Surely enough, a similar problem re- his ECO (engineering-change order), I + www.edn.com/tales

90 EDN | SEPTEMBER 4, 2008


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