Low Power Efficient Built in Self Test

R.Muthammal#, Dr K O Joseph*
GKM College of Engineering &Technology,Chennai * josephkandath49@gmail.com

Abstract This paper proposes a low power efficient Built in Self Test (BIST) with Test Pattern Generation (TPG) technique, which reduces power dissipation during testing. In general, the correlations between the consecutive test patterns are higher during normal mode than during testing mode. The proposed approach uses the concept of reducing the transitions in the test patterns generated by conventional Linear Feedback Shift Register (LFSR) [1]. The transitions are reduced by increasing the correlation between the successive bits in the test pattern, which is done with the help of modified LFSR. This approach eliminates the need for an external tester. The simulation result shows that the power dissipated during testing is reduced in modified LFSR than in conventional LFSR. Keywords Built-In-Self Test (BIST), LFSR, Transitions, Multiple Input Signature Register (MISR), Power dissipation, Automated Test Equipment (ATE).

dissipation in CMOS circuits is proportional to switching activity, this excessive switching activity during test may be responsible for cost, reliability, performance verification, autonomy and technology related problems. In this paper ordinary LFSR in the BIST [2] circuit is modified to reduce the power dissipation in the consecutive test patterns, thereby reducing the power consumed by BIST. II. BIST ARCHITECTURE Built-in Self Test (BIST) is the technique of designing additional hardware and software features into integrated circuits to allow them to perform self-testing, thereby reducing dependence on external automated test equipment (ATE).
BIST Controller Unit (BCU)

I. INTRODUCTION The VLSI circuits are featured based on its performance, cost, testing, area, reliability and power. As the communication systems are increasing rapidly, there is a need to maintain low power dissipation in VLSI circuits. The power dissipation during test mode is more than in normal mode. Hence it is important aspect to reduce power dissipation during testing. In VLSI, according to thumb rule 50% of the total integrated circuits cost is due to testing. There are two main sources of power dissipation [5] in digital circuits. They are static and dynamic power dissipation. Static power dissipation is due to leakage current and its contribution to total power dissipation is very small. Dynamic power dissipation is due to switching i.e. the power consumed due to short circuit current flow and charging of load capacitances. Dynamic power dissipation contributes to total power dissipation in the circuit. There are several reasons for this power dissipation in test mode. To test large circuit, circuits are partitioned to save the test time but this parallel testing result in excessive energy and power dissipation. Due to the lack of equipment availability, delay is introduced in the circuit during testing .This causes power dissipation. When successive test vectors are applied to a given circuits in normal mode, the test vectors results in low correlation between consecutive test patterns. This can cause large switching activity in the circuit during test than during its normal operation. Power

Linear Feedback Shift Register (LFSR)

TPG

Reference Circuit

Circuit Under Test (CUT)

Multiple Input Signature Register (MISR)

TRA Comparator

Multiple Input Signature Register (MISR)

Test Results

Fig.1 Block Diagram of BIST Architecture. A typical BIST architecture [3] consists of LFSR, reference circuit, Circuit under test, Multiple input signature register (MSIR), comparator, and BIST controller unit (BCU). The LFSR generates the test pattern. The outputs of the LFSR are used as the inputs to the reference circuit and CUT, which is c432 ISCAS-85 a benchmark circuit of interrupt controller [6]. The output of the reference circuit and CUT is driven by MISR, which efficiently map different input streams to

different signatures with every small probability of alias. Then the output of the MISR is fed to the comparator, which is a test response analyser (TRA). The comparator compares the output of reference circuit and CUT. If both the outputs are same, this indicates no fault in the CUT. If both the outputs are not same, this indicates fault in the CUT. The BCU controls the execution of all the blocks. This approach allows applying at-speed tests and eliminates the need for an external tester. III. PROCESS OF ORDINARY LFSR A Linear Feedback Shift Register (LFSR) is a type of pseudorandom number generator. To illustrate an LFSR operation, consider a register that is 4 bits wide.

patterns. This technique generates a high correlation between neighbouring bits in the scan chain, reducing the number of transitions and, thereby reducing the power dissipation.

Fig.3 Circuit Diagram of a 8-bit Modified LFSR. The LFSR used for TPG is an external-XOR LFSR. As shown, R-injection circuit taps the present state and the next state of the LFSR. R-injection circuit consist of one AND, one OR and one 2:1 MUX.

Fig.2 Circuit Diagram of 4-bit Ordinary LFSR.

Start by loading it with an initial seed value. Shift it to the right, and XOR the bit at the output of the last flip-flop and first flip-flop. Then the output of XOR gate is fed to the input of first flip-flop. For this example, we'll use a seed of 0101. 0101 shifted is 1010 and a 1 fell off. 1010 shifted is 1101 and a 0 fell off. 1101 shifted is 0110 and a 1 fell off. 0110 shifted is 0011 and a 0 fell off. The number of values that an LFSR cycles through before repeating is its period. LFSRs that are maximal period cycle through 2^n-1 values before repeating, where n is the width of the register. In this approach, the transitions are high which reduces the correlation between consecutive test patterns generated by the LFSR. Reduction in correlation increases the power dissipation during testing, thereby increases the power consumed by BIST.

Fig.4 Internal view of R-Injection circuit. The algorithm used in modified LFSR is represented by the following flowchart:
Next Vector First half is active, second half is idle and gives the output as previous. T1 Both halves are in idle. First half sent to the output and second half output is sent by R-injector circuit. Tk1 Second half is active, and first half is in idle mode and gives same output as previous. Tk2 Both halves are in idle. First half is sent by R-injector circuit and second half is same as previous. Tk3

IV. MODIFIED LFSR Modifying the LFSR [4], by adding weights to tune the pseudorandom vectors for various probabilities, decreases energy consumption and increases fault coverage. In this technique, an LFSR generates equally probable random

Fig.5 Flowchart for modified LFSR.

The TPG is activated by two non-overlapping enable signals (en1 and en2). Each enable signal activates one half of the LFSR. In other words, when en1en2=10, first half of the LFSR is active and the second half is in idle mode. The second half is active when en1en2=01. MUX selects either the injection bit or the exact bit in the LFSR. One small finite state machine (FSM) controls the pattern generation process as follows:
TABLE I LOGIC USED IN MODIFIED LFSR

It is observed that the total power consumed in modified LFSR is 58.3% less than the power consumed with normal LFSR and output dynamic power is decreased by 41.7 %. It is concluded that low power LFSR is very useful for BIST implementation in which the CUT may be Combinational, or sequential memory circuits. Using low power LFSR technique we can further decrease the power consumption in BIST implementation.

#Clk 1

Patter n

En1

En2

Sel 1

Sel 2

Modified LFSR output

2 3 4 5 ...

T1 Tk1 Tk2 Tk3 T2 ...

1 0 0 0 1 ...

0 0 1 0 0 ...

1 1 1 0 1 ...

1 0 1 1 1 ...

1010 1010 1010 1111(R) 0101 ....

1011 1111(R) 0101 0101 0101 ....

Consider the seed value of LFSR as 0101 1011, Step 1: en1en2=10, sel1sel2=11. The first half of the LFSR is active and the second half is in idle mode. Selecting sel1sel2=11, both halves of the LFSR are sent to the outputs. In this case, T1 is generated. Step 2: en1en2=00, sel1sel2=10. Both halves of the LFSR are in the idle mode. The first half of the LFSR is sent to the outputs, then the second half of the output is from the injector circuit. Tk1 is generated. Step 3: en1en2=01, sel1sel2=11. The second half of the LFSR is active and the first half of the LFSR is in idle mode. Both halves are transferred to the outputs and Tk2 is generated. Step 4: en1en2=00, sel1sel2=01. Both halves of the LFSR are in the idle mode. From the first half the injector outputs are sent to the outputs of TPG and the second half sends the exact bits in the LFSR to the outputs to generate Tk3. Step 5: The process continues by going through Step 1 to generate Ti+1. The TPG with R-injection keeps the random nature of the test patterns intact. The FSM controls the test pattern generation through steps 1 to 4 and it is independent of the LFSR size. Clk and test en are the inputs of the FSM. When test en=1, FSM starts with step 1 by setting en1en2=10 and sel1sel2=11. It continues the process by going through step1 to step 4. One pattern is generated in each clock cycle. By following the above steps the number of transitions between the test patterns are significantly reduced, which eventually reduces the power dissipation during testing. V. RESULTS AND CONCLUSION The results are obtained from the Xilin 9.1 implementation with the device xc3s200-4pq208 in which, we have generated VCD file after the post simulation. Figures 6 - 11 shows the simulation output and test bench waveforms of XOR-LFSR, and Low Power BIST.

Fig.6. Output of XOR-LFSR.

Fig.7. Output of Low Power LFSR.

Fig.8.Test bench waveform for XOR-LFSR Fig.10. Test bench waveform for LP-LFSR

Fig.9.Test bench waveform for XOR-BIST

Fig.11. Test bench waveform for LP-BIST

VI. REFERENCE

[1] Chao Cheng, Keshab K. Parhi, High Speed VLSI Architecture for General Linear Feedback Shift Register (LFSR) Structures, Dept. of Electrical & Computer Engr., University of Minnesota, Minneapolis, MN 55455, USA. [2] F. Corno, M. Rebaudengo,M. Sonza Reorda and M. Violante, A New BIST Architecture for Low Power Circuits, in Proc. European Test Workshop (ETW99), pp. 160-164, 1999. [3] N. Ahmed, M. H. Tehranipour, M. Nourani, Low Power Pattern Generation for BIST Architecture, Center for Integrated Circuits & Systems, The Univ. of Texas at Dallas Richardson, TX 75083. [4] Ramesh Bhakthavatchalu, Archana K R, Aswathy Viswambharan, Deepthi, Brinda B S. Design of Programmable Logic-BIST Structures Using Verilog for Digital VLSI Circuits, Department of ECE, Amrita Vishwa Vidyapeetham, Coimbatore. [5] S. Wang and S. Gupta,DS-LFSR: A New BIST TPG for Low Heat Dissipation, in Proc. Int. Test Conf. (ITC97), pp. 848-857, 1997. [6] http://www.eecs.umich.edu/~jhayes/iscas/c432.htm l