Specmcm 251a172a

REVISIONS
R E L or E C O REV D E S C R I P T I O N D A T E A P P R O V E D
ECO EOA20188
Refer to Document Change History Herein
01-19-04
K. Mason
NOTES: 1.
2.
This is a TOP LEVEL DRAWING (TLD). BAE SYSTEMS - Manassas, VA reference only. All sheets are the same revision status.
3.
Copyright 2003-2004, BAE SYSTEMS. Licensed Material. Property of BAE SYSTEMS. All Rights Reserved.
Part Number - See Tabulation

C O N T R A C T N O.
N/A
P R E P A R A T I O N D A T E
9300 Wellington Road Manassas, VA 20110
P. NIXON
D E S I G N C H E C K D A T E
S. DOYLE
TECHNOLOGY CHECK D A T E T I T L E D A T E
K. STURCKEN
RADIATION CHECK
MCM, CMOS, 2.5V/3.3V, SRAM, 512Kx32, STACKED, OPT
R. BROWN
D R A W I N G C H E C K D A T E
P. NIXON
O T H E R A P P R O V A L D A T E
J. KRAUSE (BURNIN)
O T H E R A P P R O V A L D A T E
T. GREMBOWSKI (TEST)
O T H E R A P P R O V A L D A T E S I Z E C A G E C O D E D R A W I N G N O . R E V
A
S C A L E
1RU44 NONE
WT
251A172
S H E E T
A 1 of 35
C. SASSI (MILSCREEN)
FORM NO W26MAN94 - 001-0
Table of Contents
Document Change History ................................................................................................................................. 4 1 SCOPE.................................................................................................................................................... 4 1.1 SCOPE .................................................................................................................................................. 5 1.2 BAE SYSTEMS PART NUMBER AND IDENTIFICATION ............................................................................. 5 1.3 ABSOLUTE MAXIMUM RATINGS ............................................................................................................... 7 1.4 RECOMMENDED OPERATING CONDITIONS ............................................................................................... 8 1.5 POWER SEQUENCING ............................................................................................................................. 8 2 Applicable Documents ............................................................................................................................ 9 2.1 GOVERNMENT SPECIFICATIONS AND STANDARDS .................................................................................... 9 2.2 BAE SYSTEMS DOCUMENTATION ........................................................................................................ 9 2.3 OTHER DOCUMENTS .............................................................................................................................. 9 2.4 ORDER OF PRECEDENCE........................................................................................................................ 9 3 Requirements ........................................................................................................................................ 10 3.1 ITEM REQUIREMENTS ........................................................................................................................... 10 3.2 DESIGN, CONSTRUCTION, AND PHYSICAL DIMENSIONS .......................................................................... 10 3.3 ELECTRICAL PERFORMANCE CHARACTERISTICS AND POSTIRRADIATION PARAMETER LIMITS ................... 13 3.4 ELECTRICAL TEST REQUIREMENTS ....................................................................................................... 15 3.5 MARKING ............................................................................................................................................. 25 4 Quality Assurance Provisions ............................................................................................................... 26 4.1 SAMPLING AND INSPECTION .................................................................................................................. 26 4.2 SCREENING ......................................................................................................................................... 26 4.3 TECHNOLOGY CONFORMANCE INSPECTION (TCI) FOR DEVICE CLASSES H (T) AND K (T+) ..................... 28 4.4 QUALITY CONFORMANCE INSPECTION (QCI) ......................................................................................... 28 4.5 BURN-IN CIRCUIT ................................................................................................................................. 31 5 Packaging/Shipping............................................................................................................................... 33 5.1 PACKAGING/SHIPPING REQUIREMENTS ................................................................................................. 33
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CAGE CODE 1RU44 REV A
DWG NO. 251A172 SHEET 2 of 35
2.5V/3.3V 512Kx32 SRAM MCM
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Figures
FIGURE 1. CASE OUTLINE: 84-LEAD FP PACKAGE TOP, SIDE AND BOTTOM VIEWS (DRAWING NO. 249A428-1) ............................................................................................................................................... 11 FIGURE 2. CASE OUTLINE: 84-LEAD FP PACKAGE CROSS SECTION .................................................................... 12 FIGURE 3. SINGLE CHIP FUNCTIONAL BLOCK DIAGRAM ....................................................................................... 14 FIGURE 4. TYPICAL STANDBY CURRENT VS. TEMPERATURE FOR PASS 2 ............................................................. 17 FIGURE 5. OUTPUT LOAD CIRCUIT ..................................................................................................................... 21 FIGURE 6. READ CYCLE TIMING DIAGRAM .......................................................................................................... 22 FIGURE 7. W RITE CYCLE TIMING DIAGRAM ......................................................................................................... 23 FIGURE 8. PART MARK (TOP LID)....................................................................................................................... 25 FIGURE 9. BURN-IN CIRCUIT DIAGRAM FOR EACH SRAM DIE............................................................................... 32
Tables
TABLE 1. TABULATION ......................................................................................................................................... 5 TABLE 2. ABSOLUTE MAXIMUM RATINGS .............................................................................................................. 7 TABLE 3. RECOMMENDED OPERATING CONDITIONS .............................................................................................. 8 TABLE 4. TRUTH TABLE ..................................................................................................................................... 13 TABLE 5. CHANGE IN RISING OUTPUT PERFORMANCE VS. ADDITIONAL OUTPUT LOADING ..................................... 16 TABLE 6. CHANGE IN FALLING OUTPUT PERFORMANCE VS. ADDITIONAL OUTPUT LOADING ................................... 16 TABLE IA. ELECTRICAL PERFORMANCE CHARACTERISTICS.................................................................................. 18 TABLE IB. RADIATION REQUIREMENTS (TEST DATA TBD) .................................................................................... 24 TABLE 7. SCREENING FLOWS............................................................................................................................. 27 TABLE 8. QUALIFICATION TESTING REQUIREMENTS............................................................................................. 29 TABLE IIA. ELECTRICAL TEST REQUIREMENTS .................................................................................................... 30 TABLE 9. TERMINAL CONNECTIONS FOR 512K X 40 MCM IN 84-FP .................................................................... 34
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Document Change History

Date 11/20/03 01/19/04 R e v ECO Description of Changes Initial Release. Used 251A137 Rev F as baseline. This ECO releases -412, -413, -422, and -423 parts to Rev . Clarified in Table 1 that xx2, -xx7 and xx9 are all processed with accelerated burn-in conditions. Update capacitor part number to Class S in table in section 1.2.1. Update Table IA parameters tSLQV, tAVWH, tSLWH, tLVWH, and tWLWH for 41x devices to be consistent with 251A137 Rev G changes. Delete references to static burn-in in section 4.5. This ECO updates -412, -413, -422, -423 parts and releases -417, -419, -427, 429 parts all to Rev A. Originator P. Nixon P. Nixon
EOA19151
A EOA20188
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1 SCOPE
1.1 Scope
This Top Level Drawing (TLD) describes and specifies the requirements for a 0.25m Leff, monolithic silicon, memory device with commercial space capability. The memory device configuration is a 512Kx32 SRAM (four stacked 4M SRAM die) in a single, double-sided ceramic substrate.
1.2
BAE SYSTEMS Part Number and Identification
The following tabulation table defines exceptions to the listed sections of this document. Exceptions include: BAE SYSTEMS qualification levels, case outline specifications, radiation test requirements, electrical test requirements, part marking requirements, screening requirements, and technology conformance inspection provisions.
Table 1. Tabulation
Section Name Rev Device Qualification Radiation Test Test Level per Requirements Requirements Type internal spec (Access Time) MAN-STC-Q002 2/ 4.0 3.3 3.4.3 Part Marking Requirements 1/ Screening Technology Requirements Conformance per internal spec Inspection per MAN-STC-Q002 internal spec MAN-STC-Q002 4.2 4.3
Section Number Part Number 251A172-412 A 412
3.5
Prototype
Limits not guaranteed
15 ns
251A172-412 Prototype (USA) datecd
Prototype flow with accelerated burn-in conditions Engineering flow
Not required
251A172-413
413
Engineering
15 ns
251A172-413 Engineering (USA) datecd
Not required
251A172-417
417
Pre-qualified
200Krad
15 ns
251A172-417 Pre-qualified (USA) datecd
Commercial Space "T+" ("modified Kscreen") flow with accelerated burn-in conditions Commercial Space "T" ("modified Hscreen ") flow with accelerated burn-in conditions Prototype flow with accelerated burn-in conditions Engineering flow
As required
251A172-419
419
Pre-qualified
200Krad
15 ns
As required
251A172-422
422
Prototype
17 ns
251A172-422 Prototype (USA) datecd
Not required
251A172-423
423
Engineering
17 ns
251A172-423 Engineering (USA) datecd
Not required
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Section Name
Rev Device Qualification Radiation Test Test Level per Requirements Requirements Type internal spec (Access Time) MAN-STC-Q002 2/ 4.0 3.3 3.4.3
Part Marking Requirements 1/
Screening Technology Requirements Conformance per internal spec Inspection per MAN-STC-Q002 internal spec MAN-STC-Q002 4.2 4.3
Section Number Part Number 251A172-427 A 427
3.5
Pre-qualified
200Krad
17 ns
Commercial Space "T+" ("modified Kscreen") flow with accelerated burn-in conditions Commercial Space "T" ("modified Hscreen ") flow with accelerated burn-in conditions
As required
251A172-429
429
Pre-qualified
200Krad
17 ns
As required
Notes: 1/ Part marking requirements are for the 3 , 4 , 5 and 6 rows as detailed in Section 3.5 herein. "datecd" = date code. Reference Case Outline shown in Figure 1 on sheet 11 herein. 2/ The test requirements for each device type are delineated in Table IA.
rd th th th
1.2.1
Manufacturing Tree for 251A172 Part Description Part Number 2 249A428-1 250A783 (WB die) 250A783 (C4 die) 1/ 8388297-1 [or LICA3T253M1FC4xA] (Class R screened) 8388297-2, -3 (upscreened parts) or 8388297-4 (Class S screened) Device Type All All Qty 1 4 Part Supplier BAE SYSTEMS BAE SYSTEMS (commercial foundry) AVX Corporation
Module Assembly DWG. No. 512Kx8 SRAM die
Capacitors (Low Inductance decoupling Capacitor Arrays), 100nF
Only -xx2, -xx3 All
10
Notes: 1/ the C4 die uses the same mask set as the WB (wirebond) die with the exception of the TV mask level which is replaced by the LV reticle for the C4 die.
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1.3
Absolute Maximum Ratings
Table 2. Absolute Maximum Ratings

Applied Conditions 1/ Storage Temperature Range (Ambient) Operating Temperature Range (TJ) 5/ Positive Supply Voltage (VDD) Positive I/O Supply Voltage (VDD2) Input Voltage 2/ Output Voltage 2/ Power Dissipation 3/ Module Thermal Resistance, junction-to-case (jc) 6/ Lead Temperature (Soldering 5 sec) Electrostatic Discharge Sensitivity 4/ Class 2 (TBD) Minimum 65C 55C 0.5V 0.5V 0.5V 0.5V Maximum +150C +140C +3.80V +5.70V VDD2 + 0.5V VDD2 + 0.5V 2.4W 7.8C/W +265C
Notes: 1/ Stresses at or beyond the absolute maximum ratings may cause permanent damage to the device. Extended operation at the maximum or minimum levels may degrade performance and affect reliability. All voltages are referenced to the module ground leads. 2/ Maximum applied voltage shall not exceed 3.80V for VDD or 5.70V for VDD2. 3/ Not tested. This value is based on a steady-state wave form analysis at worst case conditions for an active chip current spike approximately 1.5ns wide that goes to no current approximately 2.3ns into the cycle (at 2.70V) and an I/O current spike approximately 3.0ns wide that goes to no current approximately 7.0ns into the cycle (at 3.60V). This analysis assumes a 14ns access and 20ns standby cycle. The steady state power for these conditions is calculated to be 2.4W for the entire module. 4/ Class as defined in MIL-STD-883, Method 3015. 5/ Operation outside the recommended operating conditions specified in Table 3 may cause degradation in the electrical parameters as defined herein. 6/ Thermal resistance is based on all four die dissipating a total of 2.4W per module. The worst case steady-state temperature rise from the bottom of the case to the junction of the topmost die is 18.566C. A maximum transient delta temperature can be added to the maximum steady state temperature rise to establish a true maximum junction temperature rise at the sub-block level. The transient analysis of a sub-block shows the delta case to junction temperature to be 0.225C. Therefore, the maximum case to junction temperature rise for 2.4W dissipated by the entire module will be 18.791C.
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1.4
Recommended Operating Conditions
Table 3. Recommended Operating Conditions

Symbol VDD VDD2 GND Tcase VIL VIH Note: 1/ All voltages referenced to GND. Parameters 1/ Supply Voltage I/O Supply Voltage Supply Voltage Reference Case Temperature Input Logic Low Input Logic High Minimum +2.30 +3.00 0.00 55 0.00 +2.00 +25 Nominal +2.50 +3.30 Maximum +2.70 +3.60 0.00 +110 +0.80 VDD2 Units Volt Volt Volt Celsius Volt Volt
1.5
Power Sequencing
The substrate of this module is connected directly to Ground. Power shall be applied to the device only in the following sequences to prevent damage due to excessive currents. Power-up sequence: GND, VDD and/or VDD2, Inputs Power-down sequence: Inputs, VDD2 and/or VDD, GND NOTES: 1) Delay between power up or down for VDD and VDD2 can be between 10ms to +50ms. 2) The loss of the 2.5V power supply (3.3V power supply active) coupled with an external event (e.g. SEU hit on a critical I/O circuit) may result in a shorting condition. This combined event can not exist for more than 5 minutes (cumulative time) without reliability impact. A safety margin is included in this analysis, contact BAE SYSTEMS if this limit has been exceeded. If there is no external event, the loss of the 2.5V power supply alone will not result in any reliability impact.
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2 Applicable Documents
2.1 Government Specifications and Standards
Unless otherwise specified, the following specifications and standards form a part of this drawing to the extent specified herein. Specifications, Military DOD-HDBK-263 - Electrostatic Discharge Control Handbook For Protection of Electrical and Electronic Parts, Assemblies and Equipment (Excluding Electrically Initiated Explosive Devices) MIL-PRF-38534 MIL-PRF-38535 Standards, Military DOD-STD-1686 - Electrostatic Discharge Control Program for Protection of Electrical and Electronic Parts, Assemblies, and Equipment (Excluding Electrically Initiated Explosive Devices) MIL-STD-883 MIL-STD-1835 Test Methods and Procedures for Microelectronics Electronic Component Case Outlines Hybrid Microcircuits, General Specification For Integrated Circuits (Microcircuits), Manufacturing General Specification For
2.2
BAE SYSTEMS Documentation

MAN-STC-Q001 - Quality Management (QM) Program MAN-STC-Q002 - Quality and Qualification Requirements for Microcircuits
2.3
Other Documents
ASTM standard F1192M-95 - Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of Semiconductor Devices (Metric)
2.4
Order of Precedence
In the event of conflict between the text of this drawing and the references cited herein, the text of this drawing shall take precedence.
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3 Requirements
3.1 Item Requirements
The individual item requirements for device classes H (T) and K (T+) shall be in accordance with MIL-PRF38534, the device manufacturers Quality Management (QM) plan (BAE SYSTEMS specification MAN-STCQ001), BAE SYSTEMS specification MAN-STC-Q002, and as specified herein.
3.2
Design, Construction, and Physical Dimensions
The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, MIL-STD-1835, and herein. 3.2.1 Case Outline
The case outline shall be as specified in this section. The case outline for a particular device type shall be as delineated in Section 1.2 herein. 3.2.1.1 3.2.2 84-LEAD Flat Pack Package: The case outline shall be in accordance with Figure 1 on sheet 11. Terminal Connections
The terminal connections shall be as specified in Table 9, starting on sheet 34. 3.2.3 Functional Description
A Functional Block Diagram shall be as specified Figure 3 on sheet 14. 3.2.4 Truth Table
The Truth Table shall be as specified in Table 4 on sheet 13. 3.2.5 Materials
All devices supplied under this specification shall be hermetically sealed in metal and/or ceramic packages. Organic or polymerized materials may be used inside the microcircuit package provided that the package is capable of meeting the internal water-vapor content requirement of MIL-STD-883, Test Method 1018. The requirements for the lid, substrate, and the device leads are defined in the module assembly drawing as cited in Section 1.2.1 herein. 3.2.5.1 Lead Base Material The base lead material shall be type A kovar as specified in MIL-PRF-38535 paragraph 3.6.2.5. Lead Finish The lead finish material shall be 100 micro inches of gold plated over 100 to 300 micro inches of nickel.
3.2.5.2
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Notes: 1. For part mark, reference section 3.5, sheet 25 herein and Table 1, sheet 5 herein. 2. Dimensions are in millimeters, unless otherwise specified. 3. Lead Width: 0.008 0.002 inches. Lead Height: 0.005 + 0.002 / 0.001 inches. Lead Pitch: 0.020 + 0.004 inches.
Figure 1. Case Outline: 84-lead FP Package Top, Side and Bottom Views (Drawing No. - 249A428-1) SIZE A CAGE CODE 1RU44 REV A DWG NO. 251A172 SHEET 11 of 35
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Bulk Silicon Chip 2X Places per side
Gold Ball Wire Bond
97Pb / 3Sn Notes: 1. 4xx device type utilizes 2 die per each cavity of the package (4 die total). 2. 2 die use C4 flip chip to attach to the package substrate; 2 die use gold ball bond to attach from the die to the package substrate. 3. Dimensions are in inches (mm).
Figure 2. Case Outline: 84-lead FP Package Cross Section
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3.3
Electrical Performance Characteristics and Postirradiation Parameter Limits
The electrical performance characteristics specified in Table IA are guaranteed for post-irradiation to those radiation levels specified in Table IB. Device latchup will not occur for radiation levels specified in Table IB and operating conditions less than or equal to those specified in Table 3. The applicability of these postirradiation guarantees for a particular device type is as specified in section 1.2 herein.
Table 4. Truth Table

Mode LS, LD 3/ WRITE READ STANDBY 4/ STANDBY LS = LD LS = LD X LS LD S LOW LOW HIGH X Inputs 1/, 2/ W LOW HIGH X X G X LOW X X I/O DATA-IN DATA-OUT HIGH-Z HIGH-Z ACTIVE ACTIVE STANDBY STANDBY Power
Notes: 1/ Logic Low and High are defined by VIL or VIH in Table 3. VIN for Dont Care (X) inputs = VIL or VIH. 2/ When G = HIGH, I/O is High-Z. 3/ LS0, LS1 (select) and LD0, LD1 (decode) inputs provide externally programmable bank-select decode capability. A match between the LS and LD bits will pass control of the module to chip select; a mismatch between the LS and LD bits overrides chip select and puts the entire module into standby mode. 4/ To dissipate the minimum amount of standby power when in standby mode: CS > VDD; LD0 and LD1 > VDD or = GND, LS0 and LS1 > VDD or = GND. All other input levels may float.
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A17-A18
Block Decoder Sub-Block Decode Row Address Decoder ((256 x 32) x 16 x 4) x 8 Memory Cell Array
A13-A16
A0-A7
8 Bit Word Input/Output
Column Address Decoder
E S LS0
XNOR
DQ0-DQ7
A8-A12
LD0 LS1
XNOR
LD1
Notes: 1. Address and control signals (including LD/LS pins) are common with all SRAM devices. 2. E is tied to Vdd internal to the package.
Figure 3. Single Chip Functional Block Diagram
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3.4
3.4.1
Electrical Test Requirements

Manufacturing Electrical Tests
The manufacturing electrical test requirements shall consist of functional test patterns as defined below. All tests shall be performed across the temperature and supply voltage range as specified in 1.4 herein. Any single functional fail shall be cause for device rejection. The dynamic tests specified below assure test coverage for the 512Kx32 SRAM MCM device. The patterns are used with device specific address descrambling and various timing conditions to insure sound device performance. The MARCH pattern, which is 13N, covers defects or faults in the memory. Such faults are stuck cell, open cell, lack of address decode uniqueness and adjacent cell coupling. The RCGAL pattern, which is n(3/2), covers additional performance problems that may be missed by the MARCH pattern. With address descrambling, this pattern covers the potential performance problems that the traditional N patterns did when used without address descrambling. The DADD pattern, or data equals address pattern, writes and reads sequential bytes of data to and from the memory under test which are equal to the eight least significant address signals. The purpose is to check for data word uniqueness versus byte address. MARCH: a. b. c. d. e. Write a background of 0s into all cells. Starting at address 0, read 0, write it to a 1, read it as a 1. Increment address and repeat step b. for entire memory. Starting at maximum address, read 1, write it to a 0, read it as a 0. Decrement address and repeat step d. for entire memory.
RCGAL: a. b. c. d. e. f. Write a background of 0s into all cells. Write 1 into address Test Bit (Test Bit starts at cell zero and is incremented through the entire memory). Alternately read Test Bit and each cell on the row of the Test Bit. Alternately read Test Bit and each cell on the column of the Test Bit. Write Test Bit back to 0, then increment the test bit. Repeat Step b - e until Test Bit has been at every cell in memory.
DADD: a. b. c. d. e. f. g. Starting at address 0, write 0 into RAM. Increment address and data word. Write RAM. Repeat steps b and c until address and data equal 255 (base 10). Increment address, reset data word to 0, write RAM. Increment address and data word. Write RAM.
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h. i. j.
Repeat steps f and g until entire RAM is written. Reset address back to 0. Sequentially read entire RAM and check for correct data.
3.4.2
Switching Tests
Switching tests shall be as specified in Table IA.
3.4.3
Performance vs. Output Load
The following tables show the change in MCM performance based on change in output loading above and beyond the output load as shown in Figure 5.
Table 5. Change in Rising Output Performance vs. Additional Output Loading

Tcase +125C +100C +25C 30C 55C Condition VDD 2.25V 2.25V 2.50V 2.75V 2.75V VDD2 2.97V 2.97V 3.30V 3.63V 3.63V +50pF 1.841ns 1.823ns 1.516ns 1.234ns 1.132ns +100pF 3.666ns 3.637ns 3.026ns 2.468ns 2.260ns +200pF 7.319ns 7.237ns 6.053ns 4.927ns 4.520ns +300pF 10.725ns 10.703ns 9.040ns 7.383ns 6.735ns
Table 6. Change in Falling Output Performance vs. Additional Output Loading

Tcase +125C +100C +25C 30C 55C Condition VDD 2.25V 2.25V 2.50V 2.75V 2.75V VDD2 2.97V 2.97V 3.30V 3.63V 3.63V +50pF 1.820ns 1.709ns 1.330ns 1.093ns 0.997ns +100pF 3.613ns 3.385ns 2.636ns 2.170ns 1.981ns +200pF 7.216ns 6.743ns 5.249ns 4.332ns 3.963ns +300pF 10.604ns 10.003ns 7.820ns 6.470ns 6.002ns
These performance values are based on an initial module loading of 30pf, which includes the module device self capacitance. These tables are provided for user reference and the values are not tested.
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3.4.4
Standby Current vs. Temperature
The following figure shows the change in MCM standby current over temperature. This figure is based on the typical measurements (pre-irradiation) for eight devices from the Pass 2.1 design and therefore is only for reference.
512Kx32 SRAM Pass 2.1 Iddq vs Temperature

140
120.2
120 100 Iddq (mA)

82.2
80 60 40
21.6 43.8
20
1.4
2.7
5.4
10.8
0
20 C 25 C 30 C 35 C 40 C 45 C 50 C 55 C 60 C 65 C 70 C 75 C 80 C 85 C 90 C 95 C 10 0C 10 5C 11 0C 11 5C 12 0C 12 5C
Temperature (degrees C) 2.30V/3.00V 2.50V/3.30V 2.70V/3.60V
Figure 4. Typical Standby Current vs. Temperature for Pass 2.1
3.4.5
Test Requirements
The electrical test requirements shall be as specified in Table IIA on sheet 30. The electrical tests for each subgroup are defined in Table IA.
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Table IA. Electrical Performance Characteristics

Test Symbol Test Conditions 1/ 55C < Tcase < +110C 2.30V < VDD < 2.70V 3.00V < VDD2 < 3.60V unless otherwise specified
F = 25MHz /S = VIL = GND, E = VIH = VDD No output load, Random Pattern
Group A Subgroups
Device Type 2/
Limits
Units
Min. 1, 2, 3 All
Max 850 mA
Supply Current (Cycling Selected) 7/
IDD1
IDD1S
F = 25MHz /S = VIL = GND, E = VIH = VDD No output load, Sequential Pattern
1, 2, 3
All
650
mA
Supply Current (Cycling De-Selected) Supply Current (Standby)
IDD2
F = 25MHz /S = VIH = VDD, E = VIL = GND
1, 2, 3
All
100
mA
IDD3
F = 0 MHz /S = VIH = VDD, E = VIL = GND
1, 2, 3
All
100
mA
Data Retention Current (Standby) High Level Output Voltage High Level Output Voltage Low Level Output Voltage Low Level Output Voltage Data Retention Voltage High Level Input Voltage Low Level Input Voltage
IDR VOH VOH VOL VOL VDR VIH VIL
VDD = VDD2 = 1.5V IOH = -4 mA IOH = -200 A IOL = 8 mA IOL = 200 A VDD = VDD2 = VDR
1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3
All All All All All All All All 1.5 2.0 2.4 VDD2 0.1V
75
mA V V
0.4 0.1
V V V V
0.8
Input Leakage except LDx, LSx, CS
IILK
0V < VIN < 3.6V
1, 2, 3
5xx
25
25
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Test
Symbol
Test Conditions 1/ 55C < Tcase < +110C 2.30V < VDD < 2.70V 3.00V < VDD2 < 3.60V unless otherwise specified 0V < VOUT < 3.6V 3/ 3/ 3/ See 3.4.1 herein
Group A Subgroups
Device Type 2/
Limits
Units
Min. 1, 2, 3 4 4 4 7, 8A, 8B 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 5xx All All All All x1x x2x x1x x2x x1x x2x x1x x2x All All All All All All All All 3 3 1 3 5 7 5 15 17 15 17 16 18 17 19 6 25
Max 25 35 40 12 A pF pF pF
Output Leakage Cin, except LDx Cin for LDx pins Cout Functional Tests Read Cycle Time Address Access Time Chip Select Access Time LS/LD Access Time Output Enable Access Time Chip Select to Output Active LS/LD to Output Active Output Enable to Output Active Output Hold after Address Change Chip Select to Output Disable LS/LD to Output Disable Output Enable to Output Disable
IOLK
Read Cycle AC Specifications tAVAV tAVQV tSLQV tLVQV tGLQV tSLQX tLVQX tGLQX tAXQX tSHQZ tLXQZ tGHQZ ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Test
Symbol
Test Conditions 1/ 55C < Tcase < +110C 2.30V < VDD < 2.70V 3.00V < VDD2 < 3.60V unless otherwise specified
Group A Subgroups
Device Type 2/
Limits
Units
Min.
Max
Write Cycle AC Specifications 4/ to 6/ Write Cycle Time Address Setup to End of Write Chip Select to End of Write LS/LD to End of Write Write Pulse Width tAVAV tAVWH tSLWH tLVWH tWLWH 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 x1x x2x All All All All All All All All All All All 5 15 17 10 10 11 10 6 2 0 1 3 6 ns ns ns ns ns ns ns ns ns ns ns ns ns
Data Setup to End tDVWH of Write Data Hold after End of Write Address Setup to Start of Write tWHDX tAVWL
Address Hold after tWHAX End of Write Output Active after tWHQX End of Write Write Enable to Output Disable Write Disable Pulse Width tWLQZ tWHWL
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Test
Symbol
Test Conditions 1/ 55C < Tcase < +110C 2.30V < VDD < 2.70V 3.00V < VDD2 < 3.60V unless otherwise specified
Group A Subgroups
Device Type 2/
Limits
Units
Min.
Max
Notes: 1/ Test conditions are defined at inception of test. The device is first stabilized at the desired temperature in an unpowered state to ensure that the module is at the desired Tcase before parameters are measured. The case temperature (Tcase) is maintained during testing at the specified temperature by a forced air test environment. Test conditions for AC measurements are listed below. Input Levels: Input rise and fall time: 0V to VDD, VDD2 < 1.0ns/Volt 1.5V VOL = 1.23V, VOH = 2.23V.
Input and output timing reference levels (except for tristate parameters): Input and output timing reference levels for tristate parameters: Output load:
See Figure 5 below and section 0 on sheet 16.
Read Cycle timing diagram is shown in Figure 6 on sheet 22. Write Cycle timing diagram is shown in Figure 7 on sheet 23. LS and LD: 2/ 3/ 4/ 5/ 6/ 7/ See Table 4 on sheet 13. The device types are as defined in 1.2 herein. The delineation in this table is by device speed, thus the x1x and x2x nomenclature. x1x represents a 15 ns device; x2x represents a 17 ns device. Guaranteed by design and verified by periodic characterization. S high and W high must occur while address transitions. The worst case timing sequence of tWLWH + tWHWL = tAVAV (write cycle time). G high will prevent the I/O output from becoming active (tWLQZ).. IDD1 is measured at 25MHz and 110C. User may extrapolate to other frequencies by removing the fixed standby current component and rescaling according to the following formula: active current at frequency (FNEW ) = [((IDD1 - IDD3) (F=25MHz)) * FNEW ] + IDD3
162 1% 1.73V 30 pF 10%
Figure 5. Output Load Circuit
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t AVAV
ADDRESS VALID ADDRESS
t AVQV t SLQV
S
t AXQX
t SLQX t LVQX
LS,LD
VALID COMPARE
t SHQZ
t LVQV t GLQV
G
t LXQZ
t GLQX
t GHQZ
DATA OUT
HIGH IMPEDANCE VALID DATA
Figure 6. Read Cycle Timing Diagram
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t AVAV
ADDRESS VALID ADDRESS
t AVWH t SLWH
S
t WHAX
LS,LD
VALID COMPARE
t LVWH t WLWH
W
t AVWL t WLQZ
DATA OUT HIGH IMPEDANCE HIGH IMPEDANCE
t WHWL t WHQX
t DVWH t WHDX
DATA IN HIGH IMPEDANCE VALID DATA HIGH IMPEDANCE
Figure 7. Write Cycle Timing Diagram
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Table IB. Radiation Requirements

Symbol RTD RPRU Characteristics Total Dose 5/ Prompt Dose Upset 8/ RS Survivability 7/ Conditions 1/, 2/ Device Type Min. 2.0E+05 1E+08 Max Units rad(Si) rad(Si)/s
VDD = 2.70V, VDD2 = 3.60V All during irradiating, static bias 20ns-50ns pulse width All Tcase = 25C and 110C, VDD = 2.30V, VDD2 = 3.00V 20ns-50ns pulse width All Tcase = 110C, VDD = 2.70V, VDD2 = 3.60V -55C <Tcase < 110C, All VDD = 2.30V, VDD2 = 3.00V
1E+11
rad(Si)/s
SEU
Single Event Upset 3/
1E-09
upsets/bitday
SEL
All Single Event Induced -55C < Tcase < 110C, Latchup 3/ VDD = 2.70V, VDD2 = 3.60V Neutron Fluence 6/ Tcase = 25C, unbiased during exposure All
Immune 4/ 1E+13 N/cm2
RNF
Note: 1/ Measured at room temperature unless otherwise stated. Verification test per TRB approved test plan. 2/ Device electrical characteristics are guaranteed for post irradiation levels at 25C. 3/ Calculation performed assuming CREME96 GCR Heavy Ion Spectrum with 0.100 of Aluminum shielding with an absorption depth of 2m. Testing performed according to ASTM Standard F1192. 4/ Immune for LET < 80 Mev-cm2/mg. 5/ Irradiation performed according to MIL-STD-883, Test Method 1019.5, Condition A. Specification guaranteed for dose rates between 50 and 300 rad(Si)/s. 6/ Technology Capability. No specific testing is performed on this part type. 7/ Testing performed according to MIL-STD-883, Test Method 1021.2. 8/ Testing performed according to MIL-STD-883, Test Method 1020.1 and 1021.2.
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3.5
Marking
The part shall be marked with the markings shown below and as specified in section 1.2 herein. The marking orientation to the case outlines shall be as specified in the case outline described in section 3.2.1 on sheet 10. Additional markings shall include the ESD symbol as a lead one designator. The ESD classification level is a specified in section 1.3 herein. Marking shall be in accordance with MIL-PRF-38535 as implemented according to the approved BAE SYSTEMS QML Quality Management Program. ESD marking shall be in accordance with DOD-STD-1686. Marking permanence verification shall be in accordance with MIL-STD-883, Test Method 2015. Top Lid Markings ** Pin 43 Pin 84 Mark line 1: Mark line 2: Mark line 3 *: Mark line 4 *: Mark line 5 *: Mark line 6 *: *****
BAE SYSTEMS
1RU44 251A172-XXX XXXXXXXXXXXX XXXXXXXXXXXX QML*** (USA) datecode SSSSS****
Pin 42 Pin 1 Notes: * ** *** **** ***** For lines 3 through 6, reference Part Marking Requirements of Table 1, Section 1.2 herein. Lines 4 and 5 may be blank. Datecode is formatted YYWW. Reference Case Outline shown in Figure 1 on sheet 11. QML may not be required. Non repeating serial number. Serial number may also appear on selvage strip. ESD indicators are located near pin 1.
Figure 8. Part Mark (Top Lid)
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4 Quality Assurance Provisions

All quality assurance provisions shall be as documented in BAE SYSTEMS specification MAN-STC-Q002 and MAN-STC-Q001. BAE SYSTEMS specification MAN-STC-Q002 defines three quality levels of devices, or device classes. They are: BAE SYSTEMS QML (Class H/T and K/T+), Prototype, and Engineering. The qualification level of each particular device type manufactured to this drawing shall be as specified in section 1.2 herein.
4.1
Sampling and Inspection
For class H (T) and K (T+) parts, sampling and inspection procedures shall be in accordance with MIL-PRF38534 as implemented by BAE SYSTEMS approved Quality Management (QM) plan and as specified in BAE SYSTEMS specification MAN-STC-Q002.
4.2
Screening
For Class H (T) and K (T+) parts, screening shall be in accordance with MIL-PRF-38534 as implemented by BAE SYSTEMS approved Quality Management (QM) plan and as specified in Table 7. Screening shall be conducted on all devices prior to qualification and technology conformance inspection. The screening requirements for each particular device type manufactured to this drawing shall be as specified in section 1.2 herein. 4.2.1 Screening Flows are defined in Table 7 on sheet 27.
4.2.2 Accelerated Burn-in Conditions Equivalent burn-in stress is calculated using foundry reliability acceleration factors. The maximum junction temperature for burn-in is specified as 140C. The following burn-in conditions are equivalent: Temp (TA) Vdd (core) Vdd2 (I/O) Standard: Accelerated: 125C 125C 2.70V 3.00V 3.60V 3.75V Time (Flight) 160 hours 19.67 hours Time (Prototype/ Pre burn-in) 24 hours 2.95 hours Time (Life Test) 1000 hours 123 hours
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Table 7. Screening Flows

Assembly and Screening Flow BAE SYSTEMS part number Wafer Fabrication Wafer Lot Acceptance Chip Inspection 883 Test Method
Commercial Space Commercial Space "T+" ("modified K"T" ("modified Hscreen") Flight flow screen") Flight flow
251A172-xx7 -5007 2010 Foundry B per MAN-STCQ014 Cond A, per MAN-STC-A014 100% 100%
251A172-xx9 Foundry B per MAN-STCQ014 Cond A, per MAN-STC-A014 100% 100%
Prototype, Engineering Comments flow 251A172-xx2, 251A172-xx3 Foundry B Commercial Foundry procedures N/A Internal procedures N/A 100% 100% Internal procedures Internal procedures
Serialization -C4 attach/flux clean -the 2 innermost die and capacitors Die attach 2 top die, -Wire bond (Gold Ball Bond) C4 Encapsulation/Cure -Wirebond Pull Tests 2011 Die Pull Tests 2027/2031 Dynamic Burn-in 1/ 4/ 1030 (Pre-Burnin condition)
100% 100% Setup Samples Setup Samples 3.0 (-0,+1.0) hours, 125C or equivalent
100% 100% Setup Samples Setup Samples 3.0 (-0,+1.0) hours, 125C or equivalent
100% 100% N/A N/A N/A
Internal procedures Internal procedures Destructive test Destructive test Use accelerated voltage conditions of VDD = 3.00V, VDD2 = 3.75V. This pre-burnin is optional ONLY if the accelerated voltage conditions are used for the 160-hour burn-ins defined below. 3/
T1A Test 4/ Pre-Lid Inspection (Internal Visual) Customer Source Inspection (CSI) Vacuum Bake, Lid seal Fine Leak Temperature Cycle Mechanical Shock PIND X-ray T1B Test Dynamic Burn-in 1 T1C Test 4/
Per TLD 2010, 2017 Per SOW -1014 1010 2002 2020 2012 Per TLD 1015 Per TLD
25C (Optional 3 temp) Cond A, per MAN-STC-A013 *** As Req'd *** 100% 100% Cond C, 20 cycles Cond C, 2-axes Cond A, 100% 100% 25C 160hrs, 125C or equivalent 2/ 25C
25C N/A (Optional 3 temp) Cond A, per per MAN-STC-A013 MAN-STC-A013 *** As Req'd *** N/A 100% 100% Cond C, 20 cycles Cond C, 2-axes Cond A, 100% 100% 25C N/A N/A 100% Optional N/A N/A N/A N/A N/A N/A N/A Internal procedures. Cond A; Rework failing lid if necessary Cond C = -65C to +150C Cond C = 3000G
1/
This test is optional. If the two burn-ins are combined then PDA applies to the combined burn-in.
Dynamic Burn-in 2 T2 Test (Final Test) PDA
1/
1015 Per TLD --
160hrs, 125C or equivalent 2/ (3 temp) 2%\one device or pattern failure option
160hrs, 125C or equivalent 2/ (3 temp) 10%\one device or pattern failure option
24hrs, 125C or equivalent 3/ -xx2 (3 temp) -xx3 25C N/A MAN-STC-Q016 (ref. MIL-PRF38534) based on number of die
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Assembly and Screening Flow BAE SYSTEMS part number Partmark Fine/Gross Leak Final Inspection Customer Source Inspection (CSI) Stock/Ship
883 Test Method
Commercial Space Commercial Space "T+" ("modified K"T" ("modified Hscreen") Flight flow screen") Flight flow
251A172-xx7 per TLD 1014 2009 Per SOW -see Section 3.5 100% 100%, per MAN-STC-A501 *** As Req'd *** Per Purchase Order
251A172-xx9 see Section 3.5 100% 100%, per MAN-STC-A501 *** As Req'd *** Per Purchase Order
Prototype, Engineering Comments flow 251A172-xx2, 251A172-xx3 see Section 3.5 N/A Cond A, C 100%, per MAN-STC-A501 N/A Per Purchase Order
Note: 1/ Burn-in conditions as defined in Section 4.5 on sheet 31. 2/ Burn-in for 160 hours at VDD= 2.70V, VDD2=3.60V, and TA=125C calculates to an equivalent accelerated stress of 19.67 hours at VDD=3.00V, VDD2=3.75V and TA=125C. For manufacturing, time in burn-in may be performed for 19.7 -0/+2.0 hours at accelerated conditions. This calculation is based on commercial foundry reliability data with temperature acceleration constant Ea=0.7eV and voltage acceleration constant Beta=7.0/V. This 160-hour burn-in (or equivalent) is done 2X for the Commercial Space "T+" modified Class K flow and 1X for the Commercial Space "T" modified Class H flow. 3/ Pre burn-in or Prototype burn-in for 24 hours at VDD= 2.70V, VDD2=3.60V, and TA=125C calculates to an equivalent accelerated stress of 2.95 hours at VDD=3.00V, VDD2=3.75V and TA=125C. For manufacturing, time in burn-in may be performed for 3.0 -0/+1.0 hours at accelerated conditions. This calculation is based on commercial foundry reliability data with temperature acceleration constant Ea=0.7eV and voltage acceleration constant Beta=7.0/V. This 24-hour burn-in is done for the Prototype flow (-xx2) or for pre burn-in on the Flight flows. No burn-in is performed on Engineering parts (-xx3). 4/ This is an optional step in the flow.
4.3
Technology Conformance Inspection (TCI) for Device Classes H (T) and K (T+)
Inspection for device classes H (T) and K (T+) shall be in accordance with MIL-PRF-38534. Inspections to be performed shall be those specified in MIL-PRF-38534 as implemented by BAE SYSTEMS approved Quality Management (QM) plan. The TCI requirements for each particular device type manufactured to this drawing shall be as specified in section 1.2 herein. 4.3.1 Qualification Testing Requirements are defined in Table 8 on sheet 29.
4.4
Quality Conformance Inspection (QCI)
Quality conformance inspection shall be implemented as specified in BAE SYSTEMS specification MANSTC-Q002.
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Table 8. Qualification Testing Requirements

Group A1-3,7-11 B1 B2 B3 B4 B5c B6 B7 B8 Description 100% Electrical Test Test Method per TLD Condition 3 temp Sample 100% Min Part Rqmts Full Screen Notes
Physical Dimensions PIND Resistance to Solvents Internal Visual Bond Strength Die Shear Solderability Seal -- Fine -- Gross ESD External Visual PIND Temperature Cycle Constant Acceleration
and/or Mechanical Shock
883 TM 2016 883 TM 2020 883 TM 2015 883 TM 2014 883 TM 2011 883 TM 2019 883 TM 2003
A A, B and D D (wirebond) or F (flip chip) solder temp +245+/-5C A C Group A-1 A, 5 passes C, 100 cycles B (10K G), Y1 and Y2 direction C (3000 G), 6 axes A and C A, 1 pass room temp 1000hrs at +125C 3 temp < 5000ppm
2 (0) 15 (0) 3 (0) 1 (0) 2 (0) 2 (0) 1 (0) 15 (0)
Elect. Rejects Elect. Rejects Elect. Rejects Elect. Rejects Elect. Rejects
MCM MCM MCM MCM MCM
Elect. Rejects MCM Elect. Rejects MCM Elect. Rejects MCM
B9 C1a C1b C1c C1e
883 TM 1014 883 TM 1014 883 TM 3015 883 TM 2009 883 TM 2020 883 TM 1010 883 TM 2001 883 TM 2002 883 TM 1014 883 TM 2020 883 TM 1010/2009 per TLD 883 TM 1005 per TLD 883 TM 1018 at +100C 883 TM 2014 883 TM 2011 (wirebond) or 2019 883 TM 1011 883 TM 1008 883 TM 2004
3 (0) + 2 setups 5 (0) " " " " " " " " 77 (1) 3 (0) 2 (0) 2 (0) 5 (0) 5 (0) 1 (0) 5 (0)
room temp good SCM Full Screen Full Screen Full Screen Full Screen MCM MCM MCM MCM
Full Screen MCM Full Screen Full Screen Full Screen Full Screen MCM MCM MCM MCM 1/
C1f C1g C1i C1j C2a C2b C3 C4a C4b D1a D1b D1c D1d
Seal (fine and gross) PIND Visual Examination End Point Electrical Steady-state Life Test End Point Electrical Internal water vapor Internal Visual Wirebond strength/Element shear Thermal Shock Stabilization Bake Lead Integrity Seal -- Fine -- Gross Moisture Resistance Salt Atmosphere Total Ionizing Dose
Full Screen SCM Full Screen SCM from C1 from C3 from C4a Elect. Rejects MCM
C +150C, 24 hours B2 (lead fatigue), 15 leads min A C A
2/
D2 D3 E2
883 TM 1014 883 TM 1014 883 TM 1004 883 TM 1009 883 TM 1019 at 25C
5 (0) 5 (0) 22(0)+1 (Initial qual); 5(0)+1 (periodic QCI) 5(0)+1 (Initial qual) Full Screen SCM
E4
Single Event Phenomena
ASTM F1192 at 110C
Full Screen SCM
Notes: 1/ Life test may substitute 20 4-high stack MCMs in place of 77 single chip modules. Electrical readouts are tested at 0, 168. 504 and 1000 hours. 2/ Sealed empty MCM packages may be used for Group D. These packages must follow the screening and handling flows for flight hardware but electrical test is not required.
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Table IIA. Electrical Test Requirements

Test Requirements 3/ Qualification Level: Subgroups 1/, 5/ (In accordance with MIL-STD-883 and MAN-STC-Q002) Commercial Space modified Class K (T+)
(251A172-xx7)
Commercial Space modified Class H (T)

(251A172-xx9)
Prototype
(251A172-xx2)
Engineering
(251A172-xx3)
Interim electrical parameters Final electrical parameters Group A test requirements Group C1 end-point electrical parameters 4/ Group C2 end-point electrical parameters 4/ Group E end-point electrical parameters 4/
1, 7, 9 1-3, 7-11 2/ 1-3, 7-11 1, 7, 9 1-3, 7-11 1, 7, 9
1, 7, 9 1-3, 7-11 2/ 1-3, 7-11 1, 7, 9 1-3, 7-11 1, 7, 9 1-3, 7-11 1, 7, 9
Notes: 1/ Blank spaces indicate tests are not applicable. 2/ PDA applies to subgroups 1 and 7. 3/ Qualification level is defined per section 1.2 herein. 4/ Group A electrical test subgroups applied after applicable Group C, D, and E tests are completed. 5/ Group A electrical test subgroups: Subgroup Parameters 1 Static tests at +25C 2 Static tests at maximum rated operating temperature 3 Static tests at minimum rated operating temperature 4 Dynamic tests at +25C 5 Dynamic tests at maximum rated operating temperature 6 Dynamic tests at minimum rated operating temperature 7 Functional tests at 25C 8a Functional tests at maximum rated operating temperature 8b Functional tests at minimum rated operating temperature 9 Switching tests at +25C 10 Switching tests at maximum rated operating temperature 11 Switching tests at minimum rated operating temperature
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4.5
Burn-in Circuit
The applicable burn-in stresses are as specified below and are required per BAE SYSTEMS specification MAN-STC-Q002 and section 1.2 herein. 4.5.1 Stress Methodology
For Dynamic burn-in, all possible addresses are written with alternating High and Low data. All I/O pins specified in the dynamic burn-in pin lists are driven through individual series resistors (1.6K +/10%). Burn-in voltages are defined using the following notation: Pre-Burnin and Accelerated Voltage Levels: Vin(0): Vin(1): V1: V2: Vsx: 0.00 V to +0.40 V +3.65 V to +4.00 V +3.00 V (-0%/+0.100V) +3.75 V (-0%/+0.100V) Float or GND VIL= LOW level for all programmed signals VIH = HIGH level for all programmed signals All VDD pins are tied to this level All VDD2 pins are tied to this level All GND pins are tied to this level
Burnin Voltage Levels: Vin(0): Vin(1): V1: V2: Vsx: 0.00 V to +0.40 V +3.50 V to +3.85 V +2.70 V (-0%/+0.100V) +3.60 V (-0%/+0.100V) Float or GND VIL= LOW level for all programmed signals VIH = HIGH level for all programmed signals All VDD pins are tied to this level All VDD2 pins are tied to this level All GND pins are tied to this level
The burn-in circuit diagram is shown in Figure 9 on sheet 32. 4.5.2 Dynamic Burn-in
Pin Listing: The dynamic burn-in pin listing is shown below. F = square wave, 100 KHz to 1.0 MHz. Input A0 A1 A2 A3 A4 A5 Signal F/2 F/4 F/8 F/16 F/32 F/64 Input A6 A7 A8 A9 A10 A11 Signal F/128 F/256 F/512 F/1024 F/2048 F/4096 Input A12 A13 A14 A15 A16 A17 Signal F/8192 F/16384 F/32768 F/65536 F/131072 F/262144 Input A18 W DQ0..31 S G LS = LD Signal F/524288 F/1048576 F/2097152 F VIL GND
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V1 C1 _ S
LS/LD R R R R R
C1 = 0.1 F(10%) R = 1.6K ( 10% )

R
V1 C1 _ S
LS/LD R R R R R
C1 = 0.1 F(10%) R = 1.6K ( 10% )

R
DQ0
DQ8
_ W _ G
512Kx8 SRAM R
DQ7
_ W _ G
512Kx8 SRAM R
DQ15
A0
A0
A18
A18
V1 C1 _ S
LS/LD R R R R R
V1
C1 = 0.1 F(10%) R = 1.6K ( 10% )

R
C1 = 0.1 F(10%) R = 1.6K ( 10% )
C1 _ S
LS/LD R R R R R
DQ16
DQ24
_ W _ G
512Kx8 SRAM R
DQ23
_ W _ G
512Kx8 SRAM R
DQ31
A0
A0
A18
A18
Figure 9. Burn-in Circuit Diagram for each SRAM die
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5 Packaging/Shipping
5.1 Packaging/Shipping Requirements
All deliverable hardware shall be handled, stored and packaged to properly identify the item, to prevent handling damage and to protect against electrostatic damage. Proper ESD control procedures shall be followed. The requirements for packaging/shipping shall be in accordance with BAE SYSTEMS specification MANSTC-Q001.
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Table 9. Terminal Connections for 512K x 32 MCM in 84-FP

Package Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Package Signal LS0 A10 A8 A2 A0 /OE /WE VDD GND DQ8 (U2) DQ9 (U2) N/C (U3) N/C (U3) DQ20 (U5) GND VDD2 DQ21 (U5) DQ0 (U1) DQ1 (U1) DQ24 (U4) DQ25 (U4) GND DQ26 (U4) DQ27 (U4) DQ2 (U1) DQ3 (U1) DQ22 (U5) VDD2 GND DQ23 (U5) N/C (U3) N/C (U3) DQ10 (U2) DQ11 (U2) GND VDD A4 A6 A18 A16 A14 LD0 Package Pin 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 Package Signal LS1 A12 A11 A9 A3 A1 /CS VDD GND DQ15 (U2) DQ14 (U2) N/C (U3) N/C (U3) DQ19 (U5) GND VDD2 DQ18 (U5) DQ7 (U1) DQ6 (U1) DQ31 (U4) DQ30 (U4) GND DQ29 (U4) DQ28 (U4) DQ5 (U1) DQ4 (U1) DQ17 (U5) VDD2 GND DQ16 (U5) N/C (U3) N/C (U3) DQ13 (U2) DQ12 (U2) GND VDD A5 A7 A17 A15 A13 LD1
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Notes: 1/ /CS = S = Chip Select Bar /WE = W = Write Enable Bar /OE = G = Output Enable Bar LD0-LD1 = Decoder Programming LS0-LS1 = Decoder Selects A0-A18 = Address Inputs DQ0-DQ31 = Data Input/Outputs VDD = 2.5V Core Power VDD2 = 3.3V I/O Power GND = Ground N/C = No Connect 2/ See Table 4 on sheet 13 for the truth table.
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REVISIONS

Refer to Document Change History Herein

Part Number - See Tabulation

9300 Wellington Road Manassas, VA 20110

MCM, CMOS, 2.5V/3.3V, SRAM, 512Kx32, STACKED, OPT

CAGE CODE 1RU44 REV A

DWG NO. 251A172 SHEET 2 of 35

2.5V/3.3V 512Kx32 SRAM MCM

CAGE CODE 1RU44 REV A

DWG NO. 251A172 SHEET 3 of 35

2.5V/3.3V 512Kx32 SRAM MCM

Document Change History

CAGE CODE 1RU44 REV A

DWG NO. 251A172 SHEET 4 of 35

2.5V/3.3V 512Kx32 SRAM MCM

BAE SYSTEMS Part Number and Identification

Section Number Part Number 251A172-412 A 412

Limits not guaranteed

251A172-412 Prototype (USA) datecd

Prototype flow with accelerated burn-in conditions Engineering flow

Limits not guaranteed

251A172-413 Engineering (USA) datecd

251A172-417 Pre-qualified (USA) datecd

251A172-419 Pre-qualified (USA) datecd

Limits not guaranteed

251A172-422 Prototype (USA) datecd

Limits not guaranteed

251A172-423 Engineering (USA) datecd

CAGE CODE 1RU44 REV A

DWG NO. 251A172 SHEET 5 of 35

2.5V/3.3V 512Kx32 SRAM MCM

Part Marking Requirements 1/

Section Number Part Number 251A172-427 A 427

251A172-427 Pre-qualified (USA) datecd

251A172-429 Pre-qualified (USA) datecd

Module Assembly DWG. No. 512Kx8 SRAM die

Capacitors (Low Inductance decoupling Capacitor Arrays), 100nF

Only -xx2, -xx3 All

CAGE CODE 1RU44 REV A

DWG NO. 251A172 SHEET 6 of 35

2.5V/3.3V 512Kx32 SRAM MCM

Absolute Maximum Ratings

Table 2. Absolute Maximum Ratings

CAGE CODE 1RU44 REV A

DWG NO. 251A172 SHEET 7 of 35

2.5V/3.3V 512Kx32 SRAM MCM

Recommended Operating Conditions

Table 3. Recommended Operating Conditions

CAGE CODE 1RU44 REV A

DWG NO. 251A172 SHEET 8 of 35

2.5V/3.3V 512Kx32 SRAM MCM

BAE SYSTEMS Documentation

CAGE CODE 1RU44 REV A

DWG NO. 251A172 SHEET 9 of 35

2.5V/3.3V 512Kx32 SRAM MCM

Design, Construction, and Physical Dimensions

CAGE CODE 1RU44 REV A

DWG NO. 251A172 SHEET 10 of 35

2.5V/3.3V 512Kx32 SRAM MCM

2.5V/3.3V 512Kx32 SRAM MCM

Bulk Silicon Chip 2X Places per side

Gold Ball Wire Bond

Figure 2. Case Outline: 84-lead FP Package Cross Section