A PRACTICAL TRAINING SEMINAR REPORT ON

VHDL AND FPGA DESIGNING TAKEN AT PRIGANIK TECHNOLOGIES Pvt. Ltd., JAIPUR
Submitted in Partial Fulfillment for the Award of Bachelor of Technology Degree Of Rajasthan Technical University, KOTA

From 01/06/13 to 15/07/13 Session: - 2013-2014 Submitted to: Mr. Manish Singhal MS. SMRITI SACHAN (ECE, PCE) Submitted By: VIVEK KUMAR JHA IV YEAR ECE (EC/10/1101)

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING POORNIMA COLLEGE OF ENGINEERING ISI-6, RIICO INSTITUTIONAL AREA SITAPURA, JAIPUR-302022 (RAJASTHAN)

ACKNOWLEDGEMENT
I take this opportunity to express my profound gratitude and deep regards to my guide (Mr. Manish Singhal, Ms. Smriti Sachan) for their exemplary guidance, monitoring and constant encouragement throughout the course of this report. The blessing, help and guidance given by them time to time shall carry me a long way in the journey of life on which I am about to embark. I also take this opportunity to express a deep sense of gratitude to Mr. Gaurav Jindal, Application Development Engineer, Priganik Technologies Pvt. Ltd., for his cordial support, valuable information and guidance, which helped me in completing this task through various stages. I am obliged to staff members of Priganik Technologies Pvt. Ltd., for the valuable information provided by them in their respective fields. I am grateful for their cooperation during the period of my assignment. Lastly, I thank almighty, my parents and friends for their constant encouragement without which this assignment would not be possible.

VIVEK KUMAR JHA (EC/10/1101)

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PREFACE
This report is the summarization of the concepts and practical knowledge that I have learnt during my summer training program. In this project report, I have included various concepts used in the VLSI designing using VHDL and the working of the Programmable Logic Devices. In addition to that. This report also includes the details of the Institution from where I did my summer training. Additionally, the report also summarizes the details of the EDA Company Mentor Graphics, comprising of its marketing policy and the areas of its working. Doing this Project report helped me to enhance my knowledge regarding a frontier company in the field of Semiconductor and brushed up my concepts learnt during summer training. Through this report I also came to know about role of devotion towards the work.

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TABLE OF CONTENTS

Certificate-college....ii Certificate-Log Book...iii Certificate-Company...iv Acknowledgement....v Preface..vi Table of contents vii List of Tablesix List of Figuresx

Chapter 1 Introduction
1.1. 1.2. 1.3. 1.4. 1.5. 1.6. 1.7. Introduction Background of the company Organizational structure Nature of the business Products Market strength Conclusion

1-6

Chapter 2 Organization Infrastructure

2.1. 2.2. Priganik Technology Pvt. Ltd. Mentor Graphics

7-23

Chapter 3 Training Attended

3.1. 3.2. 3.3. 3.4. Introduction Features Capabilities of VHDL Design flow

24-34

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3.5. 3.6. 3.7. 3.8. 3.9. 3.10. 3.11.

Program structure Types and Constants Libraries and Packages Structural design elements Dataflow design elements Behavioral design elements Conclusion

Chapter 4 Project Development

4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.7. 4.8. Introduction FPGA CPLD System analysis Project description Project development Project testing Conclusion

35-43

Chapter 5 Conclusion
5.1. 5.2. Future Prospects of VHDL Conclusion

44-45

Annexure 46

References.53

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LIST OF TABLES

Table No.
2.1 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10

Particulars Authority figures of Mentor Graphics VHDL code example Entity declaration Architecture declaration Type declaration Array declaration Package declaration Port mapping syntax Component declaration When-Else syntax Behavioral Modelling

Page No.
16 28 28 29 30 30 31 32 32 33 33

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LIST OF FIGURES

Fig. No.
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8

Particulars Priganik Logo Functional Block of CPLD CPLD Functional block diagram of FPGA FPGA Office of Mentor Graphics at Oregon, USA Office of Mentor Graphics at Hyderabad Office of Mentor Graphics at Noida 2*16 Character LCD Interfacing of Character LCD with FPGA Circuit Diagram of Character LCD Interfacing with FPGA 7 Segment Display Interfacing with FPGA DIP Switch Functional block of ALU Xilinx Webpack Modelsim Simulator

Page No.
7 12 12 13 13 16 17 18 37 37 37 38 38 40 41 42

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CHAPTER 1 INTRODUCTION
____________________________________________________________________________

1.1. Introduction
Priganik Technologies Pvt. Ltd. is an efficient Electronics Training and Development company, working towards the best career prospect of the growing engineers.

PRIGANIK offers a wide spectrum of technical courses and application courses designed to suit every skill level, as well as the ability to consult directly with organizations to tailor made learning plans for any number of employees. Our products and services have a wide appeal and are applicable to those in varied positions including embedded design engineer, embedded developer, systems architects, test engineers, software developers, help desk staff, IT managers, senior executives, administrative assistants and business professionals. Priganik Technologies with its foundation pillars as Innovation, Information and Intelligence is exploring indefinitely as a Technology service provider and as a Training Organization. ____________________________________________________________________________

1.2. Background of the company

Priganik Technologies was started by a group of entrepreneurs with a sole mission of establishing a dedicated Research & Development Cell and bringing the findings to the benefit of budding Engineers, little did they know that their efforts will bring an enormous change in the world of technology & training. Today in just two years of its existence, Priganik Technologies has a pan India acclaim for its unmatched quality services. ____________________________________________________________________________

Vision:
Our Roadmap starts with our mission, which is enduring. It declares our purpose as a company and serves as the standard against which we weigh our actions and decisions.

Mission:

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To promote Technical education in India and Abroad. To create value and make a difference in the field of education. To provide sustainable, advanced technology solutions and services to our clients.

Our vision serves as the framework for our Roadmap and guides every aspect of our business by describing what we need to accomplish in order to continue achieving sustainable and quality growth. ___________________________________________________________________________

1.3 Organizational Structure

The company is a private enterprise and comes under the private sector. The company has its own board of members and has its branches at Jaipur, Bangalore and Pune. It is basically a service provider and its R&D centre is at Bangalore. ____________________________________________________________________________

1.4 Nature of the Business:

The company basically works as a Technology service provider and as a Training Organization. Multi domains in which Priganik Technologies operate include the following:

Research & Development: With a 24X7 work in Research & Development Cells & Our research
efforts have also dwelt into projects on VLSI FPGA Design, ASIC Design, and Verification, Robotics/Embedded kit Manufacturing, Circuit Designing and Layout Designing.

Technical Workshops & Seminars: On the journey to share its expertise with budding engineers,
Priganik has come across 10000 + students. The different themes of these workshops have been VLSI Design, FPGA Design, Advance Embedded System, Robotics and many of its kind in top notch colleges.

Training Programs: Vacations have never been this fun! Priganik organizes Summer Trainings
and Internships on Embedded Systems & VLSI Design, FPGA Design, LabVIEW, and MATLAB for the students to get an edge above the others.

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_________________________________________________________________ 1.5. Products:

The company comes under service sector and provides training and provides workshop facilities in the following arenas. Modelsim Xilinx-ISE navigator Quartus-II Keil compiler Proteus simulator Top view simulator AVRstudio-4 WinAVR AVRdude Matlab Multisim and Ultiboard Lab view Matlab Tanner Tools

_________________________________________________________________________

1.5.1. MATLAB:
Historical background, Applications, Scope of MATLAB, Importance of MATLAB for Engineers, Features, MATLAB Windows (Editor, Work Space, Command History, Command Window), Operations with Variables, Naming and Checking Existence, Clearing Operations, Introduction to Arrays and MATLAB File Types. ____________________________________________________________________________

1.5.2. Robotics:
Robotics is a field that covers almost all the spheres of technology, whether it is Mechanical, Electronics, Computer Programming, Designing Techniques or any other technical skills based on respective applications. This is basically a micro controller based robotic workshop which gives an exposure about the autonomous robotics to the students. As this field is leading to
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introduce a creative era of innovation around us, the basic motto of our team is to initiate the spark of robotics to a higher extent. These projects focus on the application and use of technology rather than their internal working so that a person can grasp the concepts well.

____________________________________________________________________________

1.5.3. Spice Stimulation:

Simulation Program with Integrated Circuit Emphasis, or SPICE, has been used for over thirty years. The original implementation of SPICE was developed at the University of California Berkeley campus in the late 1960s. SPICE was developed largely as a derivative of CANCER (Computer Analysis of Nonlinear Circuits, Excluding Radiation) also developed by UC Berkeley.

______________________________________________________________________ 1.5.4 Verilog-Hdl:

Hardware description languages such as Verilog differ from software programming languages because they include ways of describing the propagation of time and signal dependencies (sensitivity). There are two assignment operators, a blocking assignment (=), and a non-blocking (<=) assignment. The non-blocking assignment allows designers to describe a state-machine update without needing to declare and use temporary storage variables. ____________________________________________________________________________

1.5.5 Microcontroller Training:

The Intel 8051 is an 8-bit microcontroller, which means that most available operations are limited to 8 bits. There are 3 basic sizes of the 8051: Short, Standard, and Extended. The Short and Standard chips are often available in DIP (dual in-line package) form, but the Extended 8051 models often have a different form factor, and are not drop-in compatible.

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____________________________________________________________________________

1.5.6. VHDL Training: HDL(Hardware Description Language) based design has established itself as the modern approach to design of digital systems, with VHDL (VHSIC Hardware Description Language) and Verilog HDL being the two dominant HDLs. Numerous universities thus introduce their students to VHDL (or Verilog). The problem is that VHDL is complex due to its generality. Introducing students to the language first, and then showing them how to design digital systems with the language, tends to confuse students. The language issues tend to distract them from the understanding of digital components. And the synthesis subset issues of the language add to the confusion. VHDL is for writing models of a system. Reasons for modeling: 1. Requirements specification 2. Documentation 3. Testing using simulation 4. Formal verification 5. Synthesis Goal: 1. Most reliable design process, with minimum cost and time 2. Avoid design errors ______________________________________________________________________ 1.5.7 PCB Design:
Types of PCBs, Machines used for designing and The Designing Process. ____________________________________________________________________________

1.5.8 Labview Application Software Package:

LabVIEW is system design software that provides engineers and scientists with the tools needed to create and deploy measurement and control systems through unprecedented hardware integration. LabVIEW inspires you to solve problems, accelerates your productivity, and gives you the confidence to continually innovate.
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____________________________________________________________________________

1.5.9 PIC Microcontroller:

The PIC microcontroller was developed by General Instruments in 1975. PIC was developed when Microelectronics Division of General Instruments was testing its 16-bit CPU CP1600. Although the CP1600 was a good CPU but it had low I/O performance. The PIC controller was used to offload the I/O the tasks from CPU to improve the overall performance of the system. ___________________________________________________________________________

1.5.10 Other Products and Services offered:

Ethical Hacking & Cyber Security and FPGA Designing. ____________________________________________________________________________

1.6. Market strength:

The company provides an opportunity to appear in the Placement Drives of reputed MNCs. PRIGANIK being an old renowned Organization, its Training Certificates are recognized emphatically and accepted worldwide. It also provides separate Certificate for project work on company letter head, after completion of the project. PRIGANIK is registered as a Pvt. Ltd. Company under the Companies Act 1956 and approved body by Ministry of Corporate Affairs (MCA), Govt. of India and the Training provided by PRIGANIK is be considered as the compulsory vocational/industrial training as per the universities course curriculum.

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CHAPTER- 2 COMPANY INFRASTRUCTURE: 2.1. PRIGANIK TECHNOLOGIES _________________________________________________________________

2.1.1. Introduction
PRIGANIK offers a wide spectrum of technical courses and application courses designed to suit every skill level, as well as the ability to consult directly with organizations to tailor made learning plans for any number of employees.

Fig 2.1. Priganik Logo ____________________________________________________________________________

2.1.2. Department Structure

For the smooth running of the company the overall load is distributed among various departments. These departments serve as the building blocks which work individually. They can be broadly classified into the following departments. In House training: The institute provides the training on various domains at the institute itself to the students. It has different halls for the lecture purpose and the lab practical implementations. The lab contains ample amount of Personal computers and various kits such as that of FPGA, CPLD and 8051 Microcontroller kits. In addition to the hardware modules being provided by the institute itself, it also provides the software needed for the implementation of the hardware.

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Summer/Winter training: Students are also given summer internship and training for their pre-final year summer training program. Priganik is an ISO registered institute and hence its training certificate is accepted anywhere if concerned. The students have options of choosing over more than 10 different technologies for their summer training program. For each program, a set of modules is set and various classrooms lectures are given to the students. The internship also includes the working on a particular project related to that specific technology.

Industrial training: The students on the completion of their Graduate or Post Graduate courses are expected to gain experience in a technical field according to the present condition of the market. As the institute keeps upgrading its training modules according to the market scenario, consequently it also helps in delivering a decent Industrial training to the concerned student.

Faculty training: From time to time, the faculties of different colleges also have to get training on different recent technologies and the Institute also works on the same to provide the training to the faculties at the institute or at the college campus itself.

College workshop: Priganik also conducts workshops at different colleges for delivering lectures on any particular topic as requested by the college itself.

Corporate training: Apart from all its work in the field to educating students and faculties in colleges and universities, the clients of Priganik are also from the corporate world.

____________________________________________________________________________

2.1.3. Network structure

Its been 2 years since the company was establish and is progressing with a fast speed. The company has its head office in Jaipur where various training programs are conducted and the

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Bangalore branch is the R&D centre of the company. One more training zone of the company is in Pune.

_________________________________________________________________
2.1.4. Software and hardware:
The company needs a variety of hardware and software for its motive to train others. These include software such as: Modelsim: ModelSim is a powerful simulator that can be used to simulate the behavior and performance of logic circuits. The simulator allows the user to apply inputs to the designed circuit, usually referred to as test vectors, and to observe the outputs generated in response to inputs given.

Xilinx-ISE navigator: This software provides the work environment for the development of the code in Hardware Description Languages such as VHDL. It supports two hardware description languages, VHDL and Verilog. It also supports the integration of various simulation tools into itself.

Quartus-II: Quartus II is a software tool produced by Altera for analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer. The latest version is 13sp1 which is a service pack of version 13.

Keil compiler: Keil development tools for the 8051 Microcontroller Architecture support every level of software developer from the professional applications engineer to the student just learning about embedded software development. Proteus simulator: Proteus is software for microprocessor simulation, schematic capture, and printed circuit board (PCB) design. It is developed by Labcenter Electronics.

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Top view simulator: Topview Simulator gives an excellent simulation environment for the industry's most popular 8 bit Microcontroller family, MCS 51. It gives required facilities to enable the system designers to start projects right from the scratch and finish them with ease and confidence. It is the total simulation solution giving many state of art features meeting the needs of the designers possessing different levels of expertise.

AVRstudio-4: The AVR Studio 4 is an Integrated Development Environment for debugging AVR software. The AVR Studio allows chip simulation and in-circuit emulation for the AVR family of microcontrollers. The user interface is specially designed to be easy to use and to give complete information overview. The AVR uses the same user interface for both simulation and emulation providing a fast learning curve.

WinAVR: WinAVR (tm) is a suite of executable, open source software development tools for the Atmel AVR series of RISC microprocessors hosted on the Windows platform. Includes the GNU GCC compiler for C and C++.

AVRDUDE: AVRDUDE is a utility to download/upload/manipulate the ROM and EEPROM contents of AVR microcontrollers using the in-system programming technique (ISP).

Mplab: It is a 32-bit application on Microsoft Windows and includes several free software components for application development, hardware emulation and debugging. MPLAB IDE also serves as a single, unified graphical user interface for additional Microchip and third-party software and hardware development tools.

Both Assembly and C programming languages can be used with MPLAB IDE v8. Others may be supported through the use of third-party programs.

Multisim and Ultiboard: Multisim is an industry-standard, best-in-class SPICE simulation environment. It is the cornerstone of the NI circuits teaching solution to build expertise through practical application in designing, prototyping, and testing electrical
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circuits. The Multisim design approach helps you save prototype iterations and optimize printed circuit board (PCB) designs earlier in the process.

Lab view: LabVIEW (short for Laboratory Virtual Instrument Engineering Workbench) is a system-design platform and development environment for a visual programming language from National Instruments. The graphical language is named "G" (not to be confused with G-code). Originally released for the Apple Macintosh in 1986, LabVIEW is commonly used for data acquisition, instrument control, and industrial automation on a variety of platforms including Microsoft Windows, various versions of UNIX, Linux, and Mac OS X. The latest version of LabVIEW is LabVIEW 2013, released in August 2013.

Matlab: MATLAB is a high-level language and interactive environment for numerical computation, visualization, and programming. Using MATLAB, you can analyze data, develop algorithms, and create models and applications. The language, tools, and builtin math functions enable you to explore multiple approaches and reach a solution faster than with spreadsheets or traditional programming languages, such as C/C++ or Java.

Tanner Tools: Tanner EDA provides a complete line of software solutions that catalyze innovation for the design, layout and verification of analog and mixed-signal (A/MS) integrated circuits (ICs). One of the training zones at Jaipur has about 10 personal computers and 10 CPLD and FPGA hardware kits and all those hardware parts required for circuit designing on PCB.

Following are some of the hardware kits available at the institute for the practical implementation of the technologies such as VHDL and VERILOG. CPLD: Complex Programmable Logic Devices (CPLDs) are exactly what they claim to be. Essentially they are designed to appear just like a large number of PALs in a single chip, connected to each other through a crosspoint switch. They use the same development tools and programmers, and are based on the same technologies, but they

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can handle much more complex logic and more of it. The devices are programmed using programmable elements that, depending on the technology of the manufacturer, can be EPROM cells, EEPROM cells, or Flash EPROM cells.

Fig 2.2. Functional Block of CPLD

Fig 2.3. CPLD

FPGA: Field Programmable Gate Arrays are called this because rather than having a structure similar to a PAL or other programmable device, they are structured very much

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like a gate array ASIC. This makes FPGAs very nice for use in prototyping ASICs, or in places where and ASIC will eventually be used. For example, an FPGA may be used in a design that need to get to market quickly regardless of cost. Later an ASIC can be used in place of the FPGA when the production volume increases, in order to reduce cost. Each FPGA vendor has its own FPGA architecture, but in general terms they are all a variation. The architecture consists of configurable logic blocks, configurable I/O blocks, and programmable interconnect. Also, there will be clock circuitry for driving the clock signals to each logic block, and additional logic resources such as ALUs, memory, and decoders may be available. The two basic types of programmable elements for an FPGA are Static RAM and anti-fuses.

Fig 2.4. Functional block diagram of FPGA

Fig 2.5. FPGA

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____________________________________________________________________________

2.1.5 Available Plans/ strategies:

The company is working hard to achieve greater heights and to earn mare respect in market. For this it has undertaken several policies. Moreover it follows some strategies to increase its strength, such as: It provides separate Certificate for project work on company letter head, after completion of the project and also certificate of Honor & a trophy exclusively to the Best Trainee in each Batch. It provides a learning kit to all the enrolled students, comprising a Book and PRIGANIK Campus Placement Preparation materials in CD. Once after becoming a part of PRIGANIK Family, student get a Membership Card worth equivalent to $14 free of cost, through which the candidate can participate in placement drives, can revise the same course of similar fee and number of other benefits for one year & they can renew it after one year. Flexible system is provided for opting batch date that is Batch Dates once selected may be changed prior to 7 days of starting of the batch. After successful completion of the training, interested trainees are provided Live Projects undergoing at our development Cell.

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____________________________________________________________________________

2.2. MENTOR GRAPHICS

____________________________________________________________________________

2.2.1. INTRODUCTION
Mentor Graphics Corporation, founded in 1981, is a technology leader in electronic design automation (EDA), providing software and hardware design solutions that enable companies to develop better electronic products faster and more cost-effectively. The companys common stock trades on the NASDAQ National Market under the ticker symbol MENT. Its corporate headquarters are located in Wilsonville, Oregon, USA; San Jose, California, USA; and Manchen, Germany. Active within the embedded software industry, Mentor Graphics engages in the development of EDA software and systems for electrical engineering and electronics. In other words, the company offers EDA solutions for both the hardware components (chips and boards) and the software components (the embedded operating systems and applications/drivers that control the products operation). It delivers products and services worldwide, principally to companies in the communications, computer, consumer electronics, and semiconductor, networking, multimedia, military/aerospace and transportation industries. Its products, which are used in designing and developing a set of electronic products, are categorized into the following design areas: Electronic System Level Design, Embedded Systems, Intellectual Property, IC (Integrated Circuit) Nanometer Design, Scalable Verification, PCB (Printed Circuit Board) Systems, FPGA/PLD (Field Programmable Gate Array/Programmable Logic Device), DesignFor-Test (DFT), System Modeling, Electrical System Design and Harness Engineering, and Vehicle Network Design. Through its network of worldwide office locations, Mentor Graphics has a global presence in Canada, the Benelux region (Belgium, the Netherlands and Luxembourg), the United Kingdom, France, Germany, Hungary, Israel, Italy, Spain, Switzerland, China, India, Korea, Singapore, Taiwan and Japan.

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Fig 2.6. Office of Mentor Graphics at Oregon, USA ____________________________________________________________________________

2.2.2. DEPARTMENT STRUCTURE

Mentor Graphics works are mostly divided into 2 departments. The R&D department works in the area of developing and innovating new products while the other one is the customer support center which also handles the sales and services of the company.

Table 2.1. Authority figures of Mentor Graphics

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In India, Mentor Graphics has its offices at Hyderabad, Noida and Bangalore.

Bangalore: Mentor Graphics India sales team provides sales and support to customers throughout the Southern Asia region. Working closely with our corporate resources in Singapore, we are well positioned to provide our customers with world-class Mentor tools, technology, and support.

Hyderabad: Mentor Hyderabad is a Corporate R&D center of Mentor Graphics Corporation. The focus areas for research and development are PCB Systems, Electrical Design and Harness Engineering, Hardware/Software Co-Verification, Physical Design and Verification, and Design-For-Test.

Fig 2.7. Office of Mentor Graphics at Hyderabad The Hyderabad center is involved in following areas: PCB Systems Mentor Hyderabad is primarily involved in software development for Mentors Printed Circuit Board (PCB) tools. The development activities support a number of tools ranging from Schematic Capture and Netlisters, to Layout and Manufacturing preparation. Cabling and Harness Systems : Mentor Hyderabad is heavily involved in the development of several products of Mentors Cabling and Harness tools the CHS suite. CHS is data centric and integrates multiple products through a common data system.

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Design-for-Test (DFT) The DFT group at Mentor Hyderabad is responsible for the development of Boundary Scan Design Architect, a tool that generates IEEE 1149.1 compliant boundary circuitry. The group is also responsible for Quality Assurance of all Mentor DFT Tools. Co-Verification Mentor Hyderabad is involved in development activities for Seamless, a co-verification tool that enables users to verify hardware/software interfaces, accelerate the debug of firmware and analyze the performance of the system. Physical Design and Verification Mentor Hyderabad is involved in the development of interfaces for Mentors Physical verification tools to interact with various IC design databases.

Bangalore: Mentor NOIDA is a Corporate R&D center of Mentor Graphics Corporation. The focus area for research and development in Noida is Scalable Functional Verification, advanced FPGA synthesis, Debug Tools with advanced Graphical User interface ?and HDL Language compilers for various EDA tools.

Fig 2.8. Office of Mentor Graphics at Noida The R&D team in Mentor Noida is actively working on developing tools and technologies in the Scalable Functional verification space. It is engaged in development of various aspects of Questa

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Verification Software (multi-language single kernel Verification platform offering simulation, assertion, formal and unified coverage collection tools) and in Hardware Acceleration solutions for RTL (compilers and run-time). Mentor Noida is also pioneer in bringing the second and third generation of CoModeling technology (SCE-MI standards) for accelerating transaction level C testbenches. SCE-MI based testbench modeling allows testbenches to be written at a much higher level of abstraction where the untimed portion of the testbench can be written in C/VC++ and the timed portion can be written in XRTL (an enhanced RTL subset) System Level Verification. Some patents have been applied in this area from Mentor NOIDA. Using the same SCEMI technology, higher performance simulation acceleration is achieved for traditional event-based simulations of HDL testbenches. Mentor Noida is actively involved in developing RTL synthesis and optimization technologies for FPGA devices. Every year, FPGA design starts are increasing and there is a large number of FPGA device families in the market. Most of the new FPGA devices come with a wide variety of complex embedded dedicated functional blocks, making the task of synthesis tool more complex. Mentor NOIDA is actively working on advanced optimizations in RTL Synthesis including "technology-aware RTL synthesis" as well as technology mapping to various FPGA families. ____________________________________________________________________________

2.2.3. NETWORK STRUCTURE

The company has its worldwide reach to countries like Japan, America, Europe and Pacific Rim. Every country has its regional offices serving as either as the sales and services department or the research and development department. In India, the company has its network at Hyderabad, Noida and Bangalore. ____________________________________________________________________________

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2.2.4. HARDWARE AND SOFTWARE

Mentor Graphics provides software and hardware design solutions that enable companies to develop better electronic products faster and more cost-effectively. They offer innovative products and solutions that help engineers overcome the design challenges they face in the increasingly complex worlds of board and chip design. Some of the noted products of the company are as follows:

Electrical & Wire Harness Design

Electronic System Level Design: Design complexity of next-generation digital applications is outgrowing the capabilities of current design methods. Increasingly, designs are large systems that include embedded cores, IP, and complex signal processing hardware that implements computationally intensive algorithms. To deal with this complexity, Mentor Graphics offers the EDA industrys most comprehensive suite of electronic system level (ESL) design tools for hardware creation. Vista, a System C debug environment, helps designers model their designs at a higher level of abstraction where they can identify and resolve problems with minimal effort.

Embedded Software: Most electronics products today are a synthesis of hardware design and embedded software, and the embedded software is the main differentiator for product functionality and performance. As a result, embedded software has increased dramatically in electronic systems design. Mentor Graphics is the only EDA Company to offer design solutions for embedded software.

FPGA: As ICs, ASICs (application-specific integrated circuits) and FPGAs (field-programmable gate arrays) become more complex and printed circuit board (PCB) fabrication technology advances to include embedded components and high-density interconnect layers, the design of PCBs is reaching new levels of complexity. These are frequently a source of design bottlenecks.

Functional Verification: Mentor Graphics provides its customers with critical tools for solving the increasingly complicated problems of verifying that todays complex chip designs actually

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function as intended. Functional errors at the system level are the leading cause of design revisions affecting time to market and profitability. Design teams must improve existing methodologies with tools that scale across design complexity and multiple levels of abstraction.

IC Design: Traditional EDA tools for physical design and verification have reached limits due to greater manufacturing process variability and the growing size and complexity of designs that take advantage of the latest nanometer scaling. With the advent of new process technologies, the handoff between integrated circuit (IC) layout and manufacturing has changed from a simple check to a multi-step process where the layout design must be enhanced to ensure efficient manufacturing. This presents a host of challenges related to manufacturing process effects, photolithography, data volumes, and achieving a cost-effective yield of finished chips from each wafer. To meet these challenges with confidence, design teams turn to Mentor Graphics Olympus- SoC place and route system with Multi-Corner-Multi-Mode timing analysis and DFM-aware layout optimization for rapid closure of physical designs. The Olympus-SoC system works with the industry-leading integrated Calibre design-to-silicon platform, which includes physical verification, full-chip, transistor-level parasitic extraction, model-based design for manufacturability (DFM) solutions, mask data preparation (MDP) and resolution enhancement technologies (RET), such as optical proximity correction and other computational lithography techniques

IC Manufacturing Intellectual Property

Mechanical Analysis: Mentor Graphics newly formed Mechanical Analysis Division (previously Flomerics) offer a class-leading family of computational fluid dynamics (CFD) simulation tools. An extensive range of products aimed at helping engineers solve complex everyday engineering problems quickly and within budget.

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PCB Design PCB Manufacturing, Assembly & Test Silicon Test and Yield Analysis System Modeling Vehicle System Design: A new car now contains 15 percent more electronics than the models of one year ago, in entertainment, navigation and safety systems. As the electrical wiring systems in the transportation industry become increasingly complex, so the need for software solutions to manage this complexity grows

In addition to working in the above mentioned areas of hardware and software, the company also provide technical solution to other companies in following fields: 3D-IC Design and Test Solutions : To create mixed process SOCs with higher density, lower power, and greater bandwidth. All without disrupting the existing design flows. Mentor has full support for 2.5D/3D physical verification, extraction, simulation and testing.

Automotive Solutions: To reduce cost and improve quality. Their innovative EE Automotive Design solutions help the automotive industry reduce cost and time to market while improving product quality.

Foundry Solutions : Mentor Graphics has comprehensive tool flows for every stage of IC development providing the competitive edge for rapid time to market and first silicon success at the customers choice of foundry provider

Aerospace and Military Solutions: Innovate to exacting specifications. It helps in learning how their products help their aerospace and military customers design innovative products at lower cost and in less time while maintaining absolute assurance of safety and reliability.

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Low Power Solutions : Reduce the power consumption. The technologies give the added boost one needs to address power at every stage in the design flow

DO-254 Solutions: Mentor Graphics helps to meet DO-254 objectives. They offer the
industrys most comprehensive platform of DO-254 development tools, training and consultation, along with the partnerships and integrations one needs for his flows.
____________________________________________________________________________________

2.2.5. MARKETING POLICY

Mentor Graphics Corporation is a provider of software and hardware design solutions that enable its customers to develop electronic products. The Company markets its products and services worldwide, primarily to large companies in the military/aerospace, communications, computer, consumer electronics, and semiconductor, networking, multimedia, and transportation industries. The electronic systems that its customers create with its products include printed circuit boards, integrated circuits (ICs), field programmable gate arrays (FPGAs), embedded software solutions and wire harness systems. Its products are used in the design and development of a diverse set of electronic products, including automotive electronics, video game consoles, and digital cameras, cellular telephones, and Bluetooth devices, medical devices, such as automated external defibrillators, smart phones, e-book readers, and netbooks. On August 18, 2009, Mentor Graphics Corporation completed the acquisition of Logic Vision, Inc. ____________________________________________________________________________

2.2.6. CONCLUSION

Mentor Graphics is one of the frontier companies in the field of Electronic Design Automation and is one of the earliest as well. This U.S based company is ranked third in the Electronics Design field all over the world and has received many awards for its efficient working.

[23]

CHAPTER- 3

TECHNOLOGY DESCRIPTION
____________________________________________________________________________

3.1. INTRODUCTION
VHDL stands for VHSIC Hardware Description Language. VHSIC, in turn, stands for Very High Speed Integrated Circuit, which was a joint program between the US Department of Defense and IEEE in the mid-1980s to research on high-performance IC technology. VHDL was standardized by the IEEE in 1987 (VHDL-87) and extended in 1993 (VHDL-93). ____________________________________________________________________________

3.2. FEATURES
The features of VHDL can be summarized as: Designs may be decomposed hierarchically. Each design element has both, a well-defined interface (for connecting it to other elements) and a precise behavioral specification (for simulating it). Behavioral specifications can use either an algorithm or an actual hardware structure to define an elements operation. Concurrency, timing, and clocking can all be modeled. VHDL handles asynchronous as well as synchronous sequential-circuit structures. The logical operation and timing behavior of a design can be simulated. VHDL synthesis tools are programs that can create logic-circuit structures directly from VHDL behavioral descriptions. Using VHDL, you can design, simulate, and synthesize anything from a simple combinational circuit to a complete microprocessor system on a chip.

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3.3. CAPABILITIES OF VHDL

The following are the major capabilities that VHDL provide along with the feature that differentiate it from other Hardware Description languages.

1. The language can be used as an exchange medium between chip vender and CAD tool users. Different chip venders can provide VHDL description of their components to system designers. CAD tool users can use it to capture the behavior of the design at a high level of abstraction for functional simulation.

2. The language can also be used as a communication medium between different CAD and CAM tools. For example a schematic capture program may be used to generate a VHDL description for the design, which can be used as an input to a simulation program.

3. The language supports hierarchy i.e. a digital system can be modeled as a set of interconnected sub-components.

4. The language is not technology specific, but is capable of supporting different technologies. It can support various hardware technologies: for example - new logic types and new components may be defined; technology specific attributes can be used. By being technology independent the same model can be synthesized into different vendor libraries.

5. It supports both synchronous and asynchronous timing models.

6. It is an IEEE and ANSI STANDARD; therefore, models described in this language are portable.

7. The language supports three basic different description styles: structural, data flow and behavioral. A design may be described in any combination of these three descriptive styles.

[25]

8. It supports a wide range of abstraction level ranging from behavioral description to very precise gate level descriptions. It does not however support modeling at or below the transistor level. It allows a design to be captured at a mixed level using a single coherent language.

9. Arbitrary large design can be modeled using the language, and there are no limitations imposed by the language on the size of a design.

10. The language has element that make large-scale modeling easier, for example component, functions, procedure, and packages.

11. Nominal propagation delays, min-max delay, setup and holding time and spike detection can all be very naturally done in this language.

12. A model can, not only describe the functionality of a design but also the information about the design itself in terms of user defined attributes such as total area and speed.

13. A common language can be used to describe library components from different vendors. Tools that understand VHDL models will have no difficulty in reading models from a variety of venders since the languages is a standard.

14. Models written in this language can be verified by simulation, since precise simulation semantics are defined for language construct.

15. The capability of defining new data types provides the power of describe and simulate a new design technique at a very high level of abstraction without any concern the implementation details.

16. The language is publicly available and human readable.

_____________________________________________________________________

[26]

3.4. DESIGN FLOW

The basic steps involved in the design flow are as follows: 1. Hierarchical / block diagram. Figuring out the basic approach and building blocks at the block-diagram level. Large logic designs are usually hierarchical, and VHDL gives you a good framework for defining modules and their interfaces and filling in the details later. 2. Coding. Actual writing of VHDL code for modules, their interfaces, and their internal details. 3. Compilation. Analyses your code for syntax errors and checks it for compatibility with other modules on which it relies. Compilation also creates the internal information that is needed for simulation. 4. Simulation. A VHDL simulator allows you to define and apply inputs to your design, and to observe its outputs. Simulation is part of a larger step called verification. A functional verification is performed to verify that the circuits logical operation works as desired independent of timing considerations and gate delays. 5. Synthesis. Converting the VHDL description into a set of primitives or components that can be assembled in the target technology. For example, with PLDs or CPLDs, the synthesis tool may generate two-level sum-of products equations. With ASICs, it may generate a netlist that specifies how the gates should be interconnected. 6. Fitting / Placement & Routing. Maps the synthesized components onto physical devices. 7. Timing verification. At this stage, the actual circuit delays due to wire lengths, electrical loading, and other factors are known, so precise timing simulation can be performed. Study the circuits operation including estimated delays, and we verify that the setup, hold, and other timing requirements for sequential devices like flip-flops are met.

____________________________________________________________________________

3.5. PROGRAM STRUCTURE

A key idea in VHDL is to define the interface of a hardware module while hiding its internal details. A VHDL entity is simply a declaration of a modules inputs and outputs, i.e. its external

[27]

interface signals or ports. A VHDL architecture is a detailed description of the modules internal structure or behavior. You can think of the entity as a wrapper for the architecture, hiding the details of whats inside while providing the hooks for other modules to use it. VHDL actually allows you to define multiple architectures for a single entity, and it provides a configuration management facility that allows you to specify which one to use during a particular synthesis run.

In the text file of a VHDL program, the entity declaration and architecture definition are separated. Example VHDL program for a not gate:
entity Not is port (X, Y: in BIT; Z: out BIT); end Inhibit; architecture Not_arch of Not is begin Z <= X not Y; end Not_arch;

Table 3.1. VHDL code example Some of the important parameters in a VHDL program are as follows: Keywords: entity, port, is, in, out, end, architecture, begin, when, else, and not. Comments: begin with two hyphens (--) and end at the end of a line. Identifiers: begin with a letter and contain letters, digits, and underscores. (An underscore may not follow another underscore or be the last character in an identifier.) Keywords and identifiers are not case sensitive. A basic entity declaration has the syntax as shown below: entity entity-name is port (signal-names : mode signal-type; signal-names : mode signal-type; signal-names : mode signal-type); end entity-names;

Table 3.2. Entity declaration

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In addition to the keywords, an entity declaration has the following elements: Entity-name: A user-selected identifier to name the entity. Signal-names: A comma-separated list of one or more user-selected identifiers to name externalinterface signals. Mode: One of four reserved words, specifying the signal direction: In The signal is an input to the entity. Out The signal is an output of the entity. Note that the value of such a signal cannot be read inside the entitys architecture, only by other entities that use it. Buffer The signal is an output of the entity, and its value can also be read inside the entitys architecture. Inout The signal can be used as an input or an output of the entity. This mode is typically used for three state input/output pins on PLDs. Signal-type: A built-in or user-defined signal type.

A basic architecture definition has the syntax as shown below: architecture architecture-name of entity-name is type declarations signal declarations constant declarations function definitions procedure definitions component declarations begin concurrent-statement concurrent-statement end architecture-name; Table 3.3. Architecture declaration The architecture-name is a user-selected identifier, usually related to the entity name. An architectures external interface signals (ports) are inherited from the port-declaration part of its corresponding entity declaration. An architecture may also include signals and other declarations

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that are local to that architecture. Declarations common to multiple entities can be made in a separate package used by all entities. ____________________________________________________________________________

3.6. TYPES AND CONSTANTS

All signals, variables, and constants must have an associated type. The type specifies the set or range of values that the object can take on. Some predefined types are: Bit, bit_vector, character, integer, real, and string. A user-defined enumerated types have the following syntax:
type type-name is (value-list); -- value-list is a comma-separated list of all possible values of the type. -- subtypes of a type. Values must be a contiguous range of values of the base type, from start to end. subtype subtype-name is type-name range start to end; -- ascending order subtype subtype-name is type-name range start downto end; -- descending order constant constant-name: type-name := value;

Table 3.4. Type declaration Array types have the following syntax: type type-name is array (start to end) of element-type; type type-name is array (start downto end) of element-type; type type-name is array (range-type) of element-type; type type-name is array (range-type range start to end) of element-type; type type-name is array (range-type range start downto end) of element-type; Table 3.5. Array declaration Array elements are considered to be ordered from left to right, in the same direction as index range. The most important array type is: type STD_LOGIC_VECTOR is array (natural range < >) of STD_LOGIC;

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___________________________________________________________________________

3.7. LIBRARIES AND PACKAGES

A library is a place where the VHDL compiler stores information about a particular design project, including intermediate files that are used in the analysis, simulation, and synthesis of the design. For a given VHDL design, the compiler automatically creates and uses a library named work under the current design directory. Use the library clause at the beginning of the design file to use a standard library. library ieee; The clause library work; is included implicitly at the beginning of every VHDL design file. A library name in a design gives it access to any previously analyzed entities and architectures stored in the library, but it does not give access to type definitions. A package is a file containing definitions of objects that can be used in other programs. The kind of objects that can be put into a package include signal, type, constant, function, procedure, and component declarations. Signals that are defined in a package are global signals, available to any entity that uses the package. A design can use a package with the statement use ieee.std_logic_1164.all; Here, ieee is the name of the library. Use the file named std_logic_1164 within this library. The all tells the compiler to use all of the definitions in this file. The package syntax:
package package-name is -- public section: visible in any design file that uses the package type declarations signal declarations component declarations function declarations procedure declarations end package-name; package body package-name is -- private section: local to the package type declarations constant declarations function definitions -- the complete function definition procedure definitions end package-name;

Table 3.6. Package declaration

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____________________________________________________________________________

3.8. STRUCTURAL DESIGN ELEMENTS

The body of an architecture is a series of concurrent statements. Each concurrent statement executes simultaneously with the other concurrent statements in the same architecture body. E.g. if the last statement updates a signal that is used by the first statement, then the simulator will go back to that first statement and update its results according to the signal that just changed. The simulator will keep propagating changes and updating results until the simulated circuit stabilizes.
Component statement (a concurrent statement). label: component-name port map (signal1, signal2, , signal_n); label: component-name port map(port1=>signal1, port2=>signal2, , port_n=>signal_n);

Table 3.7. Port mapping syntax Component-name is the name of a previously defined entity that is to be used, or instantiated, within the current architecture body. Each instance must be named by a unique label. The port map introduces a list that associates ports of the named entity with signals in the current architecture. Before being instantiated in an architectures definition, a component must be declared in a component declaration in an architectures definition. It is essentially the same as the port-declaration part of the corresponding entity declaration. The components used in an architecture may be ones that were previously defined as part of a design, or they may be part of a library. A component declaration shown below.
component component-name port (signal-names : mode signal-type; signal-names : mode signal-type; signal-names : mode signal-type); end component;

Table 3.8. Component declaration A VHDL architecture that uses components is often called a structural description or structural design, because it defines the precise interconnection structure of signals and entities that realize the entity. A pure structural description is equivalent to a schematic or a net list for the circuit.

_________________________________________________________________
[32]

3.9. DATAFLOW DESIGN ELEMENTS

Several additional concurrent statements allow VHDL to describe a circuit in terms of the flow of data and operations on it within the circuit. This style is called a dataflow description or dataflow design. concurrent signal-assignment statement. signal-name <= expression; The type for expression must be identical or a sub-type of signal-name. conditional signal-assignment statement.
signal-name <= expression when boolean-expression else expression when boolean-expression else expression when boolean-expression else expression;

Table 3.9. When-Else syntax Boolean operators: and, or, not. Relational operators: =, /= (not equal), >, >=, <, <=. ____________________________________________________________________________

3.10. BEHAVIORAL DESIGN ELEMENTS

VHDLs key behavioral element is the process. A process is a collection of sequential statements that executes in parallel with other concurrent statements and other processes.
process statement. process (signal-name, signal-name, , signalname) type declarations variable declarations function definitions procedure definitions begin sequential-statement end process;

Table 3.10. Behavioral Modelling

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A process statement can be used anywhere that a concurrent statement can be used. A process is either running or suspended. The list of signals in the process definition, called the sensitivity list, determines when the process runs. A process initially is suspended. When any signal in its sensitivity list changes value, the process resumes execution, starting with its first sequential statement and continuing until the end. If any signal in the sensitivity list change value as a result of running the process, it runs again. This continues until none of the signals change value. In simulation, all of this happens in zero simulated time. The sensitivity list is optional; a process without a sensitivity list starts running at time zero in simulation. One application of such a process is to generate input waveforms in a test bench. A process may not declare signals. It can only declare variables. A VHDL variable is similar to signals, except that they usually dont have physical significance in a circuit. They are used only in functions, procedures, and processes to keep track of the state within a process and is not visible outside of the process.

____________________________________________________________________________

3.11. CONCLUSION
The VHDL language is used as hardware description language to design Application Specific Integrated Circuits. It is used in the programming of Field Programmable Gate Arrays and Complex Programming Logic Devices. It has its own benefits of being easier in comparison to other hardware description languages and more user friendly.

[34]

CHAPTER- 4

PROJECT DEVELOPMENT _________________________________________________________

4.1. INTRODUCTION
The VHDL language is used as Hardware Description Language. Hence, a particular code is designed for describing the behavior of any circuit which after being simulated by its test bench, has to be loaded on the FPGA or CPLD. Various interfaces are connected to these programmable devices through which the behavior of the code may be analyzed. Some of the common interfaces commented to FPGAs or CPLDs are LEDs, Dip Switches, 16 * 2 character LCD etc. ____________________________________________________________________________

4.2. FPGA
Very Large Scale Integration (VLSI) Technology has opened the door to powerful digital circuits at low cost. It has become possible to build chips with more than a million transistors. Such chips are realized using the full-custom approach, where all parts of VLSI circuit are carefully tailored to meet a set of specific requirements. Semi-custom approaches such as standard cells and MaskProgrammed Gate Arrays (MPGAs) have provided an easier way of designing and manufacturing Application-Specific Integrated Circuits (ASICs).

Each of these techniques, however, requires extensive manufacturing effort, taking several months from beginning to end. This results in a high cost until large volumes are produced. In electronics industry it is vital to reach the market in shortest possible time and also it is important that the financial risk incurred in the development of the new product be limited.

Field-Programmable Gate arrays (FPGAs) have emerged as the ultimate solution to these problems because they provide instant manufacturing and low cost prototypes.

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____________________________________________________________________________

4.3. CPLD
A Complex Programmable Logic Device (CPLD) is a combination of a fully programmable AND/OR array and a bank of macrocells. The AND/OR array is reprogrammable and can perform a multitude of logic functions. Macrocells are functional blocks that perform combinatorial or sequential logic, and also have the added flexibility for true or complement, along with varied feedback paths.

_____________________________________________
4.4. SYSTEM ANALYSIS _________________________________________________________________
4.4.1. CHARACTER LCD INTERFACE
The character LCD is power by +5V. The FPGA I/O signals are powered by 3.3V. However, the FPGAs output levels are recognized as valid Low or High logic levels by the LCD. The LCD controller accepts 5V TTL signal levels and the 3.3V LVCMOS outputs provided by the FPGA meet the 5V TTL voltage level requirements. The 390 series resistors on the data lines prevent overstressing on the FPGA and Strata Flash I/O pins when the character LCD drives a High logic value. The character LCD drives the data lines when LCD_RW is High. Most applications treat the LCD as a write only peripheral and never read from the display. The 8-bit parallel interface logic will be developed inside the FPGA to configure the HD44780 based dot matrix LCD controller for the character LCD support. The 16x2 character LCD from oriole electronics will be used to interface with FPGA through 8 bit parallel mode using FPGA I/Os.

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Fig 4.1. 2*16 Character LCD

Fig 4.2. Interfacing of Character LCD with FPGA

Fig 4.3. Circuit Diagram of Character LCD Interfacing with FPGA

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___________________________________________________________________________

4.4.2. 7 SEGMENT LED INTERFACE

A seven-segment display (SSD), or seven-segment indicator, is a form of electronic display device for displaying decimal numerals that is an alternative to the more complex dot-matrix displays. The Spartan3 FPGA Kit has a two-character, seven-segment LED display controlled by FPGA user-I/O pins, as shown in Figure. Each digit shares eight common control signals to light individual LED segments. Each individual character has a separate anode control input. To light an individual signal, drive the individual segment control signal Low along with the associated anode control signal for the individual character.

Fig 4.4. 7 Segment Display Interfacing with FPGA

______________________________________________________________________ 4.4.3. DIP SWITCHES

These switches are used to give high level or low level logic as input to the FPGA for the required output according to the VHDL code.

Fig 4.5. DIP Switch

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____________________________________________________________________________

4.5. PROJECT DESCRIPTION _________________________________________________________________

4.5.1. SERIAL IN SERIAL OUT SHIFT REGISTER
In general a shift register is characterized by the following control and data signals, which are fully recognized by XST: Clock Serial input Asynchronous set/reset Synchronous set/reset Synchronous/asynchronous parallel load Clock enable Serial or parallel output.

The shift register output mode may be: Serial: only the contents of the last flip-flop is accessed by the rest of the circuit Parallel: the contents of one or several of flip-flops other than the last one, is accessed Shift modes: left, right, etc.

_________________________________________________________________________

4.5.2. ALU
ALU (Arithmetic Logic Unit) is a digital circuit which does arithmetic and logical operations. Its a basic block in any processor. The block diagram of the ALU is given below. As clear form the diagram, it receives two input operands 'A' and 'B' which are 8 bits long. The result is denoted by 'R' which is also 8 bit long. The input signal 'Op' is a 3 bit value which tells the ALU what operation to be performed by the ALU. Since 'Op' is 3 bits long we can have 2^3=8 operations. The ALU being designed is capable of performing following operations: Addition Subtraction AND

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OR NAND NOR XOR NOT

Fig 4.6. Functional block of ALU

_________________________________________________________________
4.5.3. DISPLAY ON CHARACTER LCD
The LCD interfaced with the FPGA in the general kit is a 16*2 character LCD. The LCD is initialized by a Clock triggering event and its initialization commands such as Clear Display, Function Set, Cursor Home, Setting RAM address. The ASCII code has to be passed to the LCD for every particular character display and command execution. The 3 signals that control the working of the character LCD are Register Select, Read/Write and Enable. The value of Enable if kept at low logic, stops the internal processing of the LCD, Register Select operation is needed to select the register to write or read data while R/W command is used to select among the Read and Write operations.

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_________________________________________________________________ 4.6. PROJECT DEVELOPMENT

Fig 4.7. Xilinx Webpack The project development were done on the Xilinx Webpack ISE. The software provides the work environment for the development of the code in Hardware Description Languages such as VHDL. It supports two hardware description languages, VHDL and Verilog. It also supports the integration of various simulation tools into itself. Apart for the workspace provided for the code development, 3 other dock windows are there on the software. The first one show the files in a particular project and highlights the file on which a user is currently working. The next one show the various options of the implementation of the program such as the simulation options, options for the testing, mapping, pin configuration etc. The bottom window shows the warnings and errors of the developed code when the syntax of the code is checked by the user. It also shows the number of line at which the error exists which makes it easier for the user to debug the program.

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____________________________________________________________________________

4.7. PROJECT TESTING

Fig 4.8. Modelsim Simulator ModelSim is a powerful simulator that can be used to simulate the behavior and performance of logic circuits. The simulator allows the user to apply inputs to the designed circuit, usually referred to as test vectors, and to observe the outputs generated in response. The user can use the Waveform Editor to represent the input signals as waveforms. ModelSim performs simulation in the context of projects one project at a time. A project includes the design files that specify the circuit to be simulated.

However, even if a project responds well to its simulation, it is not necessary that it will behave in the same manner on the hardware, as the simulation only gives the response according

[42]

to the code written. It does not involve the restrictions that are faced during implementing the code on the hardware.

____________________________________________________________________________________

4.8. CONCLUSION
Through the project implementation on both hardware and software gives the complete knowledge about the RTL (Register Transfer Logic) implementation. A project after being developed have to be tested on its test bench. The test bench shows the result of the code in respect to the various inputs given to the code. Afterwards the code is to e planned and mapped before writing it to the Programming Devices which is done by various methods including JTAG communication or ETHERNET cable for the proper realization of the program.

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CHAPTER-5

CONCLUSION
____________________________________________________________________________

5.1. FUTURE PROSPECTS OF VHDL

VHDL, One of the biggest job providing sector today, have a very bright future in the coming time, but as the time is passing some other languages are making control over designing, as for example Verilog HDL. Verilog HDL is a little bit better in processing speed than VHDL. But on the other hand VHDL is also better in some fields like, all the three styles of modeling (Data flow, Behavioral, Structural) in VHDL can be mixed together in the same program i.e. VHDL is more user friendly than Verilog HDL.

But today all over world mainly VHDL is used for chip designing at low level. Till now there are number of drawbacks in VHDL. As main drawback of VHDL is that, there are a number of features in VHDL that can be simulated but not synthesized. As, final shape to VHDL was given by IEEE, hence IEEE is working on it continuously and trying to make available simulation features to synthesis also.

So if we talk about future prospectus of VHDL, it depends on success of IEEE. If IEEE got able to implement such features that there remain no differences between simulation & synthesis with higher processing speed and designing up to more lower level of abstraction, on that day VHDL may take hold over all other HDLs. ____________________________________________________________________________

5.2. CONCLUSION
Learning about VLSI designing has helped me to understand the working of many Application Specific Integrated Circuits that are used even in daily appliances like Refrigerator, Washing Machines etc.

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RTL designing has much scope in the hardware sector in upcoming time in India as the semiconductor market is worth $250 billion. Hence, the knowledge of VHDL also increases the employability.

Through my summer training, I came out of the conventional subjects and gained a small
experience of the current hardware industries requirements and expectations.

Apart from VHDL, there are also come other languages available for the Hardware Description such as Verilog and System C which have their own benefits and drawbacks. Yet, there knowledge certainly helps in becoming a good RTL designer.

The main purpose of designing a code is to make it synthesizable rather than focusing it
to be a code that can be successfully simulated. Hence, during programming a programmable device, certain hardware restrictions should always be put in mind.

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ANNEXURE _________________________________________________________
VHDL CODE FOR SHIFT REGISTER
8-bit shift-left register with a positive-edge clock, serial in, and serial out.
library ieee; use ieee.std_logic_1164.all; entity shift is port(C, SI : in std_logic; SO : out std_logic); end shift; architecture archi of shift is signal tmp: std_logic_vector(7 downto 0) begin process (C) begin if (C'event and C='1') then for i in 0 to 6 loop tmp(i+1) <= tmp(i); end loop; tmp(0) <= SI; end if; end process; SO <= tmp(7); end archi;

_______________________________________________________________ 8-bit shift-left/shift-right register with a positive-edge clock, serial in, and serial out.

library ieee; use ieee.std_logic_1164.all; entity shift is port(C, SI, left_right : in std_logic; PO : out std_logic_vector(7 downto 0)); end shift; architecture archi of shift is signal tmp: std_logic_vector(7 downto 0);

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begin process (C) begin if (C'event and C='1') then if (left_right='0') then tmp <= tmp(6 downto 0) & SI; else tmp <= SI & tmp(7 downto 1); end if; end if; end process; PO <= tmp; end archi;

___________________________________________________________

VHDL CODE FOR ALU

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity simple_alu is port( Clk : in std_logic; --clock signal A,B : in signed(7 downto 0); --input operands Op : in unsigned(2 downto 0); --Operation to be performed R : out signed(7 downto 0) --output of ALU ); end simple_alu; architecture Behavioral of simple_alu is --temporary signal declaration. signal Reg1,Reg2,Reg3 : signed(7 downto 0) := (others => '0'); begin Reg1 <= A; Reg2 <= B; R <= Reg3; process(Clk) begin

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if(rising_edge(Clk)) then --Do the calculation at the positive edge of clock cycle. case Op is when "000" => Reg3 <= Reg1 + Reg2; --addition when "001" => Reg3 <= Reg1 - Reg2; --subtraction when "010" => Reg3 <= not Reg1; --NOT gate when "011" => Reg3 <= Reg1 nand Reg2; --NAND gate when "100" => Reg3 <= Reg1 nor Reg2; --NOR gate when "101" => Reg3 <= Reg1 and Reg2; --AND gate when "110" => Reg3 <= Reg1 or Reg2; --OR gate when "111" => Reg3 <= Reg1 xor Reg2; --XOR gate when others => NULL; end case; end if; end process; end Behavioral; __________________________________________________________________

VHDL CODE FOR LCD DISLAY

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; --Define The Core Entity ENTITY LCD IS PORT( --Counter/VGA Timing CLK : IN STD_LOGIC --LCD Control Signal LCD_ENABLE : OUT STD_LOGIC; LCD_RW : OUT STD_LOGIC; LCD_RS : OUT STD_LOGIC; [48]

--LCD Data Signals LCD_DATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));

end LCD; --Define The Architecture Of The Entity ARCHITECTURE behavior of LCD IS

type state_type is (

S0, S1, S2, S3, S4, S5, S6, S7, S8, S9,

S10, S11, S12, S13, S14, S15, S16, S17, S18, S19,S20, S21, S22, S23, S24, S25,IDLE); signal current_state: state_type; BEGIN PROCESS VARIABLE cnt: INTEGER RANGE 0 TO 1750000; BEGIN WAIT UNTIL(clk'EVENT) AND (clk = '1'); --Count Clock Ticks IF(cnt = 1750000)THEN cnt := 0; ELSE cnt := cnt + 1; END IF; IF(cnt = 1500000)THEN --Next State LogiC case current_state is -------------------Function Set------------------when S0 => current_state LCD_DATA LCD_ENABLE <= LCD_RW LCD_RS when S1 => current_state LCD_DATA LCD_ENABLE <= LCD_RW LCD_RS

<= S1; <= "00110000"; '0'; <= '0'; <= '0'; <= S2; <= "00110000"; '1'; <= '0'; <= '0';

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when S2 =>current_state <= S3; LCD_DATA <= "00110000"; LCD_ENABLE <= '0'; LCD_RW <= '0'; LCD_RS <= '0' ------------------Reset Display ---------when S3 =>current_state <= S4; LCD_DATA <= "00000001"; LCD_ENABLE <= '0'; LCD_RW <= '0'; LCD_RS <= '0'; when S4 => current_state <= S5; LCD_DATA <= "00000001"; LCD_ENABLE <= '1'; LCD_RW <= '0'; LCD_RS <= '0'; when S5 => current_state <= S6; LCD_DATA <= "00000001"; LCD_ENABLE <= '0'; LCD_RW <= '0'; LCD_RS <= '0'; -------------------Display On------------------when S6 =>current_state <= S7; LCD_DATA <= "00001110"; LCD_ENABLE <= '0'; LCD_RW <= '0'; LCD_RS <= '0'; when S7 =>current_state <= S8; LCD_DATA <= "00001110"; LCD_ENABLE <= '1'; LCD_RW <= '0'; LCD_RS <= '0'; when S8 => current_state <= S9; LCD_DATA <= "00001110"; LCD_ENABLE <= '0'; LCD_RW <= '0'; LCD_RS <= '1';

-------------------Write 'H'------------------when S9 => current_state <= S10; LCD_DATA <= x"48; [50]

LCD_ENABLE <= '1'; LCD_RW <= '0'; LCD_RS <= '1'; when S10 => LCD_ENABLE <= '0'; ------------------WRITE 'E'------------------when S11 => current_state <= S12; LCD_DATA <= X"45; LCD_ENABLE <= '1'; LCD_RW <= '0'; LCD_RS <= '1'; when S12 =>current_state <= S13; LCD_ENABLE <= '0'; -------------------WRITE 'L'------------------when S13 => current_state <= S14; LCD_DATA <= X"4C"; LCD_ENABLE <= '1'; LCD_RW <= '0'; LCD_RS <= '1'; when S14 => current_state <= S15; LCD_ENABLE <= '0'; -----------------WRITE 'L'------------------when S15 => current_state <= S16; LCD_DATA <= X"4F"; LCD_ENABLE <= '1'; LCD_RW <= '0'; LCD_RS <= '1'; when S16 => current_state <= S17; LCD_ENABLE <= '0'; -------------------WRITE 'O'------------------when S17 => current_state LCD_DATA LCD_ENABLE <= LCD_RW LCD_RS when S18 => current_state LCD_ENABLE <= <= S18; <= X"4F"; '1'; <= '0'; <= '1'; <= S19; '0';

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when S24 => current_state <= S25; LCD_ENABLE <= '0'; when S25 => current_state <= IDLE; when IDLE => current_state <= IDLE; when others => current_state <= IDLE; end case; END IF; END PROCESS; END behavior;

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REFERENCES

[1]

M. Mano and C. Kime, Logic and Computer Design Fundamentals, 2nd

Edition, Prentice Hall, Upper Saddle River, 2001. [2] S. Yalamanchili, VHDL Starters Guide, Prentice Hall, Upper Saddle

River, 1998. [3] J. Bhasker, VHDL Primer, 3rd Edition, Prentice Hall, Upper Saddle

River, 1998. [4] [5] Douglas L. Perry, VHDL Programming by Examples, 4th Edition, TMH. C. H. Roth, Digital System Design using VHDL, PWS Publishing

Company, New York, 1998

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