863

2013-1426
(Reexamination Nos. 95/000,250 & 95/001,124)

IN THE
UNITED STATES COURT OF APPEALS
FOR THE FEDERAL CIRCUIT

RAMBUS, INC.,
Appellant,

v.

MICRON TECHNOLOGY, INC.,
Appellee.

Appeal from the United States Patent and Trademark Office,
Patent Trial and Appeal Board.

BRIEF FOR APPELLANT RAMBUS INC.

October 11, 2013
J . Michael J akes
J ason E. Stach
Aidan C. Skoyles
FINNEGAN, HENDERSON, FARABOW,
GARRETT & DUNNER, LLP
901 New York Avenue, NW
Washington, DC 20001
(202) 408-4000

Attorneys for Appellant Rambus Inc.

Case: 13-1426 Document: 23 Page: 1 Filed: 10/11/2013
i

CERTIFICATE OF INTEREST
Pursuant to Federal Circuit Rules 27(a)(7) and 47.4(a), counsel for Appellant
Rambus Inc. certify the following:
1. The full name of every party or amicus represented by us is:

Rambus Inc.

2. The name of the real party in interest (if the party named in the caption is not
the real party in interest) represented by us is:

Rambus Inc.

3. All parent corporations and any publicly held companies that own 10 percent or
more of the stock of any party represented by us are:

None

4. The names of all law firms and the partners or associates that appeared for the
parties now represented by us in the trial court or are expected to appear in this
Court are:

J ames R. Barney, Kathleen Daley, J . Michael J akes, Naveen Modi,
Molly R. Silfen, J ason E. Stach, and Aidan C. Skoyles
FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER, LLP

ii

TABLE OF CONTENTS
Statement of Related Cases ..................................................................................... vii
Statement of J urisdiction ............................................................................................ 1
I. Statement of the Issues .................................................................................... 2
II. Statement of the Case ...................................................................................... 3
III. Statement of Facts ............................................................................................ 6
A. The 863 Patents Relation to the Farmwald Family of
Patents.................................................................................................... 6
B. Claims 21-23, the Claims on Appeal .................................................... 7
C. Technology of the 863 Patent .............................................................. 8
1. Memory Controllers and Memory Devices ................................ 8
2. Synchronous Transaction Timing ............................................... 9
3. The 863 Patents Clocking Scheme .........................................10
4. The Delay-Locked Loop of the 863 Patent .............................11
5. The Innovations Disclosed and Claimed in the 863
Patent Enabled Unprecedented Speed and Efficiency ..............15
D. The Proceedings Below .......................................................................15
1. Procedural Background Relevant to Microns Lack of
Standing ....................................................................................15
2. The PTOs Reliance on Lofgrens Teachings ..........................18
a. Lofgren Discloses a Phase-Locked Loop That
Times External Control Signals ......................................18
b. The Examiner and Board Found the Delay
Locked Loop for Generating One or Two Internal
Clock Signals Satisfied by Lofgrens Phase-
Locked Loop for Timing External Control Signals ........20
iii

3. The PTO Combined Inagaki and Lofgren with iAPX ..............22
a. Inagaki Discloses an Asynchronous System That
Uses Pulsed Signals During Data Transfers ...................22
b. iAPX Discloses a 10 MHz System That Fully
Utilizes the Edges of Its Two External Clock
Signals, CLKA and CLKB .............................................23
c. The Board Combined iAPX and Inagaki Primarily
to Take Advantage of Dual-Edged Clocking
Even Though Claims 22 and 23 Recite Two
Internal Clocks, Not Using Both Edges of a Single
Clock ...............................................................................24
d. The Board Combined iAPX and Lofgren, Even
Though iAPX Has No Identifiable Need for
Lofgrens Circuitry .........................................................27
e. The Board Dismissed the Objective Evidence of
NonobviousnessWhich Was Directly Tied to the
Claimed Featuresfor Lacking a Nexus to the
Claims .............................................................................28
E. The Courts Recent Decision in Rambus Inc. v. Rea
Vacated the Boards Obviousness Findings in a
Reexamination of Another Farmwald Patent ......................................32
IV. Summary of Argument ..................................................................................35
V. Argument .......................................................................................................36
A. Standards of Review ............................................................................36
B. The Board Erred in Implicitly Construing Delay Locked
Loop for Generating One or More Internal Clock Signals
to Include Lofgrens Phase-Locked Loop for Delaying
Non-clock Control Signals ..................................................................36
C. The Board Erred in Finding It Obvious to Combine iAPX
with Inagaki and/or Lofgren ................................................................40
1. The Board Erroneously Placed the Burden on
iv

Rambus to Disprove Obviousness ............................................40
2. One of Ordinary Skill Would Not Have Combined
Inagaki with iAPX ....................................................................41
Lofgren with iAPX....................................................................44
4. Objective Evidence Demonstrates Nonobviousness ................46
D. Micron Lacks Standing to Argue Issues Not Raised in Its
Own Reexamination Request ..............................................................50
VI. Conclusion .....................................................................................................54

v

TABLE OF AUTHORITIES
Page(s)
FEDERAL CASES
Alcon Research, Ltd. v. Apotex Inc.,
687 F.3d 1362 (Fed. Cir. 2012) .......................................................................... 49
In re Baker Hughes Inc.,
215 F.3d 1297 (Fed. Cir. 2000) .......................................................................... 36
In re DBC,
545 F.3d 1373 (Fed. Cir. 2008) .......................................................................... 49
Gechter v. Davidson,
116 F.3d 1454 (Fed. Cir. 1997) .......................................................................... 39
In re Glatt Air Techniques, Inc.,
630 F.3d 1026 (Fed. Cir. 2011) .......................................................................... 49
In re Hyatt,
211 F.3d 1367 (Fed. Cir. 2000) .......................................................................... 39
In re ICON Health & Fitness, Inc.,
496 F.3d 1374 (Fed. Cir. 2007) .......................................................................... 36
In re Kao,
639 F.3d 1057 (Fed. Cir. 2011) .......................................................................... 33
Koninklijke Philips Electronics N.V. v. Cardiac Science Operating Co.,
590 F.3d 1326 (Fed. Cir. 2010) .......................................................................... 51
KSR International Co. v. Teleflex Inc.,
550 U.S. 398 (2007) ............................................................................................ 42
Merck & Co. v. Kessler,
80 F.3d 1543 (Fed. Cir. 1996) ............................................................................ 51
Mintz v. Dietz & Watson, Inc.,
679 F.3d 1372 (Fed. Cir. 2012) .......................................................................... 46
In re NTP, Inc.,
654 F.3d 1279 (Fed. Cir. 2011) .......................................................................... 36
vi

Rambus Inc. v. Rea,
No. 2012-1634 (Fed. Cir. Sept. 24, 2013) ........................... 32, 33, 34, 41, 48, 50
FEDERAL STATUTES
35 U.S.C. 2 ...................................................................................................... 50, 51
35 U.S.C. 141 .......................................................................................................... 1
35 U.S.C. 315 ......................................................................................16, 51, 52, 53
35 U.S.C. 317 .................................................................................................. 52, 53
REGULATIONS
37 C.F.R. 1.989 ............................................................................................... 15, 50
vii

STATEMENT OF RELATED CASES
Rambus is unaware of any other appeals or petitions taken in this
reexamination proceeding. There are, however, a number of matters pending in
this Court and other courts that involve the patent at issue in this appeal, U.S.
Patent No. 6,452,863 (the 863 patent), or other patents in the same family as the
863 patent.
1. The following pending case involves the 863 patent:
Micron Technology, Inc. v. Rambus Inc., No. 13-1294 (Fed. Cir.) (appellant
brief filed). This is the second appeal from Civil Action No. 1:00-cv-00792-SLR
(D. Del.) (Robinson, J .). This Court previously remanded the case in Appeal No.
2009-1263, 645 F.3d 1311 (Fed. Cir. 2011) (Circuit J udges Bryson, Linn, Lourie,
and Newman joined the majority opinion; Circuit J udge Gajarsa concurred in part
and dissented in part).
2. The following pending case does not involve the 863 patent but
involves patents that, like the 863 patent, descend from Application No.
07/510,898 (the 898 application):
Rambus Inc. v. Micron Technology, Inc. et al., No. 5:06-cv-00244-RMW
(N.D. Cal.) (Whyte, J .).
viii

3. Several ex parte and inter partes reexaminations involving patents
descended from the 898 application are pending at the U.S. Patent and Trademark
Office (PTO). Of those, the following have been appealed to this Court.
a. In re Rambus Inc., No. 2011-1247, 694 F.3d 42
(Fed. Cir. 2012) (Chief Circuit J udge Rader and Circuit J udges Dyk and Linn).
b. Rambus Inc. v. Rea, No. 2012-1634, __ F.3d __ (Fed. Cir.
Sept. 24, 2013) (Circuit J udges Linn, Moore, and OMalley).
c. Rambus, Inc. v. Micron Technology, Inc., No. 2013-1087
(Fed. Cir.) (briefing complete; consolidated with Appeal No. 2013-1339).
d. Rambus, Inc. v. Micron Technology, Inc., No. 2013-1192
(Fed. Cir.) (briefing complete).
e. Rambus, Inc. v. Micron Technology, Inc., No. 2013-1224
(Fed. Cir.) (appellant and appellee briefs filed; briefing not yet complete).
f. Rambus, Inc. v. Micron Technology, Inc., No. 2013-1228
(Fed. Cir.) (appellant and appellee briefs filed; briefing not yet complete).
g. Rambus, Inc. v. Micron Technology, Inc., No. 2013-1339
(Fed. Cir.) (briefing complete; consolidated with Appeal No. 2013-1087).
h. Rambus, Inc. v. NVIDIA, Corp., No. 2013-1597 (Fed. Cir.)
(briefing not yet complete).

1

STATEMENT OF JURISDICTION
This appeal arises from two inter partes reexamination proceedings before
the U.S. Patent and Trademark Office (PTO). Rambus Inc. (Rambus), the
patent owner, appealed the examiners rejection of the claims at issue to the Patent
Trial and Appeal Board (Board). The Board affirmed the examiners rejection of
claims 1-28 on October 23, 2012. Rambus requested rehearing, which the Board
denied on February 11, 2013. The Boards decision was final and appealable.
Rambus appealed. This Court has jurisdiction under 35 U.S.C. 141.

2

I. STATEMENT OF THE ISSUES
1. Where the claims call for operating a synchronous memory device to
generate one or two internal clock signals using an external clock signal and a
delay-locked loop, and to input data from a controller synchronously with respect
to the internal clock signal(s), did the Board err in construing these features so
broadly as to cover a phase-locked loop used to create a controlled delay of an
output signal from a frequency reference that is internal as opposed to external, and
where the output signal is not a clock and is not used for data input?
2. In affirming the obviousness of claims 21-23 based on a combination of
references, did the Board err by: (a) combining two references in a way that would
at best generate external clock signals, even though the claims require generating
internal clock signals; (b) finding that a third reference would have been combined
with the first, when combining those references is not suggested by any reference
and would only add unneeded precision to the first references system; and
(c) improperly discounting the objective evidence of nonobviousness?
3. Did Micron Technology, Inc. (Micron) have standing before the Board
and does it now have standing to participate in this appeal of issues that it never
raised in its reexamination request, where (a) Micron did not have a statutory right
to participate prior to the PTOs sua sponte merger of Microns and Samsung
Electronics, Inc.s (Samsung) reexamination proceedings; and (b) the PTOs
3

merger procedure is purely administrative and cannot, by itself, create substantive
appeal rights?
II. STATEMENT OF THE CASE
Rambus appeals the Boards rejections of claims 21-23 of U.S. Patent No.
6,452,863 (the 863 patent)
1
based on the following combinations of references.
2

Claim iAPX Inagaki Lofgren
21 X X
22 X X
23 X X X

In making these rejections, the Board erred in at least three ways.
First, the Board erred in construing the claimed delay locked loop for
generating either an internal clock signal or first and second internal clock
signals to encompass Lofgrens phase-locked loop (PLL) for setting a delay
element to produce control output signals having a controlled delay. Lofgren is
distinct from these claim elements in at least three ways: (1) Lofgren seeks to add
a precise amount of delay to an output signal, but the delayed signal is not
synchronous with or related to the PLL frequency source; (2) Lofgrens circuitry
pertains to delaying asynchronous, non-clock control output signals as opposed to

1
Rambus does not appeal the rejections of claims 1-20 and 24-28.
2
iAPX Interconnect Architecture Reference Manual (iAPX); J apanese
Patent Publication No. 57-210495 to Inagaki (Inagaki); UK Published Patent
Application No. 2,197,553 to Lofgren et al. (Lofgren).
4

generating clock signals for synchronously inputting data; and (3) Lofgrens
circuitry relies on a precision internal crystal oscillator used only to generate a
reference frequency as opposed to an external clock signal that is related to and
synchronous with data to be received from an external source.
The examiner supported these distinctions by stating in another
reexamination that Lofgren is direct[ed] to issuing precise delays with respect to a
control signal and does not teach generating an internal clock signal from an
external clock signal. (See A2348.) Rambuss expert similarly stated that Lofgren
is directed to external control of memory devices, not to the generation of an
internal clock signal in a memory device. (A1026[90].) The Boards decision
broadly construing the claimed delay locked loop features to encompass
Lofgrens circuitry was therefore incorrect and warrants reversal of the rejections
of claims 21 and 23.
Second, the Board erred in combining the teachings of Inagaki and Lofgren
with iAPX. The Boards obviousness analysis was flawed from the beginning, as
the Board placed the burden on Rambus to disprove obviousness. This Court
found this same approach to constitute legal error in Rambus Inc. v. Reaan
appeal from a reexamination of another patent in the same patent family as the
863 patent. Rambus Inc. v. Rea, No. 2012-1634, slip op. at 10-11 (Fed. Cir.
Sept. 24, 2013).
5

For the iAPX/Inagaki combination, claims 22 and 23 recite using two
separate clock signals, but the Board treated those claims as though they recite
using two edges of a single clock signal. This misinterpretation permeated the
Boards reasoning for why Inagaki would have been combined with iAPX. The
only justification the Board offered that pertained to generating first and second
internal clock signals, as claimed, was to use one of Inagakis signals to generate
two clocks in iAPX, CLKA and CLKB. But the examiner, requester Samsung, and
Rambus all agree that CLKA and CLKB are external received clock signals, not
the internal generated clock signals claimed. Thus, the undisputed facts
demonstrate that the Boards combination does not result in the claimed invention.
And for the iAPX/Lofgren combination, unrefuted evidence demonstrates
that the iAPX data receivers required such low timing precision that they would
not have benefited from Lofgrens precision delay circuitry, so one of ordinary
skill in the art would have had no reason to combine the references. Furthermore,
the art fails to suggest that data rate can be increased by generating internal clock
signals from the external clock signal for data received at a memory device
synchronously with a received clock signal.
The Board also erred in dismissing Rambuss objective evidence of
nonobviousness. In doing so, the Board committed many of the same errors that
led this Court to vacate a similar Board decision in Rambus Inc. v. Rea. For
6

example, the Board incorrectly found that the objective evidence lacked a nexus
with the claimed invention despite the fact that claimed features are expressly
discussed in the objective evidence. The objective evidence also discusses features
that are enabled by the claimed features, such as the high system speeds attainable
when using the claimed delay-locked loop features on a synchronous memory
device. These errors in the Boards obviousness analysis require reversing the
rejections of claims 21-23.
Finally, the Board erred in allowing Micron to participate in the appeal of
issues raised only in Samsungs reexamination request. Because Micron had no
standing to participate in a Samsung appeal before the PTOs merger of Microns
reexamination with Samsungs, it could not have gained the right to do so merely
by virtue of the PTOs merger. Micron was therefore not a proper party to the
appeal before the Board, and is also not a proper party before this Court.
III. STATEMENT OF FACTS
A. The 863 Patents Relation to the Farmwald Family of
Patents
The 863 patent claims priority to Application No. 07/510,898 (the 898
application), filed on April 18, 1990. (A60.) The 898 application led to a large
family of Farmwald patents, including the 863 patent and U.S. Patent No.
6,034,918 (the 918 patent). (A60; A1702; A1752; A1785.) The Farmwald
patents all share a substantially identical specification. (See A60-89; A1702-813.)
7

B. Claims 21-23, the Claims on Appeal
Claims 21-23 of the 863 patent (the claims at issue in this appeal), and
claim 14 from which they depend, recite the following:
14. A method of operation in a synchronous memory
device, wherein the memory device includes a plurality
of memory cells, the method of operation of the memory
device comprises:
receiving first block size information from a memory
controller, wherein the memory device is capable of
processing the first block size information, wherein the
first block size information represents a first amount of
data to be input by the memory device in response to an
operation code;
receiving the operation code, from the memory
controller, synchronously with respect to an external
clock signal; and
inputting the first amount of data in response to the
operation code.
21. The method of claim 14 further including generating
an internal clock signal, using a delay locked loop and
the external clock signal wherein the first amount of data
is input synchronously with respect to the internal clock
signal.
first and second internal clock signals using clock
generation circuitry and the external clock signal,
wherein the first amount of data is input synchronously
with respect to the first and second internal clock signals.
23. The method of claim 22 wherein the first and second
internal clock signals are generated by a delay lock loop.
(A90[25:43-58, 26:11-22].)
8

C. Technology of the 863 Patent
1. Memory Controllers and Memory Devices
The 863 patent discloses two types of memory components: (1) a memory
controller that coordinates memory operations and contains most of the
intelligence of the memory system; and (2) a memory device that can store and
retrieve information electronically. (See, e.g., A60[Abstract]; A79[3:52-4:21].) A
memory system often has multiple memory devices under the control of one
memory controller. (See, e.g., A65[Fig. 2] (showing multiple memory devices).)
The memory controller and the memory devices communicate through
signal wires or lines that form a bus. (A79[4:11-13].) Among other things, the bus
carries instructions issued by the memory controller to the memory devices, and it
also carries the data being stored in or retrieved from the memory devices.
Figure 2 of the 863 patent illustrates an example of a bus connected to a particular
type of memory device known as dynamic random access memory (or DRAM).
9

(A65[Fig. 2].)
While the improvements of the 863 patent are applicable to many types of
memory devices, they are particularly applicable to DRAMs. In DRAM systems,
large amounts of data are often transferred at high speed across the bus, so it is
important to orchestrate the timing of the transfers so no data loss occurs and to
ensure that the data bus is used as efficiently as possible.
2. Synchronous Transaction Timing
Before 1990 (the effective filing date of the 863 patent), conventional
DRAMs operated asynchronously, meaning they operated without being
synchronized to an external clock signal. (A1003-04[18].) Memory operations
within a DRAM occurred with timing determined by when the memory controller
drove asynchronous control signals to the DRAM.
10

In 1990, Rambuss founders, Dr. Michael Farmwald and Dr. Mark
Horowitz, invented a DRAM system with an architecture that substantially
increased system speed and efficiency. They made the DRAM synchronous rather
than asynchronous, meaning they moved information between the controller and
DRAM with reference to an external clock signal that provides a common timing
reference for the memory controller and the memory devices, and the DRAM
controlled its own internal timing. (A81[8:28-30].) The 863 patent discloses
several advantages enabled by the move from an asynchronous architecture to a
synchronous one, including the ability to have multiple read or write requests
pending in parallelan impossible feat with older asynchronous DRAM.
3. The 863 Patents Clocking Scheme
Fundamental to any synchronous system is its clocking scheme, and the
863 patent discloses a number of advances in this area. The bus carries an
external clock signal that continuously toggles in the manner shown in the
Figure 14 excerpt below.

(A76[Fig. 14].)
This external clock signal is used, among other things, to synchronize read
and write operations in the memory system. The synchronous DRAMs use this
11

signal to generate internal clock signals. Figure 13, shown below, illustrates an
example where two versions of an external clock signal, labeled Bus Clock1 and
Bus Clock2, are used to generate, from two sets of delay lines, Internal Clock 73
and Internal Clock Complement 74.

(A75[Fig. 13].) In this example, data is input and output synchronously with
respect to Internal Clock 73 and Internal Clock Complement 74. (A88[21:46-50],
A89[23:13-15].)
4. The Delay-Locked Loop of the 863 Patent
Given the important role the clocking scheme plays in a high-speed
synchronous memory system, Drs. Farmwald and Horowitz recognized that one
12

potential pitfall is inconsistency in the propagation of signals, like a clock signal,
through the circuits on the memory device. Some variation is inevitably
introduced to these propagating signals, such as through variations in the voltage
and temperature of the system. For example, lower voltages and higher
temperatures result in slower signals. If the variation in timing becomes significant
enough, which it may at the speeds contemplated in the 863 patent, memory
operations like sampling data from external signal lines can fail. Drs. Farmwald
and Horowitzs preferred approach utilizes a delay-locked loop to create, from an
external synchronous clock, an internal clock signal that has a specific timing
relationship to the external clock and that adjusts for changes in signal propagation
delays on the DRAM.
As Rambuss expert, Mr. Murphy, explains, a delay-locked loop is circuitry
on the device, including a variable delay line, that uses feedback to adjust the
amount of delay of the variable delay line and to generate a signal having a
controlled timing relationship relative to another signal. (A1006[24].) It is a
type of digital control circuit that, in the configuration used in the 863 patent,
measures the variation between an input clock signal and a delayed internal clock
signal. By using a feedback loop, the DLL can delay the internal clock signal such
that it has a controlled timing relationship with the input clock signal. (Id.)
13

The importance of a receiver DLL is directly related to the frequency of the
memory system. As the frequency of a memory system increases, data input
becomes more susceptible to minor variations in the data clock signal. For
example, in a 500 MHz system, one bus cycle spans only two nanoseconds
(0.000000002 seconds). (A86[17:65-18:1].) Timing variations on the order of a
few nanoseconds can catastrophically disrupt a system operating at this frequency
because it could shift the sampling point by a whole bus cycle, or even more. Not
compensating for these uncertain timing variations would greatly limit the
potential sampling rate and system frequency. However, in slower systems
running on the order of 10 MHz, one bus cycle spans 100 nanoseconds. At this
frequency, a system may easily ignore a propagation variation of a few
nanoseconds in either direction without needing specific structures like DLLs to
compensate for it.
Because the 863 patents system relies so heavily on its clocking
mechanisms and operates at high frequencies, the 863 patent discloses a
delay-locked loop circuit. The top portion of Figure 12 illustrates one DLL
implementation utilizing a signal feedback loop.
14

(A74[Fig. 12].)
DC amp 102 amplifies CLK1 and feeds it into variable delay line 103.
(A1013[47].) The output of variable delay line 103 feeds three additional delay
lines, including delay line 104. The output of delay line 104 loops back to the
clocked input receiver 101. The feedback loop is completed by passing the output
of the clocked input receiver 101 through a filter and sending the resulting signal
116 to delay line 103. The output timing of variable delay line 103 is adjusted via
the feedback line 116. The result is that the output 107 of delay line 104 has a
controlled timing relationship to the original CLK1 signal. (Id.; see also
A89[23:7-10].)
15

5. The Innovations Disclosed and Claimed in the 863
Patent Enabled Unprecedented Speed and Efficiency
By making the DRAM synchronous and developing a clocking scheme that
involves generating one or two internal clock signals from an external clock signal
using a delay-locked loop, the 863 patent enables high speed transfer of blocks of
data, particularly to and from memory devices, with reduced power consumption
and increased system reliability. (A78[1:21-24].) The specification describes a
memory system running at a very high clock rate (hundreds of MHz)
(A79[4:36-37]), and provides example bus rates of 500 MHz (A80[6:8-11];
A86[17:65-18:1]). At the time the inventors disclosed their inventions, the press
hailed the technology as a revolutionary memory chip technology that offers a
tenfold speed boost to memory chips. (A1188.) And as Rambuss expert,
Mr. Murphy, explained, generating an internal clock signal using a delay-locked
loop provided for a robust memory device that allowed the industry to move away
from the asynchronous memory model used at the time. (A1820[9].)
D. The Proceedings Below
1. Procedural Background Relevant to Microns Lack of
Standing
In 2007, Samsung requested inter partes reexamination of the 863 patent.
(A1940-49.) Samsung proposed several rejections of claims 1-35, including each
of the rejections of claims 21-23 now on appeal related to iAPX, Inagaki, and
Lofgren. (A1991-95.) In 2008, Micron filed its own inter partes reexamination
16

request seeking reexamination of claims 14-16 of the 863 patent, but Micron
based its request on different references and rejections than those proposed by
Samsung. (A2016-27.) The PTO granted Samsungs and Microns requests,
initiated separate inter partes reexaminations, and sua sponte merged the two
proceedings under 37 C.F.R. 1.989. (A2394-99.)
Samsung and Rambus settled their disputes in 2010, so Samsung withdrew
from its reexamination proceeding. (A2534.) Shortly after Samsung withdrew, the
examiner issued a Right of Appeal Notice confirming claims 29-35, but he
maintained some of Samsungs proposed rejections for claims 1-28. (A2540;
A2587-667.) The examiner did not maintain any of Microns proposed rejections.
(A2540; A2587-667.)
Rambus appealed the rejections of claims 1-28 to the Board. Micron
cross-appealed. Microns respondent brief addressed issues raised only in the
Samsung reexamination, including the rejections of claims 21-23 based on iAPX,
Inagaki, and Lofgren. (See, e.g., A2370-79.) Rambus petitioned to strike the
Samsung-related portions of Microns brief because, among other things, Micron
lacked standing to raise them under 35 U.S.C. 315(b). (A2782-88.) As Rambus
explained, that statute only gives a third-party requester a right to appeal issues
raised in its own reexamination request, not in anothers request. (Id.) The PTO
agreed that Microns respondent brief . . . does address the eight Samsung
17

proposed rejections that Micron did not propose in its initiated reexamination
proceeding. (A2799.) Nonetheless, the PTO dismissed Rambuss petition and
allowed Micron to continue to participate in the appeal. (A2800.)
After this decision, the examiner issued a new Right of Appeal Notice to
correct a clerical error in a heading that erroneously indicated a proposed rejection
had been adopted. (A1044-46.) The examiner noted that [a]ll other issues remain
the same. (A1046.) The parties filed their briefs again in response to the new
Right of Appeal Notice, and Micron repeated its arguments addressing Samsungs
issues in its respondent brief. (A2691-701.)
On appeal, the Board affirmed certain rejections of claims 1-28, but it did
not reach other rejections that it deemed cumulative. (A4.) Of particular relevance
to this appeal, the Board found claims 21-23 invalid as obvious over iAPX in view
of Lofgren and/or Inagaki in the following combinations originally proposed by
Samsung:
Claim iAPX Inagaki Lofgren
21 X X
22 X X
23 X X X

(A14-29.) The Board did not reach Microns cross-appeal. (A4.) Rambus sought
rehearing, which the Board denied. (A36-49.) Rambus now appeals the Boards
obviousness rejections of claims 21-23.
18

2. The PTOs Reliance on Lofgrens Teachings
a. Lofgren Discloses a Phase-Locked Loop That Times
External Control Signals
Lofgren is directed to producing delays on control output signals for use in
the external control of DRAMs, such as those provided from asynchronous DRAM
controllers to DRAMs. It does so through a delay line which incorporates a
phase-locked loop that seeks to achieve an output signal which is delayed by a
precise amount with respect to an input signal. (A3543[1:8-10, 1:43-45].)
Figure 1 of Lofgren, annotated below using excerpts of Figures 2A and 5 on the
Figure 1 overview, shows how the delay is achieved.

19

(A3538[Fig. 1]; A3539[Fig. 2A (excerpt)]; A3541[Fig. 5].)
Lofgren begins with an internal crystal oscillator 10 as a reference frequency
source. Phase detector 16 compares the crystal oscillators signal, OSC, with a
delayed version of the oscillators signal, DOSC, produced by variable delay block
12. (A3543[1:103-2:5].) An error signal 14 is generated to adjust the delay
through block 12 such that block 12 will delay the signal labeled OSC by exactly
one period. (Id.) Variable delay line 12 is made up of sixteen matched delay
elements labeled D1-D16 in the Figure 2A excerpt above. Each contributes 1/16
of the delay through delay block 12 such that each provides a delay equal to 1/16
of the period of the oscillator 10. By replicating a set of the same delay elements
from block 12 again in block 18, the same control signal (error signal 14) is used to
cause the delay through the elements in block 18 to be precisely determined and
maintained. This allows a precise delay based on 1/16 increments of the
oscillators period to be applied to the control signal DATA based on selecting
one of the output taps in block 18.
Lofgren indicates that these fixed, more precise delays provide optimum
timing for control of high speed dynamic RAM devices, which comprise the main
memory of virtually all personal computers. (A3543[1:14-18].) These delays are
understood to achieve timed separation between memory controller output signals
20

used to control asynchronous DRAMs of the day (e.g., between memory control
signals like those referred to as /RAS and /CAS, as well as the address signals).
Lofgrens oscillator is only used as a yardstick for a known amount of time
that is divided into a known number of delay increments that can be applied to the
DATA signal, which is not synchronized to the oscillator. Nowhere does Lofgren
teach using the PLL circuit inside a memory device, generating an internal clock
signal in a memory device from an external clock signal, or generating an internal
clock signal from an external clock signal and inputting data synchronously with
respect to the internal clock signal. (A1026[89].)
b. The Examiner and Board Found the Delay Locked
Loop for Generating One or Two Internal Clock
Signals Satisfied by Lofgrens Phase-Locked Loop for
Timing External Control Signals
The examiner found that Lofgrens PLL satisfies the claimed delay locked
loop features for generating an internal clock signal (claim 21) and first and
second internal clock signals (claim 23). In reaching this conclusion, the
examiner did not explain how Lofgrens circuitry for creating delays on external,
non-clock control signals unrelated to the PLL oscillator taught generating internal
clock signals from an external clock signal and inputting data synchronously with
respect to the internal clock signals, as recited in the appealed claims. (See A1137-
41.)
21

Perhaps recognizing this issue, in another proceeding involving a Farmwald
patent, the same examiner withdrew a rejection against similar DLL claim
language. In the concurrent ex parte reexamination of the related 918 patent, the
examiner found that Lofgren is direct[ed] to issuing precise delays with respect to
a control signal and does not teach generating an internal clock signal from an
external clock signal. (See A2348.) Based on this understanding, the examiner
ultimately withdrew the Lofgren rejection. (A2349.)
Notwithstanding the examiners withdrawal of the Lofgren DLL rejection in
another Farmwald reexamination, the Board affirmed the examiners rejections
here. (A14-17.) The Board found Lofgrens PLL to be the claimed DLL based in
part on statements from Rambuss experts in other proceedings. The Board
characterized these statements as establishing that DLLs and PLLs can be used
for the same or similar purposes. (A14.) The Board then incorporated by
reference certain Micron arguments regarding how Lofgren allegedly teaches the
DLL of claims 21 and 23. (A15; A29.)
The Board left open the question of whether it was relying on Lofgrens
circuitry specifically or some other undisclosed circuitry, stating that Lofgren
discloses or at least suggests a delay locked loop as required by claim 21.
(A14-15 (emphasis added).) And although appealed claims 21 and 23 recite not
only a DLL, but a DLL in a synchronous memory device that generates an
22

internal clock signal or first and second internal clock signals used to input
synchronous data, the Board did not explain how the prior art suggests that
Lofgrens circuitry could be used to generate those claimed clock signals. (See
A14-17.) The Board also did not address Rambuss unrebutted expert testimony
that Lofgrens circuit is directed to timing external, non-clock control signals as
opposed to generating one or more internal clock signals, as claimed.
(A1026[89-90].)
3. The PTO Combined Inagaki and Lofgren with iAPX
a. Inagaki Discloses an Asynchronous System That Uses
Pulsed Signals During Data Transfers
Inagaki is a J apanese reference that discloses a conventional asynchronous
memory system circa 1981. (A1029-30[102-105]; A3512-35.) Inagaki claims to
improve over other conventional asynchronous memory devices by transferring
data at twice the conventional speed by using both the rising and falling edges of
an intermittent pulsed signal. (A3514.) In particular, in the figure below, Inagaki
discloses a pulsed signal that is toggled during periods of data transfer. (A3515;
A1030[104].)
23

(A3520.) Signals 1 and 2 are then derived from both the rise and fall of the
signal. Signals 1 and 2 cause a circuit called a shift register to shift data
through it, which allows data to be output or input. (A3515.)
b. iAPX Discloses a 10 MHz System That Fully Utilizes
the Edges of Its Two External Clock Signals, CLKA
and CLKB
iAPX discloses a system designed in 1982 by Intela Rambus licensee
(A3198[98])that operates at a speed of 10 MHz. (A2802.) It discloses a
memory module comprising, among other things, a Memory Control Unit
(MCU) and several connected asynchronous DRAM chips. The MCU receives
two external clock signals, CLKA and CLKB, carried on an external memory bus
(MACD). (A3102.) The rising and falling edges of both external clocks are
used in the bus protocol, with one edge aligned to data output and the other three
24

edges serving other purposes. (Id. (showing information aligned to the output
drive of both edges of both clocks).) None of the clock edges are free for any
other purpose, such as transmitting additional data.
c. The Board Combined iAPX and Inagaki Primarily to
Take Advantage of Dual-Edged ClockingEven
Though Claims 22 and 23 Recite Two Internal Clocks,
Not Using Both Edges of a Single Clock
On appeal, the Board affirmed the examiners obviousness rejections
combining Inagaki with iAPX. (A17-29.) The Board acknowledged that iAPX
already uses both edges of its two clocks (A21), but nonetheless found that
Inagaki teaches that data bus systems, like that of iAPX, could have benefited by
outputting data onto bus lines by using the rising and falling edges of a clock to
double the normal data transfer speed (id.). This, like most of the Boards
justifications for combining iAPX with Inagaki, focuses on the advantages of using
both edges of a single clock signal, despite that (1) the appealed claims never refer
to dual-edged clocking, and (2) the appealed claims instead recite that data is
input synchronously with respect to two clock signals (i.e., the first and second
internal clock signals). (A90[26:15-22].)
While the Board at times acknowledges the two-clock-signal requirement of
appealed claim 22 and its dependent claim 23, at other times it expressly treats
those claims as though they require dual-edged clocking by incorrectly stating that
claim 22 does not have significant interrelated features other than those required
25

to output data synchronously using two edges of a clock signal. (A24 (emphasis
added).) The Board perpetuates this misunderstanding throughout its analysis by
focusing almost exclusively on combining Inagakis alleged dual-edged clocking
features with iAPX. (See A20 (Inagaki teaches using dual edges of a single
clock . . . .); A21 (both clock edges); A22 (Inagakis teachings, and the iAPX
use of dual edges, also evidence a reasonable expectation of success in using dual
clock edges on data for increased speed. (emphasis added)); A23-24 (Making
other required modifications to increase the data speed by using both clock
edges . . . .); A28 (motivated by Inagakis teaching of using rising and falling
clock edges).)
The Board also repeats the examiners statement that in Inagakis system
[t]he two internal clocks allow for the input/output of data to be received/output at
twice the data rate as the external clock. (A21 (quoting A1143).) Although this
statement references two internal clocks, the Board immediately interprets the
examiners reasoning as relating to dual-edged clocking, not generating two clock
signals:
As the Examiner reasons, skilled artisans would have
recognized that Inagaki teaches that data bus systems,
like that of iAPX, could have benefitted by outputting
data onto bus lines by using the rising and falling edges
of a clock to double the normal data transfer speed.

26

(Id. (emphasis added).) Thus, this reason is similar to the others that pertain to
dual-edged clocking, and illustrates the Boards confusion regarding the scope of
the appealed claims.
Only one of the Boards reasons for combining Inagaki with iAPX involves
generating two clock signals. It contends that the iAPX system could have been
modified to include the external slower Inagaki clock as a trigger for the faster
CLKA and/or CLKB. (A24.) The slower external clocks rising and falling
edges would trigger the existing CLKA and CLKB, with the external clocks rising
and falling edges corresponding to the existing rising edges of faster CLKB and/or
CLKA. (A25.)
The Board, however, does not explain how the generated CLKA and CLKB
would correspond to the claimed first and second internal clock signals
(emphasis added). (See A24-25.) The Boards omission is significant because it is
undisputed that the iAPX CLKA and CLKB signals are external clock signals.
The examiner repeatedly referenced external clock signal CLKA (A1097;
A1099; A1104-05) and confirmed that the MACD bus carrying those clock signals
is an external bus (A1094). Samsungthe party who requested reexamination
based on iAPX and Inagakialso refers to CLKA as external clock signal
CLKA (A3566; A3568, A3570), and refers to the MACD memory bus as an
external bus (A1980). The Board did not cite any evidence rebutting these facts.
27

Quite the opposite, the Boards decision says that the iAPX memory device
receives external clock signalsan apparent reference to CLKA and CLKB, and
acknowledging that they are external, not internal. (A17.)
In spite of these facts, the Board placed the burden on Rambus to disprove
combinability, concluding that Rambus fails to present evidence that skilled
artisans would have been unable to modify interrelated parts to combine iAPX
with Inagaki in the manner claimed. (A24.)
d. The Board Combined iAPX and Lofgren, Even
Though iAPX Has No Identifiable Need for Lofgrens
Circuitry
The Board combined iAPX with Lofgren because iAPX requires precise
delays to output data and . . . Lofgrens system supplies such delays. (A15 (citing
A1140.) The Board did not explain why iAPXs 10 MHz system required precise
delays other than to mention that iAPX has many different inputs and outputs.
(See id.) The Board offered no explanation of how the mere presence of inputs and
outputs is sufficient to warrant the additional complexity and cost of implementing
Lofgrens circuitry. (See id.)
Unrebutted expert testimony explains that iAPX has no need for Lofgrens
PLL. (A1025[86]; A1026-27[92].) In particular, Rambuss expert explained
how the timing variations in iAPX are inconsequential, especially when compared
with the clock speed. (A1025[86]; A1026-27[92].) The Board dismissed this
28

evidence, stating that faster speeds would have been available at the time of the
invention, relying on features not disclosed anywhere in iAPX or Lofgren. (A16.)
It also reasoned that iAPX could have benefited from Lofgrens more precise
delays, even if it ran at a slower speed than 10 MHz since Lofgren can account for
voltage and temperature variations. (Id.) The Board did not address the unrebutted
expert testimony to the contrary. (See id.)
e. The Board Dismissed the Objective Evidence of
NonobviousnessWhich Was Directly Tied to the
Claimed Featuresfor Lacking a Nexus to the Claims
Rambus provided the Board with objective evidence demonstrating
nonobviousness, including a long-felt need for faster memory, skepticism of others
regarding Rambuss solution to this need, failure of others to develop a workable
solution, commercial success, and praise by others.
By 1990, when the application leading to the 863 patent was filed, many
recognized the need for ways to improve memory performance. Giants in the
industry, such as IBM and the Burst EDO memory manufacturers, attempted to fill
this need, but they were unsuccessful. (A1007[28].) Inventors Farmwald and
Horowitz, however, filled this need by inventing a way to enable high-speed
memory performance using internal clocks where timing uncertainty is reduced.
They recognized that by adding a delay locked loop to an internally clocked
29

memory device operating synchronously, it was possible to achieve unprecedented
system speeds. (A1006[24].)
Upon learning of these inventions, the industry was skeptical that one could
even put a delay-locked loop on a DRAM memory device or that such a device
could reach the high speeds touted by the inventors. As the Federal Trade
Commission (FTC) found in its initial decision after an extensive trial:
The response to the early presentations in 1989-90 was
just disbelief that Drs. Farmwald and Horowitz would
be able to achieve a 500 megabit per second DRAM data
rate. People who listened to these presentations were
also skeptical about many of the specific features of the
technology. For example, it was felt that putting registers
on DRAM was too expensive for a commodity part and
that one could not put a phase locked loop or a delay
locked loop on the DRAM itself.
(A3199[105] (emphases added) (citation omitted).) Potential licensees also
expressed concern over whether a computers drivers and receivers could work at
these frequencies (A1198), and system companies were skeptical that [Rambus
could] operate reliably at these speeds (A1211).
Overcoming this initial skepticism, Rambuss technology came to be viewed
as essential by the industry. The FTC noted that the industry considered a number
of potential alternatives to placing a DLL on a memory device, but it rejected each
alternative as unsatisfactory. (A3375-79[1350-1387] (dismissing alternatives
such as placing a DLL on a memory controller as opposed to each memory device,
30

using a vernier circuit to provide a delay, and increasing the number of pins on the
memory device).) It concluded that [e]ach of these alternative[s] has performance
disadvantages when compared to Rambuss on-chip PLL/DLL technology.
(A3381[1397].)
Rambuss DRAM technology was widely considered revolutionary in the
industry. (A3197[91]; see also A1188 (stating in March 1992 that Rambus had a
revolutionary memory chip technology offer[ing] a tenfold speed boost to
memory chips); A1205; A1212; A1216; A1193 (describing Rambuss approach
as a fundamental change in the design of computer memory systems).) And in
receiving an award from the Institute of Electrical and Electronics Engineers, the
organization stated that Dr. Horowitzs research has changed the way an entire
industry thinks about memory interfaces and fostered a revolution in that industry.
Memory access bandwidths have increased by more than an order of magnitude in
just a few years as a result of the ideas he pioneered. (A1701.)
As a result of the high performance enabled by the claimed features, the
inventions claimed in the 863 patent have been incredibly successful. High-speed
memory devices with the claimed features have all but replaced conventional
asynchronous DRAM devices and other memory devices in most applications.
(A1007[26-28].) Without an internal clock generated from an external clock
signal, and without a delay-locked loop to ensure the necessary timing
31

relationships, a system could not reliably operate at speeds of hundreds of MHz
and beyond. (Id.)
The success of the claimed inventions is further confirmed by the many
licensees of the 863 patents technology. By J une 1992, Rambus had signed
technology license agreements with three of the top five DRAM manufacturers at
the timeNEC, Toshiba, and Fujitsu. (A1197-98; A3198[98]; A3202[135];
A1200 (two of those manufacturers signed up right away).) By J anuary 1994,
Rambus had signed license agreements with four other manufacturers, including
Intel, which designed the system described in iAPX that the Board contends would
have been obvious to modify. (A3198[98].) Since then, Rambus has added at
least six more licensees. (A2144.)
No party submitted expert testimony rebutting these facts or challenging
Rambuss expert. And despite that this evidence either explicitly addressed the
claim language (e.g., the FTCs finding of skepticism regarding the DLL) or
flowed as a direct result of the claimed features (e.g., the high system speed), the
Board dismissed this objective evidence of nonobviousness for lacking a sufficient
nexus to the claims. (A29-34.)
32

E. The Courts Recent Decision in Rambus Inc. v. Rea Vacated
the Boards Obviousness Findings in a Reexamination of
Another Farmwald Patent
This Court recently decided an appeal from a Board decision involving
another patent in the Farmwald patent family. See Rambus Inc. v. Rea, No. 2012-
1634 (Fed. Cir. Sept. 24, 2013). Among other things, the Court found that the
Board erroneously placed the burden on Rambus to prove that its claims were not
obvious. Id., slip op. at 10. In concluding the Board erred, the Court relied on
two of the Boards statements that are essentially identical to statements the Board
made in the 863 reexamination currently on appeal:
Board Statements Found Legally
Erroneous in Appeal No. 2012-1634
Board Statements in the
863 Reexamination
Rambus ha[d] not demonstrated that
skilled artisans . . . would not have been
able to arrive at the broadly claimed
invention. Slip op. at 11 (alteration in
original) (citation omitted).
Rambus has not demonstrated that
skilled artisans . . . would not have been
able to arrive at the broadly claimed
invention. (A28.)
Rambus fail[ed] to present evidence
that skilled artisans would have been
unable to modify iAPX to achieve the
claimed invention[]. Slip op. at 11
(alteration in original) (citation omitted).
Rambus fails to present evidence that
skilled artisans would have been unable
to modify iAPX to achieve the claimed
invention. (A24.)

The Court also found that the Board erred in its treatment of objective
evidence of nonobviousness. Rambus, No. 2012-1634, slip op. at 13. In
particular, [t]he Board erred when it found that Rambuss objective evidence of
nonobviousness lacked a nexus because it related to unclaimed features. Id.
33

Rambus had presented evidence related to the claimed features, and the Board did
not point to any contrary evidence in the record. Id. at 14.
Instead, the Board . . . erroneously found that Rambuss evidence relating
to high-speed memory systems was not commensurate with the scope of the claims
because the claims do not recite a specific clock speed and therefore embrace slow
memory devices. Id. (citation omitted). The Board relied on a virtually identical
rationale in the 863 reexamination, stating that while Rambus argues that the
memory devices solve a memory bottleneck problem and obtain high-speed
performance . . . , the claims read on slow memory devices, since the claims do not
recite any speed (as a functional limitation) and do not recite other sufficient and
necessary circuitry to obtain such speed. (A32 (citation omitted).) But as the
Court noted in the context of the Rambus Inc. v. Rea appeal, [s]uch a strict
requirement was improper. Objective evidence of nonobviousness need only be
reasonably commensurate with the scope of the claims, and we do not require a
patentee to produce objective evidence of nonobviousness for every potential
embodiment of the claim. Rambus, No. 2012-1634, slip op. at 14 (quoting In re
Kao, 639 F.3d 1057, 1068 (Fed. Cir. 2011)).
The Court also faulted the Boards analysis of Rambuss licensing evidence.
The Board had discounted Rambuss licenses because competitors have many
reasons for taking licenses which are not necessarily related to unobviousness. Id.
34

at 15 (citation omitted). In the 863 reexamination currently on appeal, the Board
similarly dismissed Rambuss licensing evidence, stating that competitors often
take licenses for commercial or other reasons having nothing to do with
unobviousness. (A31.) The Court, however, found that this type of finding
lacks any supporting evidence. Rambus, No. 2012-1634, slip op. at 15.
Finally, the Court found error in the Boards dismissal of evidence related to
features that were allegedly known in the prior art. Id. The Board made similar
findings here in the 863 reexamination, stating that single chip synchronous
memory devices were known, as were DRAMs, precharging and DLL circuits, as
the prior art discussed supra also discloses. Hence, the record suggests that at least
part of any commercial success would have been due to features already in the
prior art, such as the popular DRAM memory chip. (A31.) The Court noted that
this view ignored the claimed invention as a whole, and that [a]t least some of
Rambuss objective evidence of nonobviousness pertained to Rambuss overall
memory device architecture. Rambus, No. 2012-1634, slip op. at 15. According
to the Court, the proper approach is to parse the evidence that relates only to the
prior art functionality and the evidence that touted Rambuss patented design as a
whole. Id. at 15-16. For these reasons and others, the Court vacated the Boards
obviousness findings and remanded. Id. at 16.
35

IV. SUMMARY OF ARGUMENT
In finding appealed claims 21-23 obvious based on iAPX in view of Inagaki
and/or Lofgren, the Board reversibly erred in its claim-construction and validity
analyses. By allowing the delay locked loop features (1) to permit the claimed
external clock signal to encompass Lofgrens internal oscillator signal, and (2) to
permit the claimed internal clock signal[s] for synchronously inputting data to
encompass Lofgrens non-clock, non-synchronous external control signals, the
Board implicitly construed these terms contrary to the relevant intrinsic and
extrinsic evidence. The Board also provided such an ambiguous rejection that it
cannot be sustained.
The Board compounded these errors by placing the burden on Rambus to
disprove the obviousness of combining iAPX with Inagaki and/or Lofgren, all
while ignoring or dismissing unrebutted expert testimony demonstrating why these
combinations would have been infeasible and beyond the purview of those having
ordinary skill in the art in 1990. In holding otherwise, the Board rationalized its
rejections through hindsight and conjecture, and dismissed Rambuss objective
evidence of nonobviousness using the same rationales the Court found erroneous in
Rambus Inc. v. Rea, No. 2012-1634.
Finally, the Board erred in granting Micron standing to participate in the
appeal of Samsungs reexamination.
36

V. ARGUMENT
A. Standards of Review
[C]laim construction by the PTO is a question of law that [this Court]
review[s] de novo . . . . In re Baker Hughes Inc., 215 F.3d 1297, 1301
(Fed. Cir. 2000). Obviousness is a question of law that [this Court] review[s]
de novo with underlying factual findings. In re NTP, Inc., 654 F.3d 1279, 1297
(Fed. Cir. 2011); see also In re ICON Health & Fitness, Inc., 496 F.3d 1374, 1378
(Fed. Cir. 2007) (Although based on determinations of underlying facts, which we
review for substantial evidence, the ultimate conclusion of obviousness is a legal
question, which [this Court] review[s] de novo.).
B. The Board Erred in Implicitly Construing Delay Locked
Loop for Generating One or More Internal Clock Signals
to Include Lofgrens Phase-Locked Loop for Delaying
Non-clock Control Signals
By concluding that Lofgren teaches the claimed generating an internal
clock signal, using a delay locked loop and the external clock signal (claim 21),
and generating first and second internal clock signals using clock generation
circuitry and the external clock signal (claim 22) wherein the first and second
internal clock signals are generated by a delay lock[ed] loop (claim 23), the Board
implicitly misconstrued the delay locked loop features.
As the same examiner who reexamined the 863 patent found in a
reexamination of another Farmwald patent, Lofgrens circuitry relies on an internal
37

crystal oscillator to generate its output and does not rely on an external clock
signal, as claimed: Lofgren does not show that this signal [i.e., the alleged
internal clock signal] is generated using an external clock signal. As noted above
and within Lofgren, an internal crystal oscillator is used. (A2347; see also A2348
(Lofgren does not support using an external clock signal (as noted above Lofgren
uses an internal crystal oscillator) . . . .).) He therefore concluded that the
disclosed crystal oscillator [is] different from the external clock signal. (A2347.)
The examiner also questioned whether Lofgren could even function if modified to
use an external clock signal: It is unknown whether the phase locked loop
circuitry of Lofgren would work with an outside clock signal or any other clock
signal other than its own crystal oscillator. (Id.)
The examiners findings distinguish Lofgrens circuitry on the basis of the
claimed external clock signal, but unrebutted expert testimony further
distinguishes Lofgren based on the claimed internal clock signals. In particular,
Rambuss expert explained that Lofgren is directed to external control of memory
devices, not to the generation of an internal clock signal in a memory device.
(A1026[90] (emphases added).) Indeed, Lofgren never discloses generating or
outputting a clock signal of any type using delay block 18, let alone one that would
be internal to a synchronous memory device and used to synchronously input data,
as claimed. Each of Lofgrens references to clock periods or clocking relates to
38

Lofgrens internal reference signal (e.g., from the internal crystal oscillator), not to
the signals generated on Lofgrens delayed output where the alleged internal clock
signals would appear. (See generally Lofgren, A3536-50.)
No party offered expert testimony to contradict Rambuss expert, so the
Board did not rely on any. Instead, the Board rejected this internal/external
distinction as another form of the single chip argument, which refers to an
argument not advanced in this appeal about what constitutes a memory device in
the context of iAPX. (A16.) The Board did not recognize or address that this
argument is actually about the disclosure of Lofgren itself and how it fails to
disclose circuitry for doing what is claimedsynchronously input data using an
internal clock signal generated from an external clock signal that accompanies the
data. The claim words internal and external must be given weight.
The Board also determined that [i]n light of the 863 patent, including its
Figure 12, and past statements by Rambus, Lofgren discloses or at least suggests a
delay locked loop as required by claim 21. (A14-15.) The Board does not
explain how the 863 patent itself (including Figure 12) supports its obviousness
finding. And, according to the Board, the past statements by Rambus merely
indicate that a DLL and PLL can be used for the same or similar purposes.
(A14.) Even if one assumes that the Board has accurately characterized Rambuss
prior statements, those statements do not establish that any PLL, let alone
39

Lofgrens PLL, has all of the claimed features. The claims do not recite merely a
DLLthey recite a DLL that functions in a specific way to generate one or more
internal clock signals useful for inputting synchronous data. Thus, the alleged
general interchangeability of PLLs and DLLs does not establish that Lofgren
discloses the claimed features.
Also problematic is that the Board does not identify whether it relies on
Lofgrens circuitry or some other unspecified circuitry. As the Board stated,
Lofgren discloses or at least suggests a delay locked loop as required by
claim 21. (A14-15 (emphasis added).) This statement suggests that the Board
doubts its analysis of Lofgren. It also falls short of the requirement that the Board
must explain the basis for its rulings sufficiently to enable meaningful judicial
review. In re Hyatt, 211 F.3d 1367, 1371 (Fed. Cir. 2000). Necessary findings
must be expressed with sufficient particularity to enable the court, without resort to
speculation, to understand the reasoning of the Board . . . . Gechter v. Davidson,
116 F.3d 1454, 1457, 1459 (Fed. Cir. 1997) (vacating Board decision that lacks
the level of specificity necessary for our review). The Board, however, provided
no explanation regarding the critical facts of how its suggest[ed] delay-locked
loop would differ from Lofgren or how it would function. Only speculation can
fill the gaps, so the Boards analysis cannot support a finding of obviousness.
40

Ultimately, the Board misconstrued the claimed delay locked loop and
related clock signal features to read multiple limitations out of the claim. This
erroneous claim construction (1) permitted the claimed external clock signal to
encompass Lofgrens internal oscillator signal, and (2) permitted the claimed
internal clock signal[s] to encompass Lofgrens external control output signals
that are not clock signals. The Board also provided such an ambiguous rejection
that it cannot be sustained.
C. The Board Erred in Finding It Obvious to Combine iAPX
with Inagaki and/or Lofgren
Even if the cited references had taught the claimed features, it would not
have been obvious to one of skill in the art
3
to combine Inagaki and/or Lofgren
with iAPX to achieve the claimed inventions. The Board erred in finding
otherwise.
1. The Board Erroneously Placed the Burden on
Rambus to Disprove Obviousness
The Board erred at the outset by placing the burden of disproving
obviousness on Rambus, the patentee. For example, the Board stated that
Rambus has not demonstrated that skilled artisans . . . would not have been able

3
The Board did not define what it considered to be the level of ordinary skill
in the art. However, Rambuss expert stated that a person of ordinary skill in the
art as of the April 18, 1990, priority date of the 863 patent would have had a
Bachelor of Science degree in Electrical Engineering and 3-5 years of experience
designing memory circuits such as DRAMs. (A1819[4].)
41

to arrive at the broadly claimed invention. (A28.) It also said that Rambus fails
to present evidence that skilled artisans would have been unable to modify
interrelated parts. (A24.) Based on the Boards virtually identical statements in a
reexamination of another Farmwald patent, this Court found that the Board
erroneously placed the burden on Rambus to prove that its claims were not
obvious. . . . That was legal error. Rambus Inc. v. Rea, No. 2012-1634, slip op. at
10-11. This fundamental legal error incorrectly skewed the Boards obviousness
analysis, and perhaps explains the several other errors found throughout the
Boards obviousness analysis and discussed below.
Inagaki with iAPX
The Board erred in combining Inagaki with iAPX to find claims 22 and 23
obvious. As explained in Section III.D.3.c, supra, all but one of the Boards
reasons for combining those references pertains to using both edges of a single
clock signal, while the claims actually recite that data is input synchronously with
respect to two clock signals (i.e., the first and second internal clock signals).
(A90[26:15-22].) This error apparently stems from the Boards misunderstanding
of the scope of the claims. The Board made its misunderstanding explicit by
incorrectly stating that claim 22 (and therefore also its dependent claim 23) does
not have significant interrelated features other than those required to output data
synchronously using two clock edges of a clock signal. (A24 (emphasis added).)
42

Relying on this misunderstanding, the Board repeatedly identified how
combinability was desirable so iAPX could benefit from the alleged dual-edged
clocking features of Inagaki. See Section III.D.3.c, supra (identifying repeated
references to dual-edged clocking in the Boards analysis). But as the Supreme
Court has said, courts must examine evidence of combinability to determine
whether there was an apparent reason to combine the known elements in the
fashion claimed by the patent at issue. KSR Intl Co. v. Teleflex Inc., 550 U.S.
398, 418 (2007) (emphasis added). The Boards reasoning unrelated to the claims
should therefore carry no weight.
4

4
Even if the Boards reasoning had been relevant to the claims, it still would
have been incorrect because one of ordinary skill in the art would not have
modified iAPX to incorporate dual-edged data clocking. As the Board
acknowledges, [t]he iAPX system employs dual edges of two different periodic
clocks (i.e., CLKA, CLKB). (A20.) Therefore, iAPX has no free clock edges to
be able to incorporate Inagakis alleged dual-edged data clocking. Doing so would
require removing features from iAPX that already rely on CLKA and CLKBs four
edges, as the Board acknowledges. (A24 ([S]killed artisans could have modified
the iAPX system in view of Inagakis clocking scheme by dropping unneeded
functions.).) The Board cites no evidence to support this hypothesis, and the
Board made no showing that anyone of skill in the art would have considered any
of iAPXs functions unneeded. (See id.) To the contrary, the evidence
demonstrates that one of ordinary skill in the art would have simply used a faster
clock in iAPX (assuming the system could even support faster operations) as
opposed to the substantial modification suggested by the Board. (A1031[108]
([I]f the iAPX 432 system could support faster operations, one of skill in the art
would use a faster clock rather than using pulsed signals unrelated to the clock.).)
43

The Boards only justification that relates to generating two clocks involves
modifying iAPX to include the external slower Inagaki clock as a trigger for the
faster CLKA and/or CLKB. (A24.) The Board hypothesized how this could be
done: The slower external clocks rising and falling edges would trigger the
existing CLKA and CLKB, with the external clocks rising and falling edges
corresponding to the existing rising edges of faster CLKB and/or CLKA. (A25.)
The Board cited no expert opinion to support this hypothesis that a person of
ordinary skill in the art in 1990 would have been motivated to add a master clock
to the two clocks of iAPX. (A25-26.)
Moreover, the Board-crafted circuit design ignores how the prior art
functions and is therefore unworkable as articulated. It is undisputed that CLKA
and CLKB are external clock signals in iAPX that are required to be transmitted to
all bus devices, as opposed to the internal clock signals claimed. Requester
Samsung, the examiner, and Rambus all refer to those signals and the bus they
travel on as being external. See Section III.D.3.c, supra (citing repeated references
in the examiners Right of Appeal Notice and in Samsungs reexamination
request). Thus, a combination of Inagaki with iAPX that generates CLKA and
CLKB as faster internal clock signals, as the Board alleges, ignores the
requirements of the iAPX system and would not have resulted in a workable
44

combination because iAPX requires CLKA and CLKB to be external bus signals.
The Boards findings to the contrary were erroneous and should be reversed.
Lofgren with iAPX
The Board erred in finding that Lofgren discloses the claimed features for
the reasons discussed in Section V.B, supra, but the Board also erred in finding
that one of ordinary skill in the art would have modified iAPX in view of Lofgren,
and in finding that the prior art suggests a modification that looks anything like the
claims.
iAPX operates at 10 MHzwhere adequate timing margin already exists to
input data without Lofgrens circuitryso one of ordinary skill in the art in 1990
would not have incurred the additional cost, design time, and device complexity of
integrating Lofgrens circuitry into iAPX. At 10 MHz, iAPXs clock period is 100
nanoseconds, while unrebutted expert testimony demonstrates that fluctuations due
to temperature or voltage would be on the order of only a few nanoseconds.
(A1025[85-86]; A1026-27[92].) Introducing the claimed delay-locked loop
would have had no meaningful impact because the system could already tolerate
these variations, which are minor (a few percent) relative to the clock period.
(A1025[85-86]; A1026-27[92].)
The Board wrongly discounts this factor, in essence imagining a problem for
iAPX where the reference itself and the unrebutted testimony show that none
45

existed. The Board contends that iAPXs data inputs and outputs still could have
benefited from the more precise delays of Lofgreneven if run at speeds slower
than 10 MHz. (A15-16.) The Board never explains why this would be true other
than to reference voltage and temperature variations, but the Board cites no
evidence demonstrating that those variations have any significance relative to
iAPXs clock period. (A16.)
Perhaps recognizing this issue, the Board states that faster speeds [than in
iAPX] would have been available at the time of the invention as Micron argues.
(Id.) In doing so, the Board conjured up a nonexistent system not taught in iAPX
and Lofgren. Even if one would have attempted to achieve data transfer speeds
that might have benefited from the claimed delay-locked loop in 1990an
unlikely scenario given the skepticism in the industry when the inventors disclosed
systems operating at hundreds of megahertz (see Section III.D.3.e, supra)the
combined references fail to teach the claimed solution for the reasons discussed in
Section V.B, supra.
Finally, the Board contends that, in another proceeding, Rambus agreed
with the examiner that combining Lofgren with the iAPX Manual would have been
obvious. (A15 n.10.) This is a significant mischaracterization. Rambus disputed
this issue repeatedly in that proceeding, including on appeal to the Board. Indeed,
Rambuss appeal brief to the Board contains an entire section under the heading
46

iAPX . . . Would Not Have Been Combined With Lofgren, which explains
several reasons why the Boards combination is in error. (A2762-64.) Because the
PTO had already confirmed some of the claims of the patent at issue in that
proceeding, however, Rambus declined to incur the cost of further appealing the
rejection of the other claims. This decision not to appeal, however, in no way
indicates that Rambus agreed with the examiners obviousness findings,
particularly where Rambus disputed them throughout that proceeding.
4. Objective Evidence Demonstrates Nonobviousness
Even if the Board had established a prima facie case of obviousness (which
it did not), Rambus rebutted that case with objective evidence of nonobviousness.
This Court has described objective evidence of nonobviousness as a tool to
inoculate the obviousness analysis against hindsight. Mintz v. Dietz & Watson,
Inc., 679 F.3d 1372, 1378 (Fed. Cir. 2012).
As explained more fully in Section III.D.3.e, supra, Rambuss objective
evidence of nonobviousness shows that in 1990, when Drs. Farmwald and
Horowitz filed the application leading to the 863 patent, they ushered in a new era
in memory technology. Their inventions helped solve a long-felt need for
improved memory-system performance (A1180-82[267:20-269:8, 270:15-271:9,
275:14-277:1]; A1007[26]; A1188; A1190; A1193; A1194; A1212); succeeded
when others like IBM had failed (A1007[28]); overcame the initial skepticism of
47

experts to become the dominant technology in the industry (A1265[105]); found
followers in three of the top five DRAM manufacturers at the time (NEC, Toshiba,
and Fujitsu) and several others who each licensed its technology (A1675-76[n.543
(second paragraph)]; A1007[27]); and earned the inventors accolades for their
pioneering work (A1700-01).
In some instances, the evidence expressly addresses the claim language. For
example, the initial decision of the FTC credited witness testimony establishing
skepticism related to placing a DLL on a DRAM. (A3199[105].) It also found
that alternatives to Rambuss DLL technology were inferior. (A3375-79[1350-
1387]; A3381[1397].) In other instances, the evidence addresses features that
flow as a direct result of the claimed features, such as the high system speed those
features enable. See Section III.C.3.e, supra.
The Board erred in failing to credit this evidence by finding that it likely
flows from a variety of several unclaimed features. (A29-30.) None of the
allegedly unclaimed features identified by the Board (see A30), however, can
detract from the fact that claimed features were specifically identified in the
evidence Rambus provided.
To the extent the evidence pertains to the speed enabled by the claimed
features, the Board incorrectly discounted this evidence as lacking a nexus because
the claims do not recite any speed (as a functional limitation) and do not recite
48

other sufficient and necessary circuitry to obtain such speed. (A32.) This Court
rejected the Boards nearly identical reasoning in Rambus Inc. v. Rea as being
overly strict and inconsistent with the law. Rambus, No. 2012-1634, slip op. at 14.
Moreover, the Boards reasoning ignores that the FTCs findings directly link
speed with the claimed DLL. Thus, while speed is not expressly recited in the
claims, the evidence of record demonstrates that the speed-related evidence has a
nexus to the claimed inventions.
Rambuss commercial success also supports the nonobviousness of the
appealed claims. Rambuss many licensees paid significant sums for, and also
changed their architectures to accommodate, Rambuss technology. See Section
III.D.3.e, supra. Those licenses specifically covered the appealed claims, and
news articles link the licenses to the claimed technology, such as by emphasizing
the high speed the claimed features enable. Id.; see also A1197 (licensees had paid
substantial license fees to participate in the technology, which the article
described as a unique 500-MHz, 9-bit data channel designed to burst the
bottleneck between processors and DRAMs in desktop systems).
The Board nonetheless dismissed this evidence, finding that competitors
may take licenses for reasons unrelated to nonobviousness. (A31.) The Court
rejected a similar rationale in Rambus Inc. v. Rea because there was no evidence to
support the Boards findings. Rambus, No. 2012-1634, slip op. at 15. Here, the
49

Board also cited no evidence that any licensee took a license for a reason unrelated
to nonobviousness. (See A30-31.)
The Board also erred in dismissing Rambuss evidence of commercial
success as not being commensurate in scope with the broad memory device
claimed here. (A32.) This Court has rejected the Boards narrow view and held
that [c]ommercial success evidence should be considered so long as what was
sold was within the scope of the claims, regardless of the breadth of the claims.
In re Glatt Air Techniques, Inc., 630 F.3d 1026, 1030 (Fed. Cir. 2011) (quoting
In re DBC, 545 F.3d 1373, 1384 (Fed. Cir. 2008)) (rejecting same reasoning by
Board); see also Alcon Research, Ltd. v. Apotex Inc., 687 F.3d 1362, 1371
(Fed. Cir. 2012). Accordingly, the Board applied an incorrect legal standard in
assessing Rambuss evidence of commercial success.
The Board also erred in finding that the objective evidence of
nonobviousness related solely to prior-art features. (A31.) The Board is incorrect
that the claimed features were all known in the art for the reasons discussed above.
But even if the claimed features had been known individually, the Boards view
ignores the claimed invention as a whole, which is a method of operation in a
synchronous memory device having numerous recited features. Ignoring the
invention as a whole was legally incorrect, as this Court has explained that the
proper approach is to parse the evidence that relates only to the prior art
50

functionality and the evidence that touted Rambuss patented design as a whole.
Rambus, No. 2012-1634, slip op. at 15-16. The Board did not conduct this
analysis. (See A29-34.)
Although the court in Rambus Inc. v. Rea vacated and remanded in part so
the Board could assess obviousness under the correct standard, a reversal is
appropriate here. No party below offered any expert testimony refuting Rambuss
expert testimony and other evidence of nonobviousness. Accordingly, the record
does not support any conclusion other than nonobviousness. That fact is unlikely
to change if the Court were to remand, as Samsung has elected not to participate
further and Micron lacks standing to participate regarding these issues, as
discussed below. Accordingly, the errors in the Boards analysis warrant reversal.
D. Micron Lacks Standing to Argue Issues Not Raised in Its
Own Reexamination Request
5

Under 37 C.F.R. 1.989, the PTO may choose to merge two or more
pending reexaminations relating to the same patent into a consolidated proceeding.
The sole statutory authority for this rule is 35 U.S.C. 2(b)(2), which generally

5
Micron is participating in a number of other appeals before this Court that
present similar standing issues. Rambus moved to dismiss Micron as an improper
party in some of those cases, but the Court ruled that the parties should address the
standing issues in their merits briefs. See, e.g., Appeal No. 13-1224, Dkt. 28 at 2.
For this reason, Rambus presents its standing arguments in this brief as opposed to
moving to dismiss Micron.
51

gives the PTO the authority to establish regulations not inconsistent with law
that govern the conduct of proceedings in the PTO. Nothing in 35 U.S.C.
2(b)(2), however, permits the PTO to promulgate a regulation that confers
statutory rights upon a party that it would not otherwise have had. Indeed, this
Court has repeatedly held that the PTO does not have this type of substantive
rulemaking authority. See Koninklijke Philips Elecs. N.V. v. Cardiac Sci.
Operating Co., 590 F.3d 1326, 1336 (Fed. Cir. 2010) (The PTO lacks substantive
rulemaking authority.); see also Merck & Co. v. Kessler, 80 F.3d 1543, 1549-50
(Fed. Cir. 1996). Accordingly, the PTO has referred to merger merely as a
procedural housekeeping issue. (A3584.)
Nonetheless, the PTO has interpreted its merger regulation as permitting the
parties to merged reexaminations to participate in each others reexaminations,
including in appeals. The statutory right of a third-party requester of an inter
partes reexamination to appeal to the Board is established by 35 U.S.C. 315,
which states in relevant part:
(b) Third-Party Requester. A third-party requester
[of an inter partes reexamination]

(1) may appeal under the provisions of section 134
[to the Board], and may appeal under the provisions of
sections 141 through 144 [to the CAFC], with respect to
any final decision favorable to the patentability of any
original or proposed amended or new claim of the patent;
and

52

(2) may, subject to subsection (c), be a party to any
appeal taken by the patent owner under the provisions of
section 134 [to the Board] or sections 141 through 144
[to the CAFC].

35 U.S.C. 315(b) (2002).
6
That section does not contemplate, suggest, or
otherwise encompass the concept of merged reexamination proceedings, as merger
is a creature of PTO regulation, not statute. Thus, when 315 states that a
requester may argue on appeal any final decision in subsection (b)(1) and any
appeal taken by the patent owner in subsection (b)(2), it is referring to any final
decision or appeal in the particular reexamination that the third party actually
requested.
Only this view of 315(b) is consistent with the rest of the statutory
framework governing inter partes reexaminations. For example, after the PTO has
issued an order for inter partes reexamination of a patent in response to a request
by a third party, 35 U.S.C. 317(a) prohibits the same third-party requester or its
privies from filing subsequent requests for inter partes reexamination of the same
patent until the PTO has issued a reexamination certificate in the pending
reexamination proceeding. See 35 U.S.C. 317(a). The purpose of 317(a) is to
prohibit a third-party requester from requesting and participating in more than one

6
Because the inter partes reexaminations at issue in this motion were
instituted before the America Invents Act (AIA), the statutes and rules in
existence before the AIA was implemented should govern this issue.
53

inter partes reexamination of a patent at a time. Yet, the PTO has interpreted its
merger rules to give Micron the right to participate in a second concurrent inter
partes reexamination.
Without the merger, Samsungs and Microns two reexamination
proceedings would have continued separately. In the Micron-requested
proceeding, the examiner would have ultimately rejected all of Microns invalidity
arguments. (A1082-83.) At that point, the only issues Micron would have had
standing to argue to the Board and to this Court would have been the examiners
nonadoption of its own proposed rejections. See 35 U.S.C. 315(b)(1).
Meanwhile, in the Samsung-requested proceeding, the examiner would have
ultimately rejected claims 1-28 and confirmed claims 29-35. (A1045.) At that
point, Rambus would have appealed to the Board (as it did), and only Samsung
would have had a right to participate in the appeal.
Absent merger, it is beyond dispute that Micron would not have had any
statutory right to participate in the Samsung-requested reexamination. There is no
legitimate reading of 35 U.S.C. 315 and 317 that would have permitted Micron
to suddenly jump into Samsungs reexamination proceeding and argue issues to the
Board that Micron had never raised. By interpreting its merger rule to give Micron
appeal rights beyond those provided by statute, the PTO has acted contrary to
statute and outside the scope of its authority. Consequently, the Board erred in
54

granting Micron standing to argue issues it never raised in its reexamination
request, including the combinations of iAPX, Lofgren, and Inagaki at issue in this
appeal.
VI. CONCLUSION
For the foregoing reasons, this Court should properly construe the claims,
reverse the Boards decision finding claims 21-23 of the 863 patent obvious over
iAPX in combination with Lofgren and/or Inagaki, and rule that Micron lacked
standing to participate in the appeals before the Board and to this Court.

Dated: October 11, 2013 Respectfully submitted,

/s/ J ason E. Stach
J . Michael J akes
J ason E. Stach
Aidan C. Skoyles
(202) 408-4000

Attorneys for Appellant Rambus Inc.

ADDENDUM
APPLICATION NO. FILJNGDATE FIRST NAMED INVENTOR
951000,250 06/28/2007 6452863
22852 7590 1012312012
FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER
LLP
901 NEW YORK A VENUE, NW
WASHJNGTON, DC 20001-4413
UNJTED STATES DEPARTMENT OF CO!\IJ\'1ERCE
United States Patent and Tradcn1ark Office
AJJrcso: COMMJSSJONER FOR PATENTS
P.O. Box 1450
Aleoandria, Virginia 223 IJ-1450
www.uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
38512.8 4189
EXAMINER
ESCALANTE, OVIDIO
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
10/23/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
(Rev. 04/07)
Case: 13-1426 Document: 1-3 Page: 17 Filed: 05/29/2013
A1
UNITED STATES PATENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
95/001,124 ll/24/2008 6452863
22852 7590 10/2312012
LLP
901 NEW YORK A VENUE, NW
WASHINGTON, DC 20001-4413
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
ATTORNEY DOCKET NO. CONFIRMATJON NO.
896.002.863 5356
EXAMINER
ESCAI.ANTE, OVIDIO
ARTUNlT PAPER NUMBER
3992
:MAIL DATE DELIVERY MODE
10/23/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
PTOL-90A (Rev. 04/07)
A2
BEFORE THE PATENT TRIAL AND APPEAL BOARD
RAMBUSINC.
Patent Owner, Appellant and Respondent
v.
MICRON TECHNOLOGY, INC.
Requester, Respondent and Cross-Appellant
and
SAMSUNG ELECTRONICS; INC.
Requester
Appeal2012-001917
Inter Partes Reexamination Control No. 95/000,250 & 95/001,124
United States Patent 6,452,863 B2
Teclmology Center 3900
Before HOWARD B. BLANKENSHIP, KARL D. EASTHOM, and
STEPHEN C. SIU, Administrative Patent Judges.
EASTHOM, Administrative Patent Judge.
DECISION ON APPEAL
A3
Appeal 2012-001917
Reexamination Control Nos. 95/000,250 & 95/001,124
Patent 6,425,863 B2
This merged proceeding arose out of separate requests by Micron
(95/001,124) and Samsung Electronics Ltd. (95/000,250) for inter partes
reexaminations of U.S. patent 6,425,863 B2 to Farmwald et al., Method of
Operating A Memory Device Having A Variable Data Input Length (issued
Sept. 27, 2002 and claiming priority to Apr. 18, 1990 per application no.
07/510,898) assigned to Rambus.
Samsung has not filed a Brief in this proceeding. Appellant, Patent
Owner Rambus, appeals in its (Replacement) Appeal Brief(Mar. 4, 2011)
from the Examiner's decision to reject claims 1-28. (Rambus App. Br. ix.)
Cross-Appellant, Requestor Micron, appeals from the Examiner's decision
in the (Second) Right of Appeal Notice (Sept. 3, 201 O)("RAN") not to reject
claims 14-16 on certain grounds proposed by Micron and on other grounds
proposed by requester Samsung. (Micron Cr. App. Br. 3-4.) The Examiner's
Answer relies on the RAN, incorporating it by reference.
We have jurisdiction under 35 U.S.C 6, 134, and 315.
We AFFIRM the Examiner's decision to reject claims 1-28 and do not
reach Micron's Cross Appeal Brief in furtherance of the special dispatch
mandate for inter partes reexamination proceedings under 35 U.S.C 303.
Cf In re Gleave, 560 F.3d 1331, 1338 (Fed. Cir. 2009) (not reaching
obviousness after finding anticipation).
STATEMENT OF THE CASE
Ram bus and Micron refer to several related judicial and other
proceedings including inter partes and ex parte reexaminations,
International Trade Commission proceedings, and Federal District Court and
Circuit Court proceedings in their briefs and inter partes requests. An oral
2
A4
Appeal2012-001917
Patent 6,425,863 B2
hearing of this appeal transpired on July 11,2012 and was subsequently
transcribed.
Appellant Rarnbus appeals the Examiner's decision to reject the
claims as follows:
Claims 1-20 and 24-28 under 35 U.S.C. 102(b) as anticipated based
on the iAPX Manual
1
or Budde
2
(see RAN 51, 73);
Claim 21 under 35 U.S.C. 103(a) as obvious based on the iAPX
Manual or Budde, and Lofgren
3
(see RAN 94, 111 );
Claim 22 under 35 U.S.C. 103(a) as obvious based on the iAPX
Manual or Budde, and Inagaki
4
(see RAN 98, 113); and
Claim 23 under 35 U.S. C. 103(a) as obvious based on the iAPX
Manual or Budde, Inagaki, ahd Lofgren (see RAN 103, 114).
Claims 1, 14, 21, 22, and 23 of the '863 patent follow:
1. A method of controlling a memory device by a memory controller,
wherein the memory device includes a plurality of memory cells, the method
of controlling the memory device comprises:
providing first block size information to the memory device, wherein
the memory device is capable of processing the first block size information,
wherein the first block size information is provided by the memory
controller and is representative of a first amount of data to be input
by the memory device; and
1
iAPX Interconnect Architecture Reference Manual (Intel Corp.) (1982)
2
Budde eta!., U.S. 4,480,307 (Oct. 30, 1984).
3
Lofgren eta!., G.B. 2,197,553 A (May 18, 1988).
4
Inagak.i, JP 57-210495 (Dec. 24, 1982) (reference hereinafter is to an
English language translation of record).
3
A5
Appeal 2012-001917
Patent 6,425,863 B2
issuing a first operation code to the memory device, wherein in
response to the first operation code, the memory device inputs the first
amount of data.
14. A method of operation in a synchronous memory device, wherein the
memory device includes a plurality of memory cells, the method of
operation of the memory device comprises:
receiving first block size information from a memory controller,
wherein the memory device is capable of processing the first block size
information, wherein the first block size information represents a first
amount of data to be input by the memory device in response to an operation
code;
receiving the operation code, from the memory controller,
synchronously with respect to an external clock signal; and
inputting the first amount of data in response to the operation code.
21. The method of claim 14 further including generating an internal clock
signal, using a delay locked loop and the external clock signal wherein the
first amount of data is input synchronously with respect to the internal clock
signal.
22. The method of claim 14 further including generating first and second
internal clock signals using clock generation circuitry and the external clock
signal, wherein the first amount of data is input synchronously with respect
to the first and second internal clock signals.
23. The method of claim 22 wherein the first and second internal clock
signals are generated by a delay lock loop.
4
A6
Appeal2012-001917
Reexamination Control Nos. 951000,250 & 95/001,124
Patent 6,425,863 B2
ANALYSIS
I. Anticipation- iAPX Manual
Rambus does not present separate patentability arguments for claims
1-20 and 24-28 rejected as anticipated by the iAPX Manual. Ram bus argues
that "a 'memory device' is a chip and does not encompass a memory module
including a memory controller and a collection of memory devices."
(Rambus App. Br. 8.) While Rambus provides separate section headings for
claims 10 and "14-20 and 24-28" (Rambus App. Br. 14), Rambus's
arguments there also reduce to the single chip argument alluded to in the
previous sentence. As such, claim 1 is selected to represent claims 1-20 and
24-28.
The Federal Circuit recently decided against Rambus regarding the
same issue involving a similar claim- claim 18 discussed further below. In
re Rambus Inc., App. No. 2011-1247 (Fed. Cir. Aug. 17, 2012) (holding that
the claimed memory device is not limited to a single chip so that the iAPX
Manual anticipates the sole claim at issue there). As Micron points out, with
respect to the claims rejected as anticipated, each ofRambus's arguments
essentially reduce to the single chip argument (see Micron Resp. Br. 4, 13-
14) dismissed by In re Rambus as incorrect.
Ram bus also argues here, in an oblique fashion, that the bus interface
unit (BIU) of the iAPX Manual is not a memory controller. Rambus points
out that the iAPX Manual "states that 'the BIU performs as an intelligent
switch [and the] MCU acts as an intelligent memory controller."' (Ram bus
App. Br. 13 (quoting iAPX 1-1).) Rambus also argues that "neither the bus
interface units nor the memory control units provide the alleged block size
5
A7
Appeal 2012-001917
Patent 6,425,863 B2
information or operation codes to the memory devices in the storage array."
(App. Br. 13 (emphasis added).) This argument reduces to the incorrect
assertion that the iAPX MCU (memory control unit) is not part ofthe iAPX
memory module which reads on the claimed memory device- as In re
Rambus held.
As In re Rambus also decided, the iAPX BIU reads on the "bus
controller" recited in claim 18 at issue there, which follows:
18. A method of operation of a synchronous memory device, wherein the
memory device includes a plurality of memory cells, the method of
operation ofthe memory device comprises:
receiving an external clock signal;
receiving first block size information from a bus controller, wherein
the first block size information defines a first amount of data to be output by
the memory device onto a bus in response to a read request;
receiving a first read request from the bus controller; and
outputting the first amount of data corresponding to the first block
size information, in response to the first read request, onto the bus
synchronously with respect to the external clock signal.
5
(Farmwald eta!., U.S. 6,034,918 (Mar. 7, 2000) claim 18 (emphasis added).)
Comparing claim 18 in In re Rambus and claim I here reveals that
claim 18 recites a "receiving first block size information from a bus
controller" while claim I recites "receiving first block size information from
a memory controller." (Emphasis added.) Claims I and 18 respectively
require write and read operations, but little distinction exists in terms of the
claimed functions recited in the two controllers; they both send block size
information. (Claim 18 also requires receiving a read request from the bus
5
This claim is also discussed in Ram bus Inc. v. Infineon Technologies AG,
318 F.3d 1081, 1091-1092 (Fed. Cir. 2003).
6
A8
Appeal 2012-001917
Patent 6,425,863 B2
controller, but claim 1 does not specifY whence the read operation code
emanates, while claim 14 requires it to emanate from the memory
controller.)
The Examiner notes that Rambus had not made any specific
arguments about why the iAPX BIU could not constitute the claimed
memory controller since it satisfies the claimed function of (implicitly)
sending or transferring block size information. (See RAN 71.)
6
Rambus
does not direct attention to any difference between the "memory controller"
recited in claim 1 or the "bus controller" determined by In re Rambus to read
on the BIU in the iAPX Manual. As In re Rambus reasons,
it is the bus controller (i.e., the 'BIU') of the iAPX that is akin
to the BIU that Rambus distinguished during prosecution ....
There is no suggestion that the BIU oithe iAPX is within the
memory module, rather it is clearly outside of the memory
module, thus satisfying the requirement that the memory
module receive a request from a bus controller.
See In re Rambus, slip op. at 16 (emphasis added).
7
6
It appears that Ram bus, for the first time and on appeal (i.e., after the
Examiner's RAN), references the BIU as an "intelligent switch," but
Ram bus does not explain in a clear fashion why such an "intelligent switch"
does not satisfY the memory controller recited in the claims. (See Ram bus
App.Br. 13.) Instead, as indicated, Rambus devotes the bulk of its briefto
various permeations of the single chip argument. For example, after
referring to the BIU as an "intelligent switch," Ram bus argues that the MCU
is an "intelligent memory controller" and as such, cannot form part a
memory device, i.e., according to Rambus, only a single chip (e.g., a single
chip in the iAPX storage array) constitutes a memory device. (See, e.g.,
Rambus App. Br. 13.) In re Rambus rejected that single chip argument as
noted.
7
See also Rambus Inc. v. Infineon Technologies AG, 318 F.3d 1081, 1084-
1086, 1091-1092 (Fed. Cir. 2003)(also addressing, inter alia, claim 18 in the
7
A9
Appeal2012-001917
Patent 6,425,863 B2
The Board reasoned similarly in the underlying decision that Ram bus
appealed in In re Rambus:
In other words, unlike the BIU and array in Jackson, but like
the memory device in the '918 patent, the iAPX memory
module is confined to its own area, and receives commands
from an external processor (i.e., the BIU ... ).
See BP AI 2010-011178 decision at 28 (emphasis added).
Rambus's statement that the iAPX does not disclose sending block
size information in an operation code to a memory device similarly focuses
on the incorrect single chip argument- i.e., it is premised on the incorrect
assumption that the iAPX Manual's memory module is not a memory
device. (See App. Br. 13-14f
Rambus's contention that the BIU is an "intelligent switch" also
overlooks the fact that the BIU is part of the master processor module in the
iAPX system which singly or together function as the memory controller
recited in the claims: "Each processor and its associated BIUs form a
module." (iAPX 1-3; Fig. 1-2.) "The master processor and its associated
Bills generate memory bus requests." (iAPX 1-8.) "The BIU is also
responsible for arbitrating the usage of the memory bus." (iAPX 1-3.) The
'918 patent, and finding that the written descriptions of each of four related
Rambus patents, 5,954,804; 5,953,263; 6,034,918; and 6,032,214, are
substantially identical to the written description of the 07/510,898
application to which they, and the '863 patent here, all claim continuity).
8
For example. Rambus argues that "the alleged operation code is not
provided to or received by the [single chip] DRAMs, as they only receive
conventional [operations]." (App. Br. 14.) Rambus continues the argument
as follows: "Thus under the correct construction of "memory device," it is
undisputed that iAPX does not disclose providing 'block size information'
or 'issuing an operation code' to a [single chip] memory device, as recited in
claim 1." (App. Br. 14.)
8
A10
Appeal2012-001917
Reexamination Control Nos. 95/000,250 & 95/00 I, I 24
Patent 6,425,863 B2
BIU also checks for error by using parity checking and stops memory
requests if errors occur. (See iAPX 1-7, 1-8.) For example, "[n]o
information (control, address, or data) can leave a GDP confinement area
without first being checked for correctness by one of the BIUs in the
module." (iAPX 1-7.) The BIU also "accepts the access request from an
iAPX 432 processor and, based on the physical address, it decides which
memory control bus(es) will be used to control the access." (iAPX 1-3.)
Micron points to this master processor module as satisfying the
memory controller limitation in the claims: "[T]he processor module of
iAPX (which includes the BIU and a processor) (see iAPX at 1-3) comprises
a memory controller in the context of the '863 patent." (Micron Resp. Br.
14.) The Examiner similarly finds that "[t]he BIU accepts the access
requests from an iAPX processor and, based on the physical address, it
describes which memory buses will be used." (See 95/000,250 Office
Action 18 (July 3, 2008).) The Examiner, like Micron, also refers to "other
controllers external to[] the memory module and those controllers is [sic:
are] equivalent to the claimed memory controller since those controllers
such as the BIU control the memory by issuing requests and control signals
to the memory device (e.g., block size and read/write requests are sent)."
(RAN 71 (emphasis added).)
The record supports the Examiner's finding and Micron's contention
that the iAPX processor module, which includes the BIU and a processor
(see iAPX 1-3), performs memory control functions, and the BIU and the
processor singly or together perform several memory control functions
identified by Ram bus. For example, Ram bus argued to the Federal Circuit
in In re Rambus that"[ a] person of ordinary skill would understand a
9
A11
i\ppeal2012-00!917
Patent 6,425,863 B2
memory controller to perform functions such as 'fault tolerance, error
checking, bus arbitration, and address queuing."' (Rambus's In re Rambus
Appeal Brief at 25.) Rambus makes a similar argument here about memory
controllers: "The memory control unit also performs functions that are
associated with controllers, not memory devices, such as fault tolerance,
error checking, bus arbitration, and request queing." (Rambus 1\pp. Br. 12.)
1\s discussed supra, the ii\PX BIU performs error checking,
arbitration, and at least some manner of "address queuing," since the BIU
selects an address to which to send requests. Rambus has not directed the
Board in this proceeding to limitations in the '863 patent defining or limiting
the claimed "memory controller" here and distinguishing it from the claimed
"bus controller" involved in the '918 patent and in In re Rambus (the patents
date back to a common application; 07/510,898 -see supra note 7).
Presumably, a bus controller and a memory controller, defined (if at all) by
the common '898 application, refer to the same device.
Rambus does not specifically rely on the '863 patent specification fot
any distinction between a bus and memory controller, and presents the
Board with the following unsupported definition of a memory controller:
"Consistent with the understanding of one of ordinary skill in the art,
Rambus has construed a 'memory controller' to be 'an integrated circuit
device that includes circuitry to direct the actions of one or more memory
devices."' (Rambus 1\pp. Br. 13.)
9
Since, based on the foregoing
9
Rambus's proposed definition to the Federal Circuit in In re Rambus
(quoted supra) does not include the "integrated circuit device" limitation.
1\ccording to Infineon, 318 F .3d at 1090, an "integrated circuit device" is
limited to a single chip (based on its ordinary and customary meaning
10
A12
Appeal 2012-001917
Patent 6,425,863 132
discussion, the iAPX BIU "directs actions" of one or more memory modules
in the iAPX system (and In re Ram bus held that such a memory module
constitutes a memory device), the iAPX BIU satisfies the claimed memory
controller under at least one ofRambus's proposed definitions (assuming
arguendo that Ram bus's proffered definition limits or defines the term).
Bus access requests at least pass through the BIU from its associated
processor in the module. Claim I recites "wherein the first block size
information is provided by the memory controller" while claim 14 recites
"receiving first block size information from a memory controller." Neither
claim specifically requires the memory controller to issue the block size
information. But even if they do so implicitly, the BIU and its associated
:; processor are all part of the same; processor module, and assuming for the
sake of argument that the BIU does not satisfY the claimed memory
controller, as Micron and the Examiner point out, the iAPX processor
module which includes the BIU does control memory functions as discussed
supra. (See also iAPX Figure 1-2; Micron Resp. Br. 14.)
Rambus responds to Micron in its Rebuttal Brief by simply providing
generic denials, but Ram bus fails to provide any significant argument
distinguishing the iAPX memory processor module or its associated BIU
from the claimed memory controller. (See Rambus Reb. Br. 6.) Rambus
attempts to incorrectly shift the burden to Micron to show error and define
Rambus's claimed invention.
according to a trade dictionary). But under the recent logic and holding in In
re Rambus, absent a more specific claim recitation, since the claimed
"memory device" is not limited to a single chip, neither is the claimed
"memory controller."
11
A13
Appeal2012-001917
Patent 6,425,863 B2
Under In re Rambus and the arguments presented, Rambus has
presented no principled reason to the Board for distinguishing the claims
here from the holding under In re Ram bus. Based on the foregoing
discussion, the iAPX Manual anticipates claims 1-20 and 24-28. As such, it
is unnecessary to reach the cumulative rejection involving Budde. Cf In re
Gleave, 560 F.3d 1331, 1338 (Fed. Cir. 2009) (not reaching obviousness
after finding anticipation).
Claim 21- iAPX and Lofgren
Micron's analysis and responses to Rambus's arguments persuasively
show that the Examiner did not err in the rejection of claim 21 which
depends from claim 14. (See Micron Resp. Br. 15-19:) Micron's analysis:::
and responses and the Examiner's findings,(RAN 94c98) are adopted and
incorporated herein by reference.
Rambus argues that the Examiner equates a delay lock look (DLL)
with a PLL (phase lock loop) but also finds that they are different, and that
somehow, these findings show that "the Examiner does not show that
Logfren discloses a delay lock loop" or meets the Examiner's definition of a
delay lock loop. (Rambus App. Br. 17.) This argument does not distinguish
the delay circuit of Lofgren. As discussed in a related appeal, BP AI 2011-
008431, Rambus's experts have stated that a DLL and PLL can be used for
the same or similar purposes. In light of the '863 patent, including its Figure
12, and past statements by Rambus, Lofgren discloses or at least suggests a
12
A14
Appeal2012-001917
Patent 6,425,863 B2
delay locked loop as required by claim 21.
10
Micron also points out that
Rambus referred to Figure 12 in its related patents to show support for a
DLL and a PLL and provides persuasive rationale as to why, in light of the
'863 patent, Lofgren teaches a DLL as set forth in claim 21. (See Micron
Resp. Br. 16.)
As Micron also points out, Lofgren also discloses creating precise
internal integrated circuit delays which are delayed by one clock cycle
relative to a previous clock cycle. (Resp. Br. 15-16.) The Examiner makes
similar findings, reasoning that iAPX requires precise delays to output data
and that Lofgren's system supplies such delays. (See RAN 97.) Micron
points out that the iAPX memory device MCU outputs and inputs different
data and/or signals at different bus interfaces, including the MACD bus ''
based on an external clock, thereby suggesting areason for using precise
delays relative to the external clock. As Micron reasons, it would have been
obvious to employ Lofgren's DLL to ensure precise clocking for the various
data inputs and outputs at different interfaces in the iAPX memory module,
where Lofgren teaches precise delays in integrated circuits of an integer
number of clock cycles. (See Micron Resp. Br. 16-18.)
10
The examiner also found in that related case that combining Lofgren and
the iAPX system would have been obvious with Lofgren essentially teaching
an accurate timer using a delay line. The Board noted that Ram bus
essentially equated and/or advanced substantial similarities between PLLs
and DLLs, and agreed with the examiner that combining Lofgren with the
iAPX Manual would have been obvious. See BPAI 2011-008431 at 30-32.
The prior '8431 Board decision and reasoning related to Lofgren is adopted
and incorporated herein by reference.
13
A15
Appeal2012-00!917
Patent 6,425,863 B2
Ram bus argues in rebuttal that skilled artisans "would have
understood that the delay lines of Lofgren are used to achieve time
separation between the external signals used to control the DRAMs."
(Ram bus Reb. Br. 9.) Rambus also asserts that Lofgren is directed to
external control of memory devices, and that even if "the alleged DLL of
Lofgren were placed on the memory control unit of the iAPX system and
used to generate control signals applied to the asynchronous DRAMs, it
would still be unrelated to the alleged 'memory device' receiving data over
the MACD bus." (Rambus Reb. Br. 9.)
This rebuttal argument is another form of the single chip argument
and does not account for the fact that the iAPX MCU and DRAMS
constitute the. memory device of the claims as In re Ram bus holds. In other
'words, Micron's and the Examiner's rationale is premised on the memory
device MCU inputting data from the MACD bus; i.e., inputting data from
the bus to the claimed memory device (which includes the MCU and its
DRAMs). (Accord iAPX at BIU-20; MCU-41.)
While Ram bus also argues that the iAPX system runs too slow to
obtain the benefits of a DLL (Rambus App. Br. 20), faster speeds would
have been available at the time of the invention as Micron argues. (See
Micron Resp. Br. 18; note 13 infra.) Also, Rambus agrees that Lofgren
performs precise delays and such delays are used to control various DRAM
signals and to account for voltage and temperature variations. (See Ram bus
App. Br. 18-19.) This supports the Examiner's and Micron's rationale that
the iAPX memory device could have benefitted from such precise delays
even with slower or faster speeds. (See Micron Resp. Br. 18.)
14
A16
Appeal 2012-001917
Patent 6,425,863 B2
Rambus's argument that Lofgren teaches external clock signal control
is not clear. (See Rambus App. Br. 19.) Claim 21 does not specifically
relate the recited term "internal" to the claimed memory device. As such,
any "internal" signal could be satisfied by implementing a DLL internal to
another chip. But even if "internal" refers to a memory device, Micron
persuasively shows that the iAPX memory device receives external clock
signals and reasons that using such a reference as an external reference to
generate internal delay signals within the memory device would have been
obvious in order to generate precise timing signals in the iAPX memory
device, thereby overcoming sensitivity to voltage and temperature changes
in integrated circuits as Lofgren suggests. (See Micron Resp. Br. 17-18.)
Based on the foregoing discussion, Rambus fails to show error in the
rejection of claim 21 based on iAPX and Lofgren. As such, the Budde based
rejection is not reached. Cf In re Gleave, 560 F.3d 1331, 1338 (Fed. Cir.
2009) (not reaching obviousness after finding anticipation).
Claim 22 - iAPX and Inagaki
Claim 22 depends from claim 14, and requires "generating first and
second internal clock signals using clock generation circuitry and the
external clock signal, wherein the first amount of data is input
synchronously with respect to the first and second internal clock signals."
. The Examiner finds and concludes that the combined teachings of iAPX and
Inagaki render the claimed feature obvious. (See RAN 99-103.)
15
A17
Appeal20!2-00!917
Patent 6,425,863 B2
lnagaki's Teachings
I 1. Inagaki discloses a method for increasing data rates in block
access memory. As background, Inagaki teaches that conventional methods
to increase data transfer rates in RAMs involved increasing the data bus
width, which adds cost of packaging and pin count, or to increase the clock
rate. (Inagaki 2.) Inagaki's solution is to use dual edges of a clock as
quoted as follows.
12. "The rise and fall of external clock q> are detected, and clocks cp
1
and cp
2
are generated. Clocks cp
1
and cp
2
drive shift pulses of the shift
register .... In this way, since one bit is output on each half-cycle, the
operating speed is twice that ofthe conventional speed." (I d. at 4.)
13 "[T]he present invention presents block access memory that
transfers data with a speed that is twice the conventional speed, by
performing 1/0 [input/output] of da:ta on every half-cycle of the external
clock that drives the 1/0 shift register." (Id. at 3.)
14. Inagaki refers to "an internal timing generator circuit that controls
the memory cells, read circuit, row and column decoders, data input buffer,
I/0 shift register, and data output buffer, wherein; the 1/0 shift register
performs data input or output every half-cycle based on an external clock."
(Id. at 3.)
15. IJ?-agaki also specifically refers to synchronous operation: "Clock
cp
1
is generated synchronously with the external clock q>." (Id. at 5.)
Discussion
Rarnbus maintains that using Inagaki's clocking scheme in the iAPX
system would not have been obvious because lnagaki uses shift registers and
a non-periodic pulse, as opposed to a clock, and the iAPX system uses dual
16
A18
Appeal 2012-001917
Patent 6,425,863 B2
edges of two clocks for other specific functions. (See App. Br. 21-26.)
Rambus's arguments reduce to the unpersuasive assertion that the two
systems must be bodily incorporated. See In re Sneed, 710 F.2d 1544, 1550
(Fed. Cir. 1983) ("[I)t is not necessary that the inventions of the references
be physically combinable to render obvious the invention under review."); In
re Nievelt, 482 F.2d 965, 968 (CCPA 1973) ("Combining the teachings of
references does not involve an ability to combine their specific structures").
And Inagaki refers to an "external clock" repeatedly and the clock is
periodic at least while it operates (I2-I4): "The rise and fall of external clock
<pare detected, and clocks <p
1
and <p
2
are generated ..... In this way, since
one bit is output on each half-cycle, the operating speed is twice that of the
conventional speed." (Inagaki at 4.) Inagaki's system performs "data input
or output every half-cycle based on an external clock." (I d. at 2; accord I2c
14).) Inagaki's numerous external clock references point skilled artisans to
and embrace the well-known computer clock- in other words, the same type
of external computer clock generically claimed in the '863 patent.
11
See In
re Paulson, 30 F.3d 1475, 1480-81 (Fed. Cir. 1994) ("a prior art reference
must be 'considered together with the knowledge of one of ordinary skill in
the pertinent art'," and where the skill level was "'quite advanced' ... 'one
11
clock ... A source of accurately timed pulses, used for synchronization in
a digital computer .... " McGraw-Hill Dictionary of Scientific and
Technical Terms 387 (Fifth Ed. 1994). This reference indicates that clock
signals and clock pulses are the same: i.e., "clock signals. See Clock
pulses." I d. "[C)lock pulses .... Electronic pulses which are emitted
periodically, usually by a crystal device, to synchronize the operation of
circuits in a computer. Also known as clock signals." I d.
17
A19
Appeal20J2-001917
Patent 6,425,863 B2
of ordinary skill certainly was capable of providing the circuitry necessary to
make the device operable for use as a computer'") (citations omitted).
Rambus's prosecution history argument (see Rambus App. Br. 22
(citing, without attaching to the Brief, a March 21, 2002 amendment at 7, n.2
in the prosecution of App. No. 09/969,489)) that Rambus distinguished the
type of clocks involved in Inagaki fails to address the combined teachings
involving the iAPX periodic clocks or the notion that skilled artisans, see
Paulsen, 30 F.3d at 1480-81, would have recognized that Inagaki teaches
periodic external and internal clocks based on the ordinary use of the term
and the Inagaki's synchronous clock operation. (See 15; note 11).
12
Micron relies on the combination, including the iAPX external clocks,
to suggest using the rising and falling edges of a clock. The iAPX system ,
employs dual edges oftwo different periodic clocks (i.e., CLKA, CLKB) as
Rambus acknowledges (App. Br. 24-25), and Inagaki teaches using dual
edges of a single clock in order to increase speed or reduce the number of
data paths in a memory device. (Il-13.) For example, Inagaki discloses
12
Rambus's prosecution history arguments are also not persuasive to
distinguish Inagaki 's clock for another reason. That is, while Ram bus did
argue, inter alia, that '"the external clock signal' [as claimed] is a periodic
signal used to orchestrate timing events (e.g., a read operation)," Rambus
did not specifically and clearly argue that the CAS and RAS input clock
signals in the prior art were not periodic ~ w h i l e Ram bus appears to have
made that argument with respect to another "asynchronous strobe signal."
(See 09/969,489 amendment at 7, n.2.) But even ifRambus did make that
argument in a clear fashion, Ram bus made numerous other arguments, and
the prior examiner did not rely on any such distinction and provides different
reasons for allowance, including "timing of the output drivers" or "precharge
information in the operation code." (See Notice of Allowance 2 in App. No.
09/969489.)
18
A20
Appeal20l2-001917
Patent 6,425,863 B2
"performing I/0 [input/output] of data on every half-cycle of the external
clock that drives the I/0 shift register." (B.) As the Examiner finds, in
Inagaki's system "[t]he two internal clocks allow for the input/output of data
to be received/output at twice the data rate as the external clock. (RAN
1 00.) "[I]f a technique has been used to improve one device, and a person
of ordinary skill would recognize that it would improve similar devices in
the same way, using the technique is obvious unless its application is beyond
his or her skill."' KSR!nt'l Co. v. Telejlex, Inc., 550U.S. 398,417
(2007)( citation omitted).
As the Examiner reasons, skilled artisans would have recognized that
Inagaki teaches that data bus systems, like that of iAPX, could have
benefitted by outputting data onto bus lines my using the rising and falling
edges of a clock to double the normal data transfer speed. (See Il-I3; RAN
99-1 02.) Ram bus alleges that Inagaki's shift registers render unobvious
using dual edge clocks in the iAPX system for data transfer to the MCU, but
the iAPX system already employs dual clock edges as Rambus also
acknowledges. (See Rambus App. Br. 25.) Therefore, contrary to Rambus's
assertions, skilled artisans would have understood how to implement the
known feature of using both clock edges on data to maximize speed whether
shift registers were employed or not. The fact that iAPX system uses both
rising and falling edges of the clock for other purposes means that skilled
artisans would have recognized that the iAPX system contains circuitry
available to send/receive data on both edges without a shift register. (See
RAN 100.)
Rambus's allegation that Inagaki's "combinatorial logic" limits speed
also lacks merit. (Rambus App. Br. 26.) Inagaki's system increases the
19
A21
Appeal 2012-001917
Patent 6,425,863 B2
speed over prior art systems and Rambus does not direct attention to where
Inagaki describes any such logic, let alone logic which slows down Inagaki's
system. (See Il-14.) If by "logic," Rambus refers to logic associated with a
shift register, such logic is not required to implement dual pulse edges as the
iAPX Manual teaches as discussed supra.
Rambus further argues that clocks <p
1
and <p
2
are aperiodic shift pulses
instead of internal clocks. (Rambus App. Br. 24.) To the contrary, Inagaki's
"clocks <p
1
and <p
2
drive shift pulses" and are generated by the rising and
falling edges of an external clock. (12.) They form part of the "internal
timing generator circuit that controls the memory cells, read circuit, row and
column decoders, data input buffer, I/0 shift register, and data output
buffer." (See 14.)
Rambus also argues that the iAPX system's buffer directional control
somehow precludes data transfers on both edges ofCLKB. (See App. Br.
25.) But claim 22 does not require two-way traffic implicit in the argument,
or even a buffer, so the argument is not commensurate in scope with the
claim. Alternatively, skilled artisans would have recognized that buffer
directional control could have been provided with other CLKA or CLKB
edges or even with other bused signals. Rambus has not demonstrated that
skilled artisans would have been unable to modifY the combined system to
increase the speed as Inagaki teaches.
Inagaki's teachings, and the iAPX use of dual edges, also evidence a
reasonable expectation of success in using dual clock edges on data for
increased speed. Increased speed and compactness by reducing bus width
and corresponding pin number while saving cost (see II) constitute universal
motivators. Dystar Textilfarben GmBH & Co. Dutschland KG v. C.H.
20
A22
Appeal2012-001917
Patent 6,425,863 B2
Patrick Co., 464 F.3d 1356, 1368 (Fed. Cir. 2006) ("[A]n implicit
motivation to combine exists ... when the 'improvement' is technology-
independent and the combination of references results in a product or
process that is more desirable, for example because it is stronger, cheaper,
cleaner, faster, lighter, smaller, more durable, or more efficient.") Such a
reasonable expectation of success outweighs Rambus's allegations about
changing the principle of operation or rendering the iAPX system inoperable
for its intended purpose. (See App. Br. 24-25.)
The Federal Circuit recently rejected a similar inoperability argument
by noting that any claimed "difference does not affect the operability of
Mouttet's [i.e., the applicant's] broadly claimed device-a programmable
arithmetic processor:" In re Mouttet, 686 F.3d 1322, 1332 (Fed. Cir. 2012)
(citations omitted) (also reasoning :that physical incorporation is not required
to support obviousness).
The principle of operation of Applicant's broadly claimed memory
device here involves synchronously outputting data using first and second
internal clock signals. The iAPX principle involves the ability to transfer
data to and from a memory module using clock signals, depending on the
data. Hence, using one or two external clocks does not undermine the broad
principle of transferring data. In other words, the iAPX principle of
transferring data "is not unique to its ... [dual clocking] operation." See
Mouttet, 686 F.3d at 1332. Also, the Court has recognized that "the
interaction of multiple components means that changing one component
often requires the others to be modified as well." KSR, 550 U.S. at 424.
Making other required modifications to increase the data speed by using
21
A23
Appeal2012-001917
Patent 6,425,863 B2
both clock edges, as Inagaki teaches (11-B), does not defeat obviousness or
show inoperability.
Ram bus fails to present evidence that skilled artisans would have been
unable to modifY interrelated parts. Moreover, the arguments are not
commensurate in scope with broad claim 22 which does not have significant
interrelated features other than those required to output data synchronously
using two clock edges of a clock signal. As such, given the claim breadth,
skilled artisans could have modified the iAPX system in view oflnagaki's
clocking scheme by dropping unneeded functions. For example, with one
(or a handful more) DRAM(s), which the claims do not preclude, and which
Inagaki suggests, arbitration schemes would not be required. Such a
modification would create a "cleaner" memory device for handling mere
one-way or two-way data transfers embraced by broad claim. Making a
device "cleaner" (i.e., simpler) constitutes a universal motivator under
Dystar.
Alternatively, the proposed combination does not require dropping
iAPX functions or a significant amount thereof. Skilled artisans would have
recognized that the iAPX system could have been modified to include the
external slower Inagaki clock as a trigger for the faster CLKA and/or CLKB.
That is, Inagaki (see Fig. 4) teaches that fast clocks can be created by using
the dual edges of a slower external clock: In Inagaki, a slower external
clock q> has rising and falling edges corresponding to and triggering faster
clocks q>
1
and q>
2
, suggesting a similar external clock to trigger signals such
as iAPX CLKA and CLKB signals or modified versions thereof. (See e.g.
Inagaki Fig. 4; I3, 14.) Inagaki and iAPX both employ multiple clock
signals, rendering such a combination obvious.
22
A24
Appeal 2012-001917
Patent 6,425,863 B2
The slower external clock's rising and falling edges would trigger the
existing CLKA and CLKB, with the external clock's rising and falling edges
corresponding to the existing rising edges of faster CLKB and/ or CLKA.
(See RAN 100 ("using the teaching of the generation of two internal clocks
from an external clock as disclosed by Inagaki").) The iAPX Specification
heuristically illustrates this concept (which Inagaki teaches as noted) by
showing a slower "!NIT" clock trigger signal with falling and rising edges
corresponding to the faster CLKA rising edges. (See BIU-41.) The '863
patent similarly discloses using internal clock complements being created or
triggered by external bus clocks. (See Fig. 13, App. Br. 21 (describing the
'863 patent's 500 MHz clock as triggered by dual edges of a 250MHz
clock).) t'
Despite Rambus's related arguments about existing cjevice limitations
based on speed (see Rambus App. Br. 24-26), faster memory chips than
those disclosed in the iAPX system would have been available at the time of
the invention.
13
Ram bus's argument that skilled artisans would have. used a
13
For example, Rambus expert and inventor Dr. Farrnwald testified that 50
MHz computers were available in the late 1980s and that, while DRAM
speed increased at a slower rate than CPUs (which doubled in speed yearly),
solutions were available if expensive. (See Farmwald Trial Dep. 268, 269,
275-276 (attached as Rambus App. Br. Evidence Ex. E-5).) Another article
of record, published in 1989, shows that an IEEE working group would
establish single DRAMs at 500MHz (i.e., "500 hundred million transfers per
second") as a standard and that there was "no technical reason for this" lack
of speed/bandwidth. See Moussouris, Life Beyond RJSC: The Next 30 Years
in High-Performance Computing, Technologi.c Comp. Let. V. 5, No.5, p. 2
(July 31, 1989) (attached, inter alia, as Exhibit A (which refers to the article
as Exhibit E to Samsung's Comments) to Micron's Third Party Requestor
Comments (filed July 22, 2009).) A patent to Bennett, filed in 1986 and also
23
A25
Appeal2012-001917
Patent 6,425,863 B2
faster clock show that speed would have been desired to accommodate chip
speed advances (see App. Br. 24) with Inagaki's solution an alternative to a
faster clock. Both iAPX clocks could have been rendered faster as device
speed increased prior to the claimed invention in 1990.
And even if the iAPX components could not have handled faster
speeds, the iAPX system could have benefitted, at the time of the invention,
from a slower external clock's dual pulse speed doubling function as a mere
substitute or trigger for the existing clock timing, as Inagaki suggests (see
II-B). The broad claims recited here do not require any set speed.
Rambus also raises an untimely new argument in its Rebuttal Brief
improperly buttressed by new evidence and thereby waives the argument.
Ram bus alleges that the iAPX,system requires holding Bill data on the
MACD bus over successive rising edges ofCLKB, thereby precluding data
transfers on the falling edge between the two rising edges. (See Rambus
Reb. Br. 12-13 (newly citing BIU-43 as evidence).)
14
But even ifRambus's
characterizations are correct and timely, such data holding does not impact
the substitution and modification rationales described supra. For example,
having rising and falling edges of an external clock trigger the rising CLKB
of record (see Micron's Cr. App. Br. 3), refers to a 25 MHz preferred
embodiment, but expected 20ns (50MHz) speed. (See U.S. 4,734,909, col. 9,
11. 58-60; col. 13, II. 50-54.)
14
Ram bus supports the argument by discussing inherent hold and delay
times in the iAPX system. Rambus does not persuasively demonstrate that
those delays necessarily impact the data length on the bus. See id. at 11-12.
See BTIJ-40, 41, 43) (describing various inherent time delays between clock
edges and signals based on capacitance, etc.) Similar delays would occur in
the '863 patent system, but any such delays are not addressed in depth, if at
all.
24
A26
Appeal 2012-001917
Patent 6,425,863 B2
edges does not impact any timing relying on those rising CLKB edges,
regardless of the data hold length. Or, replacing the iAPX system's dual
clock system with Inagaki's simpler single clock system to handle simple
one-way (or two-way) data transfers, without arbitration and other unneeded
functions pursuant to the breadth of claim 22, would obviously involve using
dual clock edges based on whatever the signal length constraints dictate.
Inagaki's system provides the fastest speed relative to the dual clock edges
regardless of the data length, where speed is ultimately governed by the dual
edges of the clock or the bus width and the system constraints. (See Il-13.)
Further, setting aside the above-discussed rationales for a moment,
while Ram bus relies on an example to show that data is held over successive
CLKB edges (see Reb. Br. 12), this does not mean that the iAPX MACD
data cannot be modified to correspond to rising and falling clock edges.
Rambus's reliance on specific examples does not show that the iAPX system
requires the data to be held for the duration argued, or that the data could not
have been modified to be held for less than the time defined by the CLKA
pulse, or that the CLKA pulses could not be extended. As Rambus points
out, the iAPX Specification (at BIUc38) reveals that the BIU inputs and
outputs ACD15 ... 0 data (to and from a processor) on both the rising and
falling edges ofCLKB. (See Rambus App. Br. 25; BIU 20.) This ACD data
transfer further suggests the claimed combination since not all the iAPX data
had to be held for the duration that Rambus argues. The iAPX system
suggests, and Inagaki shows, that skilled artisans knew how to provide data
over the same bus using the falling and rising edges of a single clock.
In summary, the thrust ofRambus's arguments, directed as they are
toward arbitration, buffer control, two-way traffic control between the
25
A27
Appeal2012-001917
Patent 6,425,863 B2
master BIU and slave memory device MCU, and other unclaimed features
(see e.g., Rambus App. Br. 22-23), are not commensurate in scope with
claim 22, which does not require those features. Claim 22 broadly embraces
a method for controlling a memory device which samples one-way data
portions output from the memory device. Rambus has not demonstrated that
skilled artisans, motivated by Inagaki's teaching of using rising and falling
clock edges for increasing data transfer speed to a known DRAM memory
device on a single bus, would not have been able to arrive at the broadly
claimed invention. Inagaki's clocking scheme provides the fastest possible
signal transfer on a bus, regardless of any signal length delays advanced by
Ram bus, thereby providing the motivation for the modification.
Rambus's other arguments fail to demonstrate Examiner error. The
Examiner's findings and rationale and Micron's responses are more
. persuasive than Rambus's arguments. Based on the foregoing discussion,
Rambus failed to show error in the obviousness rejection of claim 22 based
on iAPX and Inagaki. See KSR, 550 U.S. 398, 416 (2007) ("The
combination of familiar elements according to known methods is likely to be
obvious when it does no more than yield predictable results."). Affirmance
of the iAPX based obviousness rejection renders it unnecessary to reach the
Budde based obviousness rejection. Cf In re Gleave, 560 F.3d 1331, 1338
(Fed. Cir. 2009) (not reaching obviousness after finding anticipation).
Claim 23 - iAPX, Inagaki, and Lofgren
Rambus maintains that it would not have been obvious to combine the
references in the manner suggested because Inagaki discloses pulses that
would be incompatible with a delay lock loop (DLL). (Rambus App. Br. 27;
26
A28
Appeal 2012-001917
Patent 6,425,863 B2
Rambus Reb. Br. 14.) But the combination teaches or suggests such a well-
known clock as discussed supra. Ram bus's similar argument that Inagaki's
clocks signals are not internal clock signals because they are pulses is also
not persuasive for the same reasons. (See Rambus App. Br. 27.)
Moreover, as indicated supra, Inagaki recites an "internal timing
generator circuit" that controls various circuits in the RAM memory chip
device. (See 14.) Inagaki also refers to clock signals generated
synchronously with respect to an external clock and generally refers to an
external clock as discussed supra. (See 12, 14, see also Inagaki at 4; Fig. 1 0;
I 1-I3.) As such, the combination of iAPX, Inagaki, and Lofgren suggests
internal clocks generated by an external clock. Since typical DLL internal
clocks drive various internal RAM circuits as Lofgren suggests and as
discussed above, this further suggests combining, the DLL ofLofgren for
precise timing and delay.
Rambus's remaining arguments primarily restate arguments presented
with respect to claims 21 and 22. Micron's. responses support the
Examiner's findings and conclusion of obviousness. (See RAN I 03-105.)
Affirmance of the iAPX based obviousness rejections renders it unnecessary
to reach the Budde based obviousness rejections. Cf In re Gleave, 560 F.3d
1331, 1338 (Fed. Cir. 2009) (not reaching obviousness after finding
anticipation).
Secondary Considerations
Rambus contends that substantial secondary evidence supports
unobviousness. But the evidence fails to establish a nexus because any
success likely flows from a variety of several unclaimed features touted here
27
A29
Appeal 2012-001917
Patent 6,425,863 B2
or in other Ram bus proceedings or patents. Such unclaimed, but disclosed
features, include eight data lines, small DRAM sizes with minimal bus
loading, multiplexed bus architecture and device interfaces, packetized
control, unique device identifiers, time access and arbitration schemes, a 500
MHz data rate, minimal clock skew system, a high speed cache method, a
narrow bus, and memory devices having all the functionality of prior art
circuit boards. (See '863 patent, col. 3, ll. 29-62; col. 4, II. 3-6, 37-52; col. 7,
11. 18-22; col. 9, II. 23-30; col. 12, II. 50-58; col. 14, 11. 48-50.) See also
Rambus Inc. v. Infineon Technologies AG, 318 F.3d 1081, 1095 (Fed. Cir.
2003) ('"The present invention is designed to provide a high speed,
multiplexed bus'" (quoting Rambus's related '918 patent, col. 5,11. 36-46),
but "the prosecution history shows that a multiplexing bus is only one of
h many inventions disclosed in the '898 application.") Ram bus agrees that
"the original disclosure describes many inventions." (Rambus Resp. Br. 22;
accord Murphy Dec!. ~ 30 (filed Jan. 18, 2011) ("the original disclosure
describes multiple objects of the invention").)
As Micron points out, Ram bus presents the same evidence it provided
"in every one of the 10 pending inter partes reexaminations." (Micron Reb.
Br. 21.) Different claims in the different proceedings have varying scope.
Rambus's evidence does not demonstrate that any success was due
solely to the claimed features, or to claimed features that were not already
known in the prior art. Ram bus's contentions about "significant sales" and
"that the Farmwald family, which includes the '863 patent, has numerous
licensees," (App. Br. 29) are vague statements which do not show any sales
or even allege that the '863 patent is licensed. Rambus does not provide a
copy of any licenses (even if one does pertain to the '863 patent) or provide
28
A30
Appeal 2012-001917
Patent 6,425,863 B2
evidence showing what claimed features any of the licenses involve. Also, it
is well known and settled law that competitors often take licenses for
commercial or other reasons having nothing to do with unobviousness.
As discussed in related reexamination cases, see BPAI 2012-001639
at 45-4 7 (adopted and incorporated herein by reference), single chip
synchronous memory devices were known, as were DRAMs, precharging
and DLL circuits, as the prior art discussed supra also discloses. Hence, the
record suggests that at least part of any commercial success would have been
due to features already in the prior art, such as the popular DRAM memory
chip.
15
Cf In re DEC, 545 F.3d 1373, 1384 (Fed. Cir. 2008) (Board's
conclusion of nonobviousness supported, the Board finding, inter alia, that
"evidence in the record suggested that the success ofXanGo juice may be
due-to other factors-for example, the increasing popularity of the
mangosteen fruit in general"). The Federal Circuit, further observed in
DEC that
... DBC has done little more than submit evidence of sales.
However substantial those sales, that evidence does not reveal
in any way that the driving force behind those sales was the
claimed combination ofmangosteen fruit, mangosteen rind
extract, and fruit or vegetable juice. Nor is there any evidence
that sales ofXanGo juice were not merely attributable to the
increasing popularity of mangosteen fruit or the effectiveness of
the marketing efforts employed.
Moreover, while Rambus argues long-felt need, skepticism, praise,
and failure of others (see Ram bus App. Br. 27-29), these arguments appear
15
See BPAI 2012-001639 at 44-45 (finding, based on cited prior art, that
DRAMs where "the most popular" memory chip at the time ofthe
invention) (adopted and incorporated herein by reference).
29
A31
Appeal 2012-001917
Patent 6,425,863 B2
to be directed to the a memory device as a single chip DRAM instead of the
broad claims recited here. Also, while Ram bus argues that the memory
devices solve a memory bottleneck problem and obtain high-speed
performance (see App. Br. 28-29), the claims read on slow memory devices,
since the claims do not recite any speed (as a functional limitation) and do
not recite other sufficient and necessary circuitry to obtain such speed.
16
Ram bus's allegations of recognition and praise for the "'high bandwidth
memory-interface technology'" and other similar speed features '"as a result
of the ideas [Dr. Horowitz] pioneered"' (App. Br. 29 (citation omitted)) lack
a nexus to the claims. The devices claimed here have no bandwidth
limitation, let alone limitations directed to the myriad other "ideas [Dr.
Horowitz] pioneered"- whatever they: may have been.
Moreover, Dr. Farmwald testified that "even up into the early part of
the '90s, it [speed] wasn't going to be a problem." (See Farmwald Trial
Dep. 276 (attached as App. Br. Evidence Ex. E-5).) In other words, Dr.
Farmwald may have solved a problem predicted to occur in the future using
a single chip solution; i.e., not a long-standing problem commensurate in
scope with the broad memory device claimed here. The then-current
16
In another reexamination proceeding, similar to the proceeding here
(Resp. Br. 15), Rambus alleges "disbelief' and pervasive skepticism '"over a
500 megabit per second DRAM data rate'" and "about many of the specific
features of the technology" as showing "'strong evidence of
nonobviousness."' See Rambus Resp. Br. 19 (citations omitted) in the BPAI
2012-000142 reexamination proceeding. Assuming for the sake of argument
that uncorroborated statements by the inventors show skepticism by others,
as noted, claims here do not require the 500 MHz speed touted or "many of
the other specific features"- whatever they may have been.
30
A32
Appeal2012-001917
Patent 6,425,863 B2
technology solved any speed problems (using several chips) as Dr.
Farmwald indicates.
Based on the foregoing discussion, the record suggests that the
proffered evidence is not commensurate with the claim scope and lacks a
nexus thereto. Ram bus has not demonstrated that any success is not due to
single DRAM chips which were known to be popular, synchronous memory
chips, synchronous memory devices such as the iAPX memory module, or to
a whole host of unclaimed features, including the unclaimed but touted
multiplexed bus interface, high bandwidth and/or speed, and other
unclaimed circuit features, such as the identification feature, arbitration
control features, low capacitance and power, etc. See Ormco Corp. v. Align
Technology, Inc., 463 F.3d 1299, 1312, 131:3 (Fed. Cir. 2006) ("[I]fthe
feature that creates the commercial success was known in the prior art, the
success is not pertinent." Reasoning that success thatis due "'partially' to
claimed features" and to unclaimed features and/or other features already in
the art lacks the requisite nexus to show unobviousness.) (citations omitted).
The record also indicates that such added features (and other
pioneering ideas) would have been required to obtain the touted high speed
from a single DRAM. See Infineon, 318 F .3d at 1095 (quoted supra,
mentioning Rambus's high speed multiplexed system).
Rambus has not established that its secondary evidence is
commensurate in scope with the broad reach of the claims. See Application
ofTiffzn, 448 F.2d 791 (CCPA 1971) (commercial success evidence of
thermoplastic foam cups is not commensurate in scope with broad claims
directed to thermoplastic foam containers). Even ifRambus's evidence does
point to the unobviousness of using dual internal clock edges or a DLL
31
A33
Appeal2012-001917
Patent 6,425,863 B2
circuit inside of a single DRAM, the proffered evidence does not rebut the
obviousness of using these known features within other memory devices
such as the iAPX memory module and array.
Rambus's proffered secondary considerations fail to outweigh the
evidence and rationale of record for combining known prior art dual edge
clock features with known memory device methods to yield predictable
results as set forth in the method claims at issue here.
Weak secondary considerations generally do not overcome a strong
prima facie case of obviousness. See Media Techs. Licensing, LLC v. Upper
Deck Co., 596 F.3d 1334 (Fed. Cir. 2010), cert. denied, 2010 WL 2897876
(Oct. 04, 2010) ("Even if[the patentee] could establish the required nexus, a
highly successful product alone would not overcome the strong showing of
obviousness.").
DECISION
The Examiner's decision to reject claims 1-28 is affirmed. Requests
for extensions oftime in this inter partes reexamination proceeding are
governed by 37 C.F.R. 1.956. See 37 C.F.R. 41.79.
ack
cc:
32
A34
Appeal2012-001917
Patent 6,425,863 B2
Patent Owner
FINNEGAN, HENDERSON, F ARAB OW, GARRETT & DUNNER LLP
901 NewYorkAve.,N.W.
Washington, DC 20001-4413
Third Party Requester Samsung
HAYNES AND BOONE, LLP IP SECTION
2323 VICTORY A VENUE, SUITE 700
DALLAS, TX 75219
Third Party Requester Micron
NOVAK, DRUCE & QUIGG, LLP
(NDQ REEXAMINATION GROUP)
1000 LOUISIANA STREET
HOUSTON, TX 77002
33
A35
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR
95/000,250 I 06/28/2007 6452863
22852 7590 02/ll!2013
FINNEGAN, HENDERSON, F ARABOW, GARRETT & DUNNER
LLP
901 NEW YORK AVENUE, NW
UNITED STATES DEPARTMENT OF COMI'tfERCE
Address: COMMISSIONER FOR PA TEJ\'TS
P.O. Box 1450
Alexandria, Virginia 223131450

38512.8 4189
EXAMINER
ESCALANTE, OVIDIO
3992
:1\.WLDATE DELIVERY MODE
02/11/2013 PAPER
Please find below and/or attached an Office commnnication concerning this application or proceeding.
PTOL-90A (Rev. 04/07)
A36
APPLICATION NO. FILING DATE FIRST NAMED IN""VENTOR
95/001,124 11124/2008 6452863
22852 7590 02!1112013
LLP
901 NEW YORK AVENUE, NW
UNITED STATES DEPARTMENT OF COMMERCE
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
896.002.863 5356
EXAMINER
ESCALANTE, OVJDIO
3992
MAIL DATE DELIVERY MODE
02/11/2013 PAPER
Please find below and/or attached an Office commnnication concerning this application or proceeding.
PTOL-90A (Rev. 04/07)
A37
BEFORE THE PATENT TRIAL AND APPEAL BOARD
RAMBUSINC.
Patent Owner, Appellant and Respondent
v.
MICRON TECHNOLOGY, INC.
Requester, Respondent and Cross-Appellant
and
SAMSUNG ELECTRONICS, INC.
Requester
Appeal2012-001917
Inter Partes Reexamination Control No. 95/000,250 & 95/001,124
United States Patent 6,452,863 B2
Technology Center 3900
Before HOWARD B. BLANKENSHIP, KARL D. EASTHOM, and
STEPHEN C. SIU, Administrative Patent Judges.
EASTHOM, Administrative Patent Judge.
DECISION ON RAMBUS'S REQUEST FOR REHEARING
A38
Appeal2012-001917
Patent 6,425,863 B2
Patent Owner Rambus seeks relief in its Patent Owner's Request for
Rehearing (Nov. 20, 2012). In response, Micron filed a Third Party
Requester's Comments to Patent Owner's Request for Rehearing Pursuant
to 37 C.F.R. 41.79 (Dec. 20, 2012) ("Micron's Comments").
In a rehearing request, parties have the burden to "state with
particularity the points believed to have been misapprehended or overlooked
in rendering the Board's opinion reflecting its decision." 37 C.P.R. 41.79
(b)(1). Rambus has not made the requisite showing.
Ram bus seeks reconsideration of the Board's finding that the memory
device and memory controller recited in claim 1 read respectively on the
iAPX memory module (which includes an MCU (memory control unit)) and
processor module (which includes a BIU (bus interface unit)) as disclosed in
the iAPX Manual.
1
As the Decision points out (see Dec. 5), the Federal Circuit decided
against Rambus regarding a similar issue and claim. In re Rambus Inc., 694
F.3d 42 (Fed. Cir. 2012) (holding that that the iAPX memory module which
includes an MCU chip and numerous memory chips constitutes a "memory
device" in Rambus's related patent claim.) Notwithstanding In re Rambus,
Rambus argues that "the Board should reconsider its decision and find that
the MCU is not part of the claimed memory device." (Reh'g Req. 5.) By
making the argument, Rambus effectively requests the Board to overrule or
somehow distinguish the Federal Circuit in In re Ram bus. Micron points out
that Rambus made similar arguments before the Federal Circuit in a
1
iAPX Interconnect Architecture Reference Manual (Intel Corp.) (1982).
The Manual also includes an associated Specification.
2
A39
Appeal 2012-001917
Patent 6,425,863 B2
rehearing request in In re Ram bus which was denied. (Requester Comments
2.)
Based on Rambus's arguments and the respective claims, the central
difference between claim 18 determined by In re Rambus to be anticipated
by the iAPX Manual is that claim 18 recites a "bus controller" instead of a
"memory controller" as recited in claim 1 at issue here. (See Reh'g Req. 4.)
In re Rambus involved a related Rambus patent which has continuity back to
a common application with the '863 patent. (See Dec. 10.) The Decision
compares Ram bus's two controllers and finds that Rambus does not point
the Board in a substantive or persuasive manner to a patentable distinction
therebetween.
The Decision reasons as follows:
Rambus does not direct attention to any difference between the
"memory controller" recited in claim 1 or the "bus controller"
determined by In re Rambus to read on the Bill in the iAPX
Manual. As In re Rambus reasons,
it is the bus controller (i.e., the 'BIU') of the iAPX that
is akin to the BIU that Rambus distinguished during
prosecution .... There is no suggestion that the BIU of
the iAPX is within the memory module, rather it is
clearly outside of the memory module, thus satisfying
the requirement that the memory module receive a
request from a bus controller.
(Dec. 7 (quoting In re Rambus, 694 F.3d at 50 (emphasis added).)
As quoted supra, In re Rambus finds that the iAPX BIU satisfies the
"bus controller" recited in claim 18 at issue there. The Decision finds that
Ram bus does not rely on anything in the '863 patent Specification to
3
A40
Appeal2012-001917
Patent 6,425,863 B2
distinguish the claimed "memory controller" from the claimed "bus
controller" involved in In re Rambus:
As discussed supra, the iAPX BIU performs error
checking, arbitration, and at least some manner of "address
queuing, since the BIU selects an address to which to send
requests." Rambus has not directed the Board in this
proceeding to limitations in the '863 patent defining or limiting
the claimed "memory controller" here and distinguishing it
from the claimed "bus controller" involved in the '918 patent
and in In re Rambus (the patents date back to a common
application, 07/510,898- see supra note 7). Presumably, a bus
controller and a memory controller, defined (if at all) by the
common '898 application, refer to the same device.
(Dec. 10 (emphasis added).)
Also, despite Rambus's arguments here, the Federal Circuit noted that
Rambus referred to a BIU as a memory controller in its argument to the
Federal Circuit: "Rambus's 'argument for allowance [over Jackson] hinged
on the BIU-a memory controller- not being part of the claimed memory
device.' Appellant's Br. 45 (emphasis in original)." 694 F.3d at 49 (quoting
Rambus's Appellant's Brief). (Accord Micron Comments 5 (quoting In re
Rambus at 49-50 and addressing Rambus's assertion that In re Rambus
distinguishes a "bus controller" and "memory controller").) Rambus's
argument here that a BIU is not a memory controller contradicts its
prosecution history based argument before the Federal Circuit that it is.
Rambus also does not provide a distinction between Jackson's BIU
discussed in In Re Rambus and the iAPX BIU. Moreover, the '863 patent
effectively equates bus and memory controllers as masters by referring to
"master or bus"controller devices, such as CPUs, Direct Memory Access
devices (DMAs)" and distinguishing masters from "slave devices" which
4
A41
Appeal2012-001917
Patent 6,425,863 B2
include "memory devices." ('863 patent, col. 6, II. 12-16.) In light of the
'863 patent Specification at column 6, memory and bus controllers are
masters. During prosecution of the '863 patent (App. No. 09/492982),
Rambus relied on this portion of the Specification (which describes a
"master or bus controller") to provide support for amended claims reciting a
"memory controller" limitation (Response to Office Action 2 (June 1,
2002))
2
and to overcome a written description rejection in which "the
Examiner was unable to find support for the memory controller in the
specification" (Non-fmal Rejection 2 (May 22, 2001). Hence, if a memory
controller is patentably distinct from a bus controller or master such as a
BIU as Rambus now effectively argues, the '863 patent lacks original
support for the memory controller, contrary to Rambus's prosecution history
arguments.
3
Rambus cannot have it both ways.
Instead of relying on the '863 patent Specification for the newly
argued distinction between a bus and memory controller, Rambus relies on
supposed distinctions between the claims, in the iAPX Manual, and in In re
Rambus, and argues that the Board "eliminates the differences." (See Reh'g
Req. 6.) But as argued by Rambus, relative to the recited memory device,
each claim implicitly requires an external (bus or memory) controller, and
In re Rambus does not create a distinction between an external memory
2
Rambus referred to the original Specification at "page 13, lines 13-16"
which corresponds to the same portion quoted supra from the column 6 of
the '863 patent.
3
A text search of the '863 patent for the term "memory controller" produces
hits for the term only in the claims (which are not original). Also, Rambus
filed a terminal disclaimer to overcome a double patenting rejection based
on the '918 patent at issue in In re Rambus. (See Amendment 4 (June 5,
2000).)
5
A42
Appeal2012-001917
Patent 6,425,863 B2
controller and an external bus controller, both of which read on the external
iAPX BIU (or the external processor module). Also, Ram bus eliminated any
distinction, if there was one, by as noted supra, pointing to written
descriptive support based on descriptions of a master bus controller in the
'863 patent and similarly calling the external '"BIU-a memory
controller."' 694 F.3d at 49 (quoting Rambus's Appellant's Brief at 45)
(emphasis by Board).
As to alleged distinctions based on the iAPX Manual, the claims
"must be read in view of the specification." Phillips v. AWH Corp., 415
F.3d, 1303, 1317 (Fed. Circ. 2005) (en bane). However, Rambus effectively
requests the Board to ignore the clear guidance in Phillips by reading the
claims in light of Ram bus's new citations to the iAPX Manual in order to
distinguish In re Rambus. "[T]he specification is always highly relevant to
the claim construction analysis. Usually, it is dispositive; it is the single best
guide to the meaning of a disputed term." Id. The Specification is
dispositive here as Rambus points to no disclosed distinction between its
claimed memory and bus controllers which both read on the iAPX BIU.
In addition, while Rambus focuses on the iAPX BIU (see Reh'g Req.
4), the Decision does not rely solely on the iAPX BIU as a master memory
controller, but also relies on, in the alternative, the iAPX "master processor
module" which includes the BIU and a processor in a GDP confinement
area. (See Dec. 8-9.) The Decision also lists memory control functions
performed by the BIU and the GDP. (See id. at 8-11.)
According to Rambus, since the BIU and MCU perform similar
functions, the Board should distinguish In re Rambus because it is
inconsistent for the Board to include the MCU in the claimed memory
6
A43
Appeal2012-001917
Patent 6,425,863 B2
device without also including the BIU. (See Reh'g Req. 5.) But, as noted,
Ram bus argued that a '"BIU-a memory controller. .. [is] not ... part of the
claimed memory device."' 694 F .3d at 49 (quoting Ram bus's Appellant's
Brief).
Assuming that Ram bus's arguments based on the iAPX Manual are
timell and probative, Rambus ignores the In re Rambus and Board findings
related to interface functionality and physical location which show
similarities between the iAPX system and the '863 patent system.
5
That is, In re Rambus finds that the '"BIU is ... clearly outside the
memory module"' (Dec. 7 (quoting In re Rambus )) and the Board finds that
4
Rambus's new arguments about the differences in functionality between
the BIU and MCU are untimely because they are based on new evidence
which was not presented to the Board in the appeal. The Board noted that
Rambus presented no argument to the Examiner and one truncated argument
about the BIU to the Board, citing the iAPX Manual as describing the BIU
as an "intelligent switch." (Dec. 7, n. 6 (noting that Rambus only presented
a limited "intelligent switch" argument to the Board).) Rambus now seeks
to expand that argument by new citations to the iAPX Manual. (See Reh'g
Req. 2-6.) Rambus also belatedly laments the fact that the Board and the
Examiner should have performed a more thorough analysis of the iAPX
Manual: "Had such an analysis been performed, the Board and Examiner
would have discovered that the ... MCU ... performs control functions of a
bus controller." (Reh'g Req. 2 (emphasis added).) Rambus's untimely
arguments place the burden in the wrong place. See In re Morris, 127 F.3d
1048, 1056 (Fed. Cir. 1997) ("It is the applicants' burden to precisely define
the invention, not the PTO's."). As such, Rambus's new function based
distinctions are untimely and waived since they are based on "evidence not
previously relied upon." See 37 C.F.R. 41.52.
5
The Board also analyzed other functions of a memory controller according,
inter alia, to Rambus's definitions, and finds the iAPX processor module
satisfies the definitions. (See Dec. 8-11.) Rambus's new arguments fail to
challenge the finding that the iAPX BIU satisfies Ram bus's definitions of a
memory controller.
7
A44
i\ppeal2012-001917
Patent 6,425,863 B2
the MCU is within the iAPX memory module which "'is confined to its own
area."' (Dec. 8 (quoting BPAI 2010-011178 at 28).) The MCU's location
allows it to act as an interface to the bus for the memory module- i.e.,
similar to the "device interface" disclosed as part of the memory device
recited in claim 1. (See '863 Patent Fig. 2.) The BIU or processor module is
external to the iAPX memory module, unlike the MCU, and does not
function as the memory mpdule or memory device interface to an external
bus. In re Rambus agreed with the PTO's characterization regarding the
similar interface functionality of the ii\PX MCU and claimed memory
device, i.e., the '863 patent's memory device "provide[s] at least the control
functionality necessary to enable the ... [device] to interface with the rest of
the system, similar to how the MCU controls the array in the iAPX
Manual." 694 F.3d at 49 (emphasis added).
Also, even if the BIU and MCU perform some overlapping functions
as Rambus argues, that does not imply that they must both be part of a
memory device, contrary to Rambus's argument. The '863 patent
specifically allows for overlapping master and slave functions in distinct
master and slave devices:
A slave device responds to control signals, a master sends
control signals. Persons skilled in the art will realize that some
devices may behave as both master and slave at various times,
depending on the mode of operation and the state of the system.
For example, a memory device will typically have only slave
functions, while a DMA controller, disk controller or CPU may
include both slave and master functions.
('863 Patent, col. 6, ll. 16-23 (emphasis added).)
The MCU is part of the slave memory device (i.e., the ii\PX memory
module), whereas the BIU is part of, or is, a master memory or bus
8
A45
Appeal2012-001917
Patent 6,425,863 B2
controller (i.e., the iAPX processor module). Analogous to the rationale in
In re Rambus which interprets the claimed memory device as not excluding
all control functions such as those in the iAPX MCU, see 694 F.3d at 49,
claim 1 only implies that the master "memory controller" must provide two
control functions -i.e., provide block size information and an operation
code.
6
As indicated further below and in the Decision, Ram bus does not
argue that the iAPX BIU (or its associated processor) fails to provide these
two functions to the MCU.
Micron's Comments persuasively addresses Rambus's arguments in
Rambus's Request and parallel the findings and rationale in the Board's
Decision and in In re Ram bus. Rather than repeating Micron's Comments
and other excerpts from the Decision, the Comments are adopted and
incorporated by reference here to address Rambus's contentions.
7
Micron
specifically addresses, inter alia, Rambus's contentions about the iAPX
BIU, the iAPX MCU, and the prosecution history involving Jackson, and
shows that the Decision does not overlook Rambus's contentions. (See
Micron Comments 2-7.) Micron persuasively points out that the Federal
Circuit in In re Rambus equated, or at least did not distinguish, the claimed
memory controller and the disclosed iAPX BIU or bus controller (id. at 5),
that the '863 patent does not distinguish the two, that the iAPX BIU or
processor module constitutes the claimed memory controller by controlling
operations placed on the bus, including arbitration, and directing actions of
6
Claim 1 does not explicitly recite that the memory controller must provide
the information and code. (See Dec. 11.)
7
The Decision is adopted and incorporated here by rule. See 37 C.P.R.
41.79 (d).
9
A46
Appeal2012-001917
Patent 6,425,863 B2
the memory modules, the BIU and processor function as a "master"
according to descriptions in the '863 Patent Specification, that the iAPX
MCU is part ofthe claimed memory device, and that Rambus attempts to
avoid the holding in In re Rambus. (See id.at 2-7.)
Rambus's other arguments rephrase or re-state similar arguments
made before the Board. For example, Ram bus argues as follows:
Even if the BIU or the processor module could be
considered a memory controller, which Rambus does not
concede, the purported memory controller of iAPX does not
provide block size information or an operation code to iAPX's
memory. As a result, the BIU or the processor module of iAP X
does not "provid[ e] first block size information to the memory
device" as recited in claim 1.
(Reh'g Req. 5 (emphasis added).)
The Decision considers a previous version of this argument as
follows: "Rambus's statement that the iAPX does not disclose sending block
size information in an operation code to a memory device similarly focuses
on the incorrect single chip argument- i.e., it is premised on the incorrect
assumption that the iAPX Manual's memory module is not a memory
device." (Dec. 8.)
As the arguments show, Ram bus relies on the same "incorrect single
chip argument" by asserting that the iAPX processor module or BIU does
not send the operation code or block size information "to [the] iAPX's
memory." (Reh'g Req. 5 (emphasis supplied).) Recognizing Rambus's
reference to the iAPX memory is key to understanding the argument. The
memory is a subset of the iAPX memory module; i.e., the "memory" is the
array of DRAM chips in the iAPX memory module as opposed to the MCU
therein. Hence, Rambus argues that the memory controller does not send the
10
A47
Appeal2012-001917
Patent 6,425,863 B2
required code and information to the "memory device" because Rambus
considers a single DRAM chip in the memory array to be the claimed
"memory device." Rambus does not challenge the Decision which relies on
the Examiner's finding that the iAPX Manual discloses that the BIU
provides the claimed block size information and the operation code to the
MCU interface (of the claimed memory device). (See Right of Appeal
Notice 51-52f Rambus also does not dispute the Board's characterization
ofRambus's argument as premised on this incorrect single chip argument.
Micron characterizes Rambus's argument in the same fashion. (See
Micron's Comments 7.)
Rambus's arguments with respect to the combination ofiAPX,
Lofgren,
9
and Inagaki
10
rely on its arguments presented with respect to claim
1 which are not persuasive based on the foregoing discussion. (See Reh'g
Req. 6-7.)
In sum, Rambus fails to meet the burden of distinguishing claim 1 in
the '863 patent from the iAPX system and anticipated claim 18 at issue in In
re Rambus. Ram bus requests the Board to effectively overrule In re Rambus
by weaving non-existent distinctions between the bus and master controllers
claimed in Rambus's two patents without requisite guidance from Rambus
based on the '863 patent Specification. As such, Ram bus fails to show that
8
In re Rambus notes that Ram bus conceded at oral argument similar control
logic exists in the MCU interface to allow reception by the iAPX MCU of
block size requests. See 694 F.3d at 49.
9
Lofgren et al., G.B. 2,197,553 A (May 18, 1988).
10
Inagaki, JP 57-210495 (Dec. 24, 1982) (reference hereinafter is to an
English language translation of record).
11
A48
Appeal2012-001917
Patent 6,425,863 B2
the Board overlooked any material arguments or evidence warranting a
modification of the Decision.
REHEARING DECISION
We decline to modify the Decision affirming the Examiner's decision
to reject claims 1-28.
DENIED
Patent Owner
FINNEGAN, HENDERSON, F ARAB OW, GARRETT & DUNNER LLP
901 New York Ave., N.W.
Washington, DC 20001-4413
Third Party Requester Samsung
HAYNES AND BOONE, LLP
IP SECTION
2323 VICTORY A VENUE, SillTE 700
DALLAS, TX 75219
Third Party Requester Micron
NOVAK, DRUCE & QillGG, LLP
(NDQ REEXAMINATION GROUP)
1000 LOillSIANA STREET, 53'ct FLOOR
HOUSTON, TEXAS 77002
12
A49
A60
111111 1111111111111111111111111111111111111111111111111111111111111
(12) United States Patent
Farmwald et al.
(54) METHOD OF OPERATING A MEMORY
DEVICE HAVING A VARIABLE DATA INPUT
LENGTH
(75) Inventors: Michael Farmwald, Berkeley; Mark
Horowitz, Palo Alto, both of CA (US)
(73) Assignee: Rambus Inc., Los Altos, CA (US)
( *) Notice: This patent issued on a continued pros-
ecution application filed under 37 CFR
1.53( d), and is subject to the twenty year
patent term provisions of 35 U.S.C.
154(a)(2).
Subject to any disclaimer, the term of this
patent is extended or adjusted under 35
U.S.C. 154(b) by 169 days.
This patent is subject to a terminal dis-
claimer.
(21) Appl. No.: 09/492,982
(22) Filed: Jan.27,2000
Related U.S. Application Data
(63) Continuation of application No. 09/252,997, filed on Feb.
19, 1999, now Pat. No. 6,034,918, which is a continuation
of application No. 09/196,199, filed on Nov. 20, 1998, now
Pat. No. 6,038,195, which is a continuation of application
No. 08/798,520, filed on Feb. 10, 1997, now Pat. No.
5,841,580, which is a division of application No. 08/448,
657, filed on May 24, 1995, now Pat. No. 5,638,334, which
is a division of application No. 08/222,646, filed on Mar. 31,
1994, now Pat. No. 5,513,327, which is a continuation of
application No. 07/954,945, filed on Sep. 30, 1992, now Pat.
No. 5,319,755, which is a continuation of application No.
07/510,898, filed on Apr. 18, 1990, now abandoned.
(51) Int. Cl? .................................................. GllC 8/00
(52) U.S. Cl. ................. .. ... ... ... ....... 365/233; 365/189.01
(58) Field of Search ................................. 365/233, 235,
365/238.5; 39/189.01
REGULAR ACCESS
US006452863B2
(10) Patent No.: US 6,452,863 B2
*Sep.17,2002 (45) Date of Patent:
(56)
EP
EP
EP
References Cited
U.S. PATENT DOCUMENTS
3,691,534 A
3,771,145 A
3,882,470 A
9/1972 Veradi et a!. ................. 365/78
11/1973 Wiener ....................... 365/240
5/1975 Hunter ....................... 365/200
(List continued on next page.)
FOREIGN PATENT DOCUMENTS
0 246 767
0 276 871
0282735
4/1987
1!1988
9/1988
OTHER PUBLICATIONS
M. Bazes et. al., "A Programmable NMOS DRAM Control-
ler for Microcomputer Systems with Dual-Port Memory and
Error Checking and Correction", IEEE Journal of Solid
State Circuits, vol. 18 No.2, pp. 164--172 (Apr. 1983).
A. Agarwal, "An Evaluation of Directory Schemes for
Cache Coherence", IEEE document pp. 280-289 (1988).
D. Kawley, "Superfast Bus Supports Superfast Transac-
tions", High Performance Systems, pp. 90--94 (Sep. 89).
Primary Examiner-Tan T. Nguyen
(74) Attorney, Agent, or Firm-Neil A Steinberg
(57) ABSTRACT
A method of controlling a memory device, wherein the
memory device includes a plurality of memory cells. The
method includes providing first block size information to the
memory device, wherein the first block size information
defines a first amount of data to be input by the memory
device in response to a write request. The method further
includes issuing a write request to the memory device,
wherein in response to the write request the memory device
inputs the first amount of data corresponding to the first
block size information.
35 Claims, 14 Drawing Sheets
ADDRVALID BUS DATA[0:7]
24
) CYCLE
0- EVEN
1
I
I I I I I I I
3_
v ACCESSTYPE[0:3] : MASTER[0:3] 2
ADDRESS[0:8] 25 1 -ODD
22
--
ADDRESS[9: 17]
2
ADDRESS[18:26] 3
ADDRESS[27:35]
26 4
27-- - 0
I
ADDFIESS[36:39] : BLOCKSIZE[0:3] 5
\.._.
28
A61
US 6,452,863 B2
Page 2
U.S. PATENT DOCUMENTS 4,949,301 A
4,951,251 A
4,953,128 A
4,954,987 A
4,975,872 A
4,979,145 A
5,009,481 A
5,016,226 A
5,018,111 A
5,029,124 A
5,034,964 A
5,036,495 A
5,083,260 A
5,083,296 A
5,093,807 A
5,107,465 A
5,109,498 A
5,111,486 A
5,123,100 A
5,134,699 A
5,140,688 A
5,142,376 A
5,142,637 A
5,148,523 A
5,175,835 A
5,179,667 A
5,193,193 A
5,206,833 A
5,276,846 A
5,301,278 A
5,361,277 A
5,684,753 A
6,034,918 A *
8/1990
8/1990
8/1990
9/1990
Joshi et a!. ................. 711!100
4,047,246 A
4,048,673 A
4,092,665 A
4,099,231 A
4,183,095 A
4,205,373 A
4,231,104 A
4,330,852 A
4,337,523 A
4,394,753 A
4,435,762 A
4,445,204 A
4,466,127 A
4,482,999 A
4,509,142 A
4,513,370 A
4,536,795 A
4,566,099 A
4,586,167 A
4,589,108 A
4,616,268 A
4,625,307 A
4,629,909 A
4,631,659 A
4,648,102 A
4,663,735 A
4,672,470 A
4,675,850 A
4,680,738 A
4,685,088 A
4,703,418 A
4,719,505 A
4,719,602 A
4,726,021 A
4,734,880 A
4,748,617 A
4,750,839 A
4,755,937 A
4,763,249 A
4,785,394 A
4,785,428 A
4,788,667 A
4,792,926 A
4,799,199 A
4,803,621 A
4,807,189 A
4,821,226 A
4,825,287 A
4,825,416 A
4,835,674 A
4,839,801 A
4,845,664 A
4,845,670 A
4,845,677 A
4,849,965 A
4,851,990 A
4,870,562 A
4,870,622 A
4,873,671 A
4,875,192 A
4,876,670 A
4,878,166 A
4,882,712 A
4,891,791 A
4,901,036 A
4,920,483 A
4,926,385 A
4,928,265 A
4,937,734 A
4,945,516 A
9/1977 Kerllenevich et a!. ........ 710/61
9/1977 Hendrie et a!. ............. 710/129
5/1978 Saran ... ... .. ... ... ... ... ... .. . 341/63
7/1978 Kotok et a!. ...... .......... 711!168
1/1980 Ward ..................... 365/189.02
5/1980 Shah et a!. ................. 710/128
10/1980 St. Clair ............ .. ....... 713/500
5/1982 Redwine et a!. ............ 365/221
6/1982 Hotta et a!. ......... .. ...... 365/194
7/1983 Penzel ........................ 365/236
3/1984 Milligan et a!. ............... 710/6
4/1984 Nishiguchi .................. 365/194
8/1984 Ohgishi et a!. .... .... 455/182.01
11/1984 Janson et a!. ............... 370/452
4/1985 Childers ........... .. ... ..... 364/900
4/1985 Ziv et a!. .................... 709/253
8/1985 Hirota et a!. ............... 348/714
1/1986 Mager! ....................... 370/509
4/1986 Fujishima et a!. ..... 365/189.05
5/1986 Billy .......................... 370/503
10/1986 Shida et a!. ................ 358/451
11/1986 Tulpule et a!. .............. 370/402
12/1986 Cameron .......... .. ... ..... 327/211
12/1986 Hayne et a!. ............... 711!167
3/1987 Riso et a!. .................. 375/356
5/1987 Novak et a!. ............... 345/515
6/1987 Morimoto et a!. ............ 386/16
6/1987 Kumanoya et a!. .... 365/189.08
7/1987 Tam ........................... 365/239
8/1987 Ianucci ....................... 365/194
10/1987 James ........................ 364/200
1/1988 Katznelson ................. 348/502
1/1988 Hag et a!. .............. 365/189.02
2/1988 Horiguchi et a!. ............ 371/38
3/1988 Collins ....................... 711!105
5/1988 Drewlo ....................... 359/121
6/1988 Wang et a!. ................ 365/233
7/1988 Glier
8/1988 Bomba et a!. .............. 364/200
11/1988 Fischer ............. .. ... ..... 710/114
11/1988 Bajwa ........................ 365/233
11/1988 Nakano et a!. ............. 365/193
12/1988 Roberts ................. 365/189.02
1/1989 Scales, III et a!. ...... 365/230.08
2/1989 Kelly ............................ 711!5
2/1989 Pinkham et a!. ....... 365/189.05
4/1989 Christopher et a!. .. . 365/230.03
4/1989 Baji et a!. ................... 348/720
4/1989 Tam et a!. ....... .. ... ...... 365/194
5/1989 Collins eta!. .............. 709/214
6/1989 Nicely et a!. ................. 710/35
7/1989 Aichelmann, Jr. et a!. .. 364/900
7/1989 Nishimoto et a!. ........... 365/78
7/1989 Chappell et a!. ....... 365/189.02
7/1989 Chomel et a!. ............. 370/438
7/1989 Johnson et a!. ............. 710/100
9/1989 Kimoto et a!. .............. 364/200
9/1989 Aria et a!. .... .. ...... . 365/230.02
10/1989 Kowshik et a!. ....... 365/189.12
10/1989 Matsumoto
10/1989 Nakabayashi et a!. . 365/189.12
10/1989 Johnson et a!. ............. 710/127
11/1989 Ohno et a!. ................. 365/206
1/1990 Iijima .................... 365/189.01
2/1990 Herold et a!. ................. 331!25
4/1990 Pogue et a!. ................ 364/200
5/1990 Fujishima et a!. .... . 365/230.03
5/1990 Beighe et a!. ......... 365/189.01
6/1990 Bechtolsheim .............. 711!202
7/1990 Kashiyama ............ 365/189.05
EP
EP
EP
EP
JP
JP
JP
JP
JP
JP
JP
JP
JP
JP
JP
JP
JP
JP
JP
wo
12/1990
12/1990
4/1991
5/1991
5/1991
7/1991
7/1991
7/1991
1!1992
1!1992
3/1992
4/1992
4/1992
5/1992
6/1992
7/1992
8/1992
8/1992
8/1992
9/1992
12/1992
1!1993
3/1993
4/1993
1!1994
4/1994
11/1994
11/1997
3/2000
Yamaguchi et a!. ... 365/189.02
Kawai eta!. ............... 365/194
Auvinen et a!. ....... 365/189.02
Zaiki .... ...... ...... .. ...... ... 365/49
Remington et a!. ......... 711!106
Kinoshita et a!. ............. 385/33
Hiwada eta!. ............. 365/233
Madland .......... .. ... ...... 365/233
Leahy et a!. ................ 710/105
Khan et a!. ..... .. ... ....... 375/242
Busch eta!. ................ 365/233
Tsuchiya .................... 710/113
Hara et a!. .... ...... ... 365/230.02
Hashimoto et a!. .... 365/230.09
Fung et a!. ...... ...... 365/230.08
Kamiya et a!. ............. 395/425
Oliboni et a!. .............. 375/120
Hisada et a!. ............... 713/401
Aria eta!. .................... 710/35
White et a!. ................ 345!550
Ogura .. .. .. .. .. .. . .. . .. .. .. .. . 386/29
Harlin et a!. ............... 345/425
Harlin et a!. ............... 345/519
Beighe et a!. ..... .. ....... 711!212
Iyer ........................... 711!167
Iyer ........................... 710/117
Lee ............................ 365/233
Aichelmann, Jr. et a!. .. 711!165
Bowater et a!. .... ........ ... 711!5
Grover ........................ 375/36
Hashimoto et a!. ......... 365/233
Farmwald et a!. .......... 365/233
FOREIGN PATENT DOCUMENTS
0 334 552
0218523
0449052
0424774
S56-82961
S57-14922
Sho 60-80193
SHO 58-192154
Sho 60-55459
S61-72350
SHO 61-107453
SHO 61-160556
SHO 62-16289
62-51509
SHO 63-34795
SHO 63-91766
S63-142445
B63-46864
S64-29951
wo 89/12936
3/1989
5/1989
3/1990
5/1991
7/1981
1!1982
5/1983
11/1983
3/1985
4/1986
5/1986
10/1986
1!1987
3/1987
2/1988
4/1988
6/1988
9/1988
1!1989
12/1989
OTHER PUBLICATIONS
H. L. Kalter et al., "A 50-ns 16Mb DRAM with a 10-ns
Data Rate and On-Chip ECC", IEEE Journal of Solid State
Circuits, vol. 25 No. 5, pp. 1118-1128 (Oct. 1990).
S. Watanabe et. al., "AN Experimental 16-Mbit CMOS
DRAM Chip with a 100-MHz serial READ/WRITE Mode",
IEEE Journal of Solid State Circuits, vol. 24 No. 3, pp.
763-770 (Jun. 1982).
T.L. Jeremiah et. al., "Synchronous Packet Switching
Memory and 1/0 Channel," IBM Tech. Disc. Bul,. vol. 24,
No. 10, pp. 4986-4987 (Mar. 1982).
A62
US 6,452,863 B2
Page 3
L. R. Metzeger, "A 16K CMOS PROM with Polysilicon
Fusible Links", IEEE Journal of Solid State Circuits, vol. 18
No. 5, pp. 562-567 (Oct. 1983).
A Yuen et. al., "A 32K ASIC Synchronous RAM Using a
Two-Transistor Basic Cell", IEEE Journal of Solid State
Circuits, vol.24 No. 1, pp. 57-61 (Feb. 1989).
D.T. Wong et. al., "An 11-ns 8Kx18 CMOS Static RAM
with O.S,um Devices", IEEE Journal of Solid State Circuits,
vol. 23 No. 5, pp. 1095-1103 (Oct. 1988).
T. Williams et. al., "An Experimentall-Mbit CMOS SRAM
with Configurable Organization and Operation", IEEE Jour-
nal of Solid State Circuits, vol. 23 No. 5, pp. 1085-1094
(Oct. 1988).
D. Jones, "Synchronous static ram", Electronics and Wire-
less World, vol. 93, No. 1622, pp. 1234--1244 (Dec. 87).
F. Miller et. al., "High Frequency System Operation Using
Synchronous SRAMS", Midcon/87 Conference Record, pp.
430--432 Chicago, IL, USA; Sep. 15-17, 1987.
K. Ohta, "A 1-Mbit DRAM with 33-MHz Serial I/O Ports",
IEEE Journal of Solid State Circuits, vol. 21 No. 5, pp.
649-654 (Oct. 1986).
K. Nogami et. al., "A 9-ns HIT-Delay 32-kbyte Cache
Macro for High-Speed RISC", IEEE Journal of Solid State
Circuits, vol. 25 No. 1, pp. 100--108 (Feb. 1990).
F. Towler et. al., "A 128k 6.5ns Access/Sus Cycle CMOS
ECL Static RAM", 1989 IEEE international Solid State
Circuits Conference, (Feb. 1989).
M. Kimoto, "A 1.4ns/64kb RAM with 85ps/3680 Logic
Gate Array", 1989 IEEE Custom Integrated Circuits Con-
ference.
D. Wendell et. al. "A3.5ns, 2Kx9 Self Timed SRAM", 1990
IEEE Symposium on VLSI Circuits (Feb. 1990).
R. Schmidt, "A memory Control Chip fo Formatting Data
into Blocks Suitable for Video Applications", IEEE Trans-
actions on Circuits and Systems, vol. 36, No. 10 (Oct. 1989).
D. K. Morgan "The CVAX CMCTL-A CMOS Memory
Controller Chip", Digital Technical Journal, No. 7 (Aug.
1988).
T.C. Poon et. al., "A CMOS DRAM-Controller Chip Imple-
mentation", IEEE Journal of Solid State Circuits, vol. 22 No.
3, pp. 491-494 (Jun. 1987).
K. Numata et. al. "New Nibbled-Page Architecture for High
Density DRAM's", IEEE Journal of Solid State Circuits,
vol. 24 No. 4, pp. 900-904 (Aug. 1989).
E.H. Frank "The SBUS: Sun's High Performance System
Bus for RISC Workstations" Sun Microsystems Inc. 1990.
Watanabe, T.; "Session XIX: High Density SRAMS"; IEEE
International Solid State Circuits Conference pp. 266-267
(1987).
Ohno, C.; "Self-Timed RAM: STRAM"; Fujitsu Sci.
TechJ., 24, 4, pp. 293-300 (Dec. 1988).
"Fast Packet Bus for Microprocessor Systems with Caches",
IBM Technical Disclosure Bulletin, pp. 279-282 (Jan.
1989).
Gustavson, D. "Scalable Coherent Interface"; Invited Paper,
COMPCON Spring '89, San Francisco, CA; IEEE, pp.
536-538 (Feb. 27-Mar. 3, 1989).
James, D.; "Scalable 1!0 Architecture for Busses"; IEEE, pp.
539-544 (Apr. 1989).
European Search Report for EPO Patent Application No. 00
1011832.
European Search Report for EPO Patent Application No. 89
30 2613.
Z. Amitai, "New System Architectures for DRAM Control
and Error Correction", Monolithic Memories Inc., Electro/
87 and Mini/Mica Northeast: Focusing on the OEM Con-
ference Record, pp. 1132, 4/31-3, (Apr. 1987).
N. Siddique, "100-MHz DRAM Controller Sparks Multi-
processor Designs", Electronic Design, pp. 138-141, (Sep.
1986).
H. Kuriyama et al., "A 4-Mbit CMOS SRAM with 8-NS
Serial Access Time", IEEE Symposium On VLSI Circuits
Digest Of Technical Papers, pp. 51-52, (Jun. 1990).
J. Chun et al., "A 1.2ns GaAs 4K Read Only Memory",
IEEE Gallium Arsenide Integrated Circuit Symposium
Technical Digest, pp. 83-86, (Nov. 1988).
A Fielder et al., "A 3 NS lK X 4 Static Self-Timed GaAs
RAM", IEEE Gallium Arsenide Integrated Circuit Sympo-
sium Technical Digest, pp. 67-70, (Nov. 1988).
JEDEC Standard No. 21C.
Takasugi, A. et al., "A Data-Transfer Architecture for Fast
Multi-Bit Serial Acess Mode DRAM," 11'h European Solid
State Circuits Conference, Toulouse, France pp. 161-165
(Sep. 1985).
Amitai, Z., "Burst Mode Memories Improve Cache Design,"
WESCON/90 Conference Record, pp. 279-282 (Nov.
1990).
Ikeda, Hiroaki et al., "100 MHz Serial Acess Architecture
for 4Md Field Memory," Symposium of VLSI Circuits,
Digest of Technical Papers, pp. 11-12 (Jun. 1990).
Schmitt-Landsiedel, Doris, "Pipeline Architecture for Fast
CMOS Buffer RAMs," IEEE Journal of Solid-State Cir-
cuits, vol. 25, No. 3, pp. 741-747 (Jun. 1990).
Horowitz et al., "MIPS-X: A20-MIPS Peak 32-Bit Micro-
processor with ON-Chip Cache", IEEE J. Solid State Cir-
cuits, vol. SC-22, No. 5, pp. 790-798 (Oct. 1987).
Robert J. Lodi et al., "Chip and System Characteristics of a
2048-Bit MNOS-BORAM LSI Circuit," 1976 IEEE Inter-
national Solid-State Circuits Conference (Feb. 18, 1976).
Whiteside, Frank, "A Dual-Port 65ns 64Kx4 DRAM with a
SOMHz Serial Output,"IEEE International Solid-State Cir-
cuits Conference Digest (Feb. 1986).
Pinkham, Raymond, "A High Speed Dual Port Memory with
Simultaneous Serial and Random Mode Access for Video
Applications," IEEE Journal of Solid-State Circuits, vol.
SC-19, No. 6, pp. 999-1007 (Dec. 1984).
Ishimoto, S. et al., "a 256K Dual Port Memory," ISSCC
Digest of Technical Papers, pp. 38-39 (Feb. 1985).
Iqbal, Mohammad Shakaib, "Internally Timed RAMs Build
Fast Writable Control Stores," Electronic Design, pp. 93-96
(Aug. 25, 1988).
Schnaitter, William M. et al., "AO.S-GHz CMOS Digital RF
Memory Chip," IEEE Journal of Solid-State Circuits, vol.
SC-21, No. 5, pp. 720-726 (Oct. 1986).
Bursky, Dave, "Advanced Self-Timed SRAM Pares Access
Time to 5 ns," Electronic Design, pp. 145-147 (Feb. 22,
1990).
Tomoji Takada et al., "A Video Codec LSI for High-Defi-
nition TV Systems with One-Transistor DRAM Line
Memories," IEEE Journal of Solid-State Circuits, vol. 24,
No. 6, pp. 1656-1659 (Dec. 1989).
Robert J. Lodi et al., "MNOS-BORAM Memory Charac-
teristics," IEEE Journal of Solid-State Circuits, vol. SC-11,
No. 5, pp. 622-631 (Oct. 1976).
Gregory Uvieghara et al., "an On-Chip Smart Memory for
a Data-Flow CPU," IEEE Journal of Solid-State Circuits,
vol. 25, No. 1, pp. 84--89 (Feb. 1990).
A63
US 6,452,863 B2
Page 4
Ray Pinkham et al., "A 128Kx8 70--MHz Multipart Video
RAM with Auto Register Reload and 8x4 WRITE Feature,"
IEEE Journal of Solid State Circuits, vol. 23, No. 3, pp.
1133-1139 (Oct. 1988).
Hans-Jurgen Mattausch et al., "a Memory-Based High-
Speed Digital Delay Line with a Large Adjustable Length,"
IEEE Journal of Solid-State Circuits, vol. 23, No. 1, pp.
105-110 (Feb. 1988).
Kanopoulos, Nick and Jill H. Hallenbeck, "A First-In,
First-Out Memory for Signal Processing Applications,"
IEEE Transactions on Circuits and Systems, vol. CAS-33,
No. 5, pp. 556-558 (May 1986).
Pelgrom et al., "A 32-kbit Variable-Length Shift Register
for Digital Audio Application", IEEE Journal of Solid-State
Circuits, vol. sc-22, No. 3, Jun. 1987, pp. 415-422.
Grover et al., "Precision Time-Transfer in Transport Net-
works Using Digital Crossconnect Systems", IEEE Paper
47.2 Globecom, 1988, pp 1544-1548.
Gustavson et al., "The Scalable Interface Project (Super-
bus)" (DRAFT), SCI-22 Aug 88--doc1 pp. 1-16, Aug. 22,
1988.
Knut Alnes, "SCI: A Proposal for SCI Operation",
SCI-10Nov88-doc23, Norsk Data, Oslo, Norway, pp. 1-12,
Nov. 10, 1988.
Knut Alnes, "SCI: A Proposal for SCI Operation",
SCI-6Jan89-doc31, Norsk Data, Oslo, Norway, pp. 1-24,
Jan. 6, 1989.
Bakka et al., "SCI: Logical Level Proposals",
SCI-6Jan89-doc32, Norsk Data, Oslo, Norway, pp. 1-20,
Jan. 6, 1989.
Knut Alnes, "Scalable Coherent Interface",
SCI-Feb89--doc52, (To appear in Eurobus Conference Pro-
ceedings May 1989) pp. 1-8.
Boysel et al., "Four-Phase LSI Logic Offers New Approach
to Computer Designer", Four-Phase Systems Inc. Cuper-
tino, CA, Computer Design, Apr. 1970, pp. 141-146.
Boysel et al., "Random Access MOS Memory Packs More
Bits To The Chip", Electronics, Feb. 16, 1970, pp. 109-146.
Hansen et al., "A RISC Microprocessor with Integral MMU
and Cache Interface", MIPS Computer Systems, Sunnyvale,
CA, IEEE 1986 pp. 145-148.
Moussouris et al., "A CMOS Processor with Integrated
Systems Functions", MIPS Computer Systems, Sunnyvale,
CA, IEEE 1986 pp. 126-130.
"LR2000 High Performance RISC Microprocessor Prelimi-
nary" LSI Logic Corp. 1988, pp. 1-15.
"LR2010 Floating Point Accelerator Preliminary" LSI Logic
Corp. 1988, pp. 1-20.
"High Speed CMOS Databook", Integrated Device Tech-
nology Inc. Santa Clara, CA, 1988 pp. 9-1 to 9-14.
Riordan T. "MIPS R2000 Processor Interface
78-00005(C)", MIPS Computer Systems, Sunnyvale, CA,
Jun. 30, 1987, pp. 1-83.
Moussouris, J. "The Advanced Systems Outlook-Life
Beyond RISC: The next 30 years in high-performance
computing", Computer Letter, Jul. 31, 1989 (an edited
excerpt from an address at the fourth annual conference on
the Advanced Systems Outlook, in San Francisco, CA (Jun.
5)).
* cited by examiner
A64
U.S. Patent
Sep.17,2002
FIG_
3
Sheet 1 of 14
US 6,452,863 B2
RAM ARRAY
WORD
LINES
6
BITLINES
COLUMN AMPLIFIERS
COLUMN
SELECT
1
A65
F
I
G
_
2

1
1

1
2

1
6
1

1
3

1
6
1
\

C
P
U

l

R
O
M

(

D
R
A
M

D
E
V
I
C
E

D
E
V
I
C
E

D
E
V
I
C
E

I
N
T
E
R
F
A
C
E

I
N
T
E
R
F
A
C
E

I
N
T
E
R
F
A
C
E

R
E
S
E
T
O
U
T

I
I

l

I
I

l

I
I

l

I

I

I

I

'

I

I

I

I

I

I

I

-
-
-
-
-
-
-
-
-
-
-
-

-
-
-
-
-
-
-
-
-
-
-

-
-
-
-
-
-
-
-
-
-
-
-

-
-
-
-
1
4

D
R
A
M

~
1
6
1

D
E
V
I
C
E

I
N
T
E
R
F
A
C
E

I
I

l

'

R
E
S
E
T
I
N

I

I

B
U
S
D
A
T
A
[
7
]

I

_
_
_
_
_
_
_

.
.
.

-
-
-
-
-
-
-
-
-

B
U
S
D
A
T
A

[
1
]

B
U
S
D
A
T
A

[
0
]

A
D
D
R
V
A
L
I
D

C
L
O
C
K
1

C
L
O
C
K
2

V
R
E
F

G
N
D

V
o
o

d

I
J
l

~

~

~

~

=

~

\
F
J
.

~

'
?

"
"
"
"

-
.
.
-
.
.
.
1

N

Q

Q

N

\
F
J
.

:
r

~

~

~

N

=

-
.
.

"
"
"
"

~

e

'
J
l

~

)
.

0
1

N

~

~

w

~

N

A66

R
E
G
U
L
A
R

A
C
C
E
S
S

2

1

I

I

I

I

I

I

I

I

v

A
C
C
E
S
S
T
Y
P
E
[
0
:
3
]

:

M
A
S
T
E
R
[
0
:
3
]

A
D
D
R
E
S
S
[
0
:
8
]

2
2

A
D
D
R
E
S
S
[
9
:
1
7
]

A
D
D
R
E
S
S
(
1
8
:
2
6
]

A
D
D
R
E
S
S
(
2
7
:
3
5
]

I
-
0

I

A
D
D
F
1
E
S
S
[
3
6
:
3
9
]

:

B
L
O
C
K
S
I
Z
E
[
0
:
3
]

=
-
:
=
-
I
c
;
_
L
I
-
2
4

C
Y
C
L
E

0
-
E
V
E
N

2
5

1
-
0
0
0

2

3

2
6

4

5

2
8

d

\
J
J
.

.
.
.
.
.
.

=

.
.
.
.
.
.

'
J
J
.

'
?

1
-
"

N

c

c

N

'
J
J
.

=
-

.
.
.
.
.

1
-
"

e

r
J
'
l

0
'
1

1
;
.

O
l

N

Q
o

0
'
1

N

A67
U.S. Patent
23
28
,_
----
23
-
22
--
ADDRVALID
~
f.-'
1
0
ADDRVALID
_....
1
---
27
-
1
0
0
~
0
0
29
Sep.17,2002 Sheet 4 of 14
REJECT(NACK)CONTROLPACKET
BUSDATA[0:7)
I I I I I
ACCESSTYPE[0:3] : MASTER[0:3] = 0
INF0(0:7]
.---Ic_51
BUSDATA(0:7]
I I I I I
ACCESSTYPE[0:3] : MASTER[0:3]
ADDRESS[0:8]
ADDRESS[9:17]
ADDRESS[18:26]
ADDRESS[27:35]
ADDRESS[36:39]: BLOCKSIZE[0:3]
XXX
XXX
XXX
XXX
INVALID: REQUEST[1 :7]
REQUEST[8:15]
.--IG_I:i
I
I
US 6,452,863 B2
I
I
24
25
26
28
29
30
31
32
33
34
CYCLE
0- EVEN
1-0DD
CYCLE
0
2
3
4
5
6
7
8
9
10
11
A68
U.S. Patent Sep.17, 2002 Sheet 5 of 14
US 6,452,863 B2
8
44
FIG_7_A
A69
U.S. Patent
Sep.l7,2002
Sheet 6 of 14
lL
1-
~ - - - - - - - . - - - - - - - - - - - - - - - - - - - - - - -
_..l
<(W
U::J
- _J 0
C.9<(
0>
_J
w
(.9
;::
_J
0
>
~ - - - - - - - . - - - - --- ___ ___.
.------'------- "------.
~
~
"
0
.,.....
L{')
~
_-::t
-I{)
ctl-::t'
..c<::t
- ~ - -
-.....
><(
><(
LL
1-
i
1'--
- - ___.) -::t
<.0
-::t
-- ~
US 6,452,863 B2
lL
lL
0
<(
lL
ZLL
00
<(CD
A70
U.S. Patent
Sep.17,2002 Sheet 7 of 14
US 6,452,863 B2
50
CLOCK1
CLOCK2
54
55\ . /56
CHIP N 52 ____ ___ L_l
,. 0 n 0 n, 0 (58

A71
U.S. Patent Sep.17,2002 Sheet 8 of 14 US 6,452,863 B2
A72
l ~ = l l
o!Y
a:
(f)
w
w
z
X
w
:J
__.J
I-
0....
:J
I- 0....
__.J
I-
:J
:J
2 0
l.[)
I'-
0
.q:
0....
+f-o
iS:w
O'l ,zo::
CD
N
:::.:::
I'-
__.J
0
C")
I'-
+f-o
c
:::Jw
I
~ 0 : :
w
A
,.-
~ 0
1:sh
I'-
1--Z
I
:JW
o....O::
() I'-
zW
- LL
~
w co
0::
CD
~
A73
F-IG_ II
SAMPLE
68
69
S E N S E ~
INPUT- INPUT+
INPUT REFERENCE
PAD
A74
F
I
G
_
I
2

E
A
R
L
Y

C
L
O
C
K

5
3

L
A
T
E

C
L
O
C
K

5
4

(
1
0
0

C
L
K
1
1
0
1
_
_
.
/

(
1
1
0

C
L
K
2
1
1
1
-
-
-
1

C
L
O
C
K
E
D

R
E
C
E
I
V
E
R

C
L
O
C
K
E
D

R
E
C
E
I
V
E
R

D
C

A
M
P

1
0
3

"
<
_
1
0
2

I

D
E
L
A
Y

L
I
N
E

/

1
1
6
-
~

F
I
L
T
E
R

F
I
L
T
E
R

1
0
4

(

L
[
1
U
f

D
E
L
A
Y
=

T
o

r
1
0
5
_
{
1
0
8

D
E
L
A
Y
=

T
o
+

X

~
1
1
5

r
1
0
6

(
7
3

-
D
E
L
A
Y
=

T
o
+

X
/
2

,

"
-
-
1
1
5

T
O

I
N
P
U
T

S
A
M
P
L
E
R
S

d

\
J
l

~

~

.
.
.
.
.
.

~

=

.
.
.
.
.
.

'
J
J
.

~

'
?

'
"
"
"
'

~
-
.
.
J

N

c

c

N

'
J
J
.

=
-
~

~

.
.
.
.
.

'
"
"
"
'

'
"
"
"
'

0

.
.
.
.
.
.
,

'
"
"
"
'

~

e

r
J
'
l

0
'
1

'
l
.

(
I
t

N

O
o

0
'
1

~

~

N

A75
F
I
G
_
I
3

I

I

I

j
_
_
l

_
_

B
U
S

C
L
O
C
K
1

5
3

_
.
/
1

1
2
1

/

1
2
1

I

B
U
S

C
L
O
C
K
2

5
4

D
E
L
A
Y

L
I
N
E

O
U
T
P
U
T

1
0
7

D
E
L
A
Y

L
I
N
E

O
U
T
P
U
T

1
0
8

I
N
T
E
R
N
A
L

C
L
O
C
K

7
3

I
N
T
E
R
N
A
L

C
L
O
C
K

C
O
M
P
L
E
M
E
N
T

7
4

I

:

J

~
-
-
-
-
-
/
J
_
_
I

-
-
_
_

_
_
_
_
.

:

1
2
3
:

1
2
3

I

I

I

I

1
2
8

:

:

I

=
+
!
l
~

l

I

J

-
-
_
j

-
-
-
-
-
'
-
/
.

1

1
2
0

1
2
0

:

I

I

_
_

I

_
_
I

l

1
2
2
/
_
_
_

_

L

r
-
-
-
1
2
4
/

I

.

L

I
N
P
U
T

S
A
M
P
L
E

1
2
7
)

1
2
5
)

1
2
7
)

1
2
5
)

t

d

0
0

~

~

~

~

=

~

r
J
1

~

~

_
;
-
-
l

N

=

=

N

r
J
1

:
:
r

~

~

~

N

~

.
.
.
,

~

~

e

r
J
'
l

~

~

U
l

N

Q
o

~

w

~

N

A76
U.S. Patent Sep.17,2002
z
~
I-
0
w
0
(f)
_J
w
0
a:
Sheet 13 of 14
I-
:::>
0
I-
w
(f)
w
a:
C\J
+
z
.,....
+
z
z
~
1'-
0
.........
<(
I-
<(
0
(f)
:::>
co
US 6,452,863 B2
A77
U.S. Patent
Sep.17,2002
Sheet 14 of 14
US 6,452,863 B2
FIG_I5
130
131
1 5 0 - - . . . ~ . -
148
146
147 A
147
B
132
149 146
133
151
135
152
136
137
153
138
139
154
140
155
141
142
156
143
144
157
145
A78
US 6,452,863 B2
1
METHOD OF OPERATING A MEMORY
DEVICE HAVING A VARIABLE DATA INPUT
LENGTH
This application is a continuation of application Ser. No. 5
09/252,997 now U.S. Pat. No. 6,034,918, which is a con-
tinuation of application Ser. No. 09/196,199, filed on Nov.
20, 1998 now U.S. Pat. No. 5,038,195, which is a continu-
ation of application Ser. No. 08/798,520, filed on Feb. 10,
1997 (now U.S. Pat. No. 5,841,580); which is a division of 10
application Ser. No. 08/448,657, filed May 24, 1995 (now
U.S. Pat. No. 5,638,334); which is a division of application
Ser. No. 08/222,646, filed on Mar. 31, 1994 (now U.S. Pat.
No. 5,513,327); which is a continuation of application Ser.
No. 07/954,945, filed on Sep. 30, 1992 (now U.S. Pat. No. 15
5,319,755); which is a continuation of application Ser. No.
07/510,898, filed on Apr. 18, 1990 (now abandoned).
FIELD OF THE INVENTION
2
memory cell Is split into two addresses, row and column,
each of which can be Multiplexed over a bus only half as
wide as the memory cell address of the prior art would have
required.
COMPARISON WITH PRIOR ART
Prior art memory systems have attempted to solve the
problem of high speed access to memory with limited
success.
U.S. Pat. No. 3,821,715 (Hoff et. al.), was issued to Intel
Corporation for the earliest 4-bit microprocessor. That
patent describes a bus connecting a single central processing
unit (CPU) with multiple RAMs and ROMs. That bus
multiplexes addresses and data over a 4-bit wide bus and
uses point-to-point control signals to select particular RAMs
or ROMs. The access time is fixed and only a single
processing element is permitted. There is no block-mode
type of operation, and most important, not all of the interface
An integrated circuit bus interface for computer and video
systems is described which allows high speed transfer of
blocks of data, particularly to and from memory devices,
with reduced power consumption and increased system
reliability. A new method of physically implementing the
20
signals between the devices are bused (the ROM and RAM
control lines and the RAM select lines are point-to-point).
bus architecture is also described. 25
BACKGROUND OF THE INVENTION
In U.S. Pat. No. 4,315,308 (Jackson), a bus connecting a
single CPU to a bus interface unit is described.
The invention uses multiplexed address, data, and control
information over a single 16-bit wide bus. Block-mode
operations are defined, with the length of the block sent as
part of the control sequence. In addition, variable access-
time operations using a "stretch" cycle signal are provided.
There are no multiple processing elements and no capability
Semiconductor computer memories have traditionally
been designed and structured to use one memory device for
each bit, or small group of bits, of any individual computer
word, where the word size is governed by the choice of
computer. Typical word sizes range from 4 to 64 bits. Each
memory device typically is connected in parallel to a series
30 for multiple outstanding requests, and again, not all of the
interface signals are bused.
of address lines and connected to one of a series of data
lines. When the computer seeks to read from or write to a
specific memory location, an address is put on the address
lines and some or all of the memory devices are activated
using a separate device select line for each needed device.
One or more devices may be connected to each data line but
typically only a small number of data lines are connected to
a single memory device. Thus data line 0 in connected to
device(s) 0, data line 1 is connected to device(s) 1, and so on.
In U.S. Pat. No. 4,449,207 (Kung, et. al.), a DRAM is
described which multiplexes address and data on an internal
bus. The external interface to this DRAM is conventional,
35
with separate control, address and data connections.
In U.S. Pat. Nos. 4,764,846 and 4,706,166 (Go), a 3-D
package arrangement of stacked die with connections along
a single edge is described. Such packages are difficult to use
40
because of the point-to-point wiring required to interconnect
conventional memory devices with processing elements.
Both patents describe complex schemes for solving these
problems. No attempt is made to solve the problem by
Data is thus accessed or provided in parallel for each
memory read or write operation. For the system to operate
45
properly, every single memory bit in every memory device
must operate dependably and correctly.
changing the interface.
In U.S. Pat. No. 3,969,706 (Proebsting, et. al.), the current
state-of-the-art DRAM interface is described. The address is
two-way multiplexed, and there are separate pins for data
and control (RAS, CAS, WE, CS). The number of pins
grows with the size of the DRAM, and many of the
50
connections must be made point-to-point in a memory
system using such DRAMs.
To understand the concept of the present invention, it is
helpful to review the architecture of conventional memory
devices. Internal to nearly all types of memory devices
(including the most widely used Dynamic Random Access
Memory (DRAM), Static RAM (SRAM) and Read Only
Memory (ROM) devices), a large number of bits are
accessed in parallel each time the system carries out a
memory access cycle. However, only a small percentage of 55
accessed bits which are available internally each time the
memory device is cycled ever make it across the device
boundary to the external world.
There are many backplane buses described in the prior art,
but not in the combination described or having the features
of this invention. Many backplane buses multiplex addresses
and data on a single bus (e.g., the NU bus). ELXSI and
others have implemented split-transaction buses (U.S. Pat.
Nos. 4,595,923 and 4,481,625 (Roberts)). ELXSI has also
implemented a relatively low-voltage-swing current-mode
ECL driver (approximately 1 V Swing). Address-space
registers are implemented on most backplane buses, as is
some form of block mode operation.
Referring to FIG. 1, all modern DRAM, SRAM and ROM
designs have internal architectures with row (word) lines 5 60
and column (bit) lines 6 to allow the memory cells to tile a
two dimensional area 1. One bit of data is stored at the
intersection of each word and bit line. When a particular
word line Is enabled, all of the corresponding data bits are
transferred onto the bit lines. Some prior art DRAMs take
advantage of this organization to reduce the number of pins
needed to transmit the address. The address of a given
Nearly all modern backplane buses implement some type
of arbitration scheme, but the arbitration scheme used in this
invention differs from each of these. U.S. Pat. No. 4,837,682
65 (Culler), U.S. Pat. No. 4,818,985 (Ikeda), U.S. Pat. No.
4,779,089 (Theus) and U.S. Pat. No. 4,745,548 (Blahut)
describe prior art schemes. All involve either log N extra
A79
US 6,452,863 B2
3
signals, (Theus, Blahut), where N is the number of potential
bus requestors, or additional delay to get control of the bus
(Ikeda, Culler). None of the buses described in patents or
other literature use only bused connections. All contain
some point-to-point connections on the backplane. None of 5
the other aspects of this invention such as power reduction
by fetching each data block from a single device or compact
and low-cost 3-D packaging even apply to backplane buses.
The clocking scheme used in this invention has not been
used before and in fact would be difficult to implement in 10
backplane buses due to the signal degradation caused by
connector stubs. U.S. Pat. No. 4,247,917 (Heller) describes
4
based wiring used with conventional versions of these
devices. The new bus includes clock signals, power and
multiplexed address, data and control signals. In a preferred
implementation, 8 bus data lines and an Address Valid bus
line carry address, data and control information for memory
addresses up to 40 bits wide. Persons skilled in the art will
recognize that 16 bus data lines or other numbers of bus data
lines can be used to implement the teaching of this inven-
tion. The new bus is used to connect elements such as
memory, peripheral, switch and processing units.
In the system of this invention, DRAMs and other devices
receive address and control information over the bus and
transmit or receive requested data over the same bus. Each
memory device contains only a single bus interface with no
a clocking scheme using two clock lines, but relies on
ramp-shaped clock signals in contrast to the normal rise-
time signals used in the present invention. 15 other signal pins. Other devices that may be included in the
system can connect to the bus and other non-bus lines, such
as input/output lines. The bus supports large data block
transfers and split transactions to allow a user to achieve
In U.S. Pat. No. 4,646,270 (Voss), a video RAM is
described which implements a parallel-load, serial-out shift
register on the output of a DRAM. This generally allows
greatly improved bandwidth (and has been extended to 2, 4
and greater width shift-out paths.) The rest of the interfaces
20
to the DRAM (RAS, CAS, multiplexed address, etc.) remain
the same as for conventional DRAMS.
high bus utilization. This ability to rapidly read or write a
large block of data to one single device at a time is an
important advantage of this invention.
The DRAMs that connect to this bus differ from conven-
tional DRAMs in a number of ways. Registers are provided
which may store control information, device identification,
One object of the present invention is to use a new bus
interface built into semiconductor devices to support high-
speed access to large blocks of data from a single memory
device by an external user of the data, such as a
microprocessor, in an efficient and cost-effective manner.
25
device-type and other information appropriate for the chip
such as the address range for each independent portion of the
device. New bus interface circuits must be added and the
internals of prior art DRAM devices need to be modified so
Another object of this invention is to provide a clocking
scheme to permit high speed clock signals to be sent along
30
the bus with minimal clock skew between devices.
Another object of this invention is to allow mapping out
defective memory devices or portions of memory devices.
they can provide and accept data to and from the bus at the
peak data rate of the bus. This requires changes to the
column access circuitry in the DRAM, with only a minimal
increase in die size. A circuit is provided to generate a low
skew internal device clock for devices on the bus, and other
circuits provide for demultiplexing input and multiplexing
Another object of this invention is to provide a method for
distinguishing otherwise identical devices by assigning a
unique identifier to each device.
35
output signals.
Yet another object of this invention is to provide a method
for transferring address, data and control information over a
relatively narrow bus and to provide a method of bus
arbitration when multiple devices seek to use the bus simul-
taneously.
Another object of this invention is to provide a method of
distributing a high-speed memory cache within the DRAM
chips of a memory system which is much more effective
than previous cache methods.
High bus bandwidth is achieved by running the bus at a
very high clock rate (hundreds of MHz). This high clock rate
is made possible by the constrained environment of the bus.
The bus lines are controlled-impedance, doubly-terminated
40
lines. For a data rate of 500 MHz, the maximum bus
propagation time is less than 1 ns (the physical bus length is
about 10 em). In addition, because of the packaging used,
the pitch of the pins can be very close to the pitch of the
pads. The loading on the bus resulting from the individual
45
devices is very small. In a preferred implementation, this
generally allows stub capacitances of 1-2 pr and inductances
of 0.5-2 nH. Each device 15, 16, 17, shown in FIG. 3, only
has pins on one side and these pins connect directly to the
bus 18. A transceiver device 19 can be included to interface
Another object of this invention is to provide devices,
especially DRAMs, suitable for use with the bus architecture
of the invention.
SUMMARY OF INVENTION
50
multiple units to a higher order bus through pins 20.
A primary result of the architecture of this invention is to
increase the bandwidth of DRAM access. The invention also
reduces manufacturing and production costs, power
consumption, and increases packing density and system
reliability.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention includes a memory subsystem
comprising at least two semiconductor devices, including at
least one memory device, connected in parallel to a bus,
where the bus includes a plurality of bus lines for carrying 55
substantially all address, data and control information
needed by said memory devices, where the control infor-
mation includes device-select information and the bus has
substantially fewer bus lines than the number of bits in a
single address, and the bus carries device-select information
without the need for separate device-select lines connected
directly to individual devices.
FIG. 1 is a diagram which illustrates the basic 2-D
60
organization of memory devices.
Referring to FIG. 2, a standard DRAM 13, 14, ROM (or
SRAM) 12, microprocessor CPU 11, 1!0 device, disk con-
troller or other special purpose device such as a high speed 65
switch is modified to use a wholly bus-based interface rather
than the prior art combination of point-to-point and bus-
FIG. 2 is a schematic block diagram which illustrates the
parallel connection of all bus lines and the serial Reset line
to each device in the system.
FIG. 3 is a perspective view of a system of the invention
which illustrates the 3-D packaging of semiconductor
devices on the primary bus.
FIG. 4 shows the format of a request packet.
A80
US 6,452,863 B2
5
FIG. 5 shows the format of a retry response from a slave.
FIG. 6 shows the bus cycles after a request packet
collision occurs on the bus and how arbitration is handled.
FIGS. 7a and 7b show the timing whereby signals from
two devices can overlap temporarily and drive the bus at the
5
same time.
FIGS. Sa and Sb show the connection and timing between
bus clocks and devices on the bus.
FIG. 9 is a perspective view showing how transceivers
10
can be used to connect a number of bus units to a transceiver
bus.
FIG. 10 is a block and schematic diagram of input/output
circuitry used to connect devices to the bus.
FIG. 11 is a schematic diagram of a clocked sense- 15
amplifier used as a bus input receiver.
FIG. 12 is a block diagram showing how the internal
device clock is generated from two bus clock signals using
a set of adjustable delay lines.
FIG. 13 is a timing diagram showing the relationship of
20
signals in the block diagram of FIG. 12.
FIG. 14 is a timing diagram of a preferred means of
implementing the reset procedure of this invention.
FIG. 15 is a diagram illustrating the general organization
25
of a 4 Mbit DRAM divided into 8 subarrays.
DETAILED DESCRIPTION
6
line 6. When a particular word line is enabled, all of the
corresponding data bits are transferred onto the bit lines.
This data, about 4000 bits at a time in a 4 MBit DRAM, is
then loaded into column sense amplifiers 3 and held for use
by the 1!0 circuits.
In the invention presented here, the data from the sense
amplifiers is enabled 32 bits at a time onto an internal device
bus running at approximately 125 MHz. This internal device
bus moves the data to the periphery of the devices where the
data is multiplexed into an 8-bit wide external bus interface,
running at approximately 500 MHz.
The bus architecture of this invention connects master or
bus controller devices, such as CPUs, Direct Memory
Access devices (DMAs) or Floating Point Units (FPUs), and
slave devices, such as DRAM, SRAM or ROM memory
devices. A slave device responds to control signals; a master
sends control signals. Persons skilled in the art realize that
some devices may behave as both master and slave at
various times, depending on the mode of operation and the
state of the system. For example, a memory device will
typically have only slave functions, while a DMAcontroller,
disk controller or CPU may include both slave and master
functions. Many other semiconductor devices, including 1!0
devices, disk controllers, or other special purpose devices
such as high speed switches can be modified for use with the
bus of this invention.
Each semiconductor device contains a set of internal
registers, preferably including a device identification (device
The present invention is designed to provide a high speed,
multiplexed bus for communication between processing
devices and memory devices and to provide devices adapted
for use in the bus system. The invention can also be used to
connect processing devices and other devices, such as 1!0
interfaces or disk controllers, with or without memory
devices on the bus. The bus consists of a relatively small
number of lines connected in parallel to each device on the
bus. The bus carries substantially all address, data and
control information needed by devices for communication
with other devices on the bus. In many systems using the
present invention, the bus carries almost every signal
between every device in the entire system. There is no need
for separate device-select lines since device-select inform a-
tion for each device on the bus is carried over the bus. There
30
ID) register, a device-type descriptor register, control reg-
isters and other registers containing other information rel-
evant to that type of device. In a preferred implementation,
semiconductor devices connected to the bus contain regis-
ters which specify the memory addresses contained within
35
that device and access-time registers which store a set of one
or more delay times at which the device can or should be
available to send or receive data.
Most of these registers can be modified and preferably are
set as part of an initialization sequence that occurs when the
40
system is powered up or reset. During the initialization
sequence each device on the bus is assigned a unique device
ID number, which is stored in the device ID register. A bus
master can then use these device ID numbers to access and
set appropriate registers in other devices, including access-
time registers, control registers, and memory registers, to
configure the system. Each slave may have one or several
access-time registers (four in a preferred embodiment). In a
preferred embodiment, one access-time register in each
slave is permanently or semi-permanently programmed with
is no need for separate address and data lines because
address and data information can be sent over the same lines.
45
Using the organization described herein, very large
addresses ( 40 bits in the preferred implementation) and large
data blocks (1024 bytes) can be sent over a small number of
bus lines (8 plus one control line in the preferred
implementation).
Virtually all of the signals needed by a computer system
can be sent over the bus. Persons skilled in the art recognize
that certain devices, such as CPUs, may be connected to
other signal lines and possibly to independent buses, for
example a bus to an independent cache memory, in addition 55
to the bus of this invention. Certain devices, for example
cross-point switches, could be connected to multiple, inde-
pendent buses of this invention. In the preferred
implementation, memory devices are provided that have no
connections other than the bus connections described herein 60
and CPUs are provided that use the bus of this invention as
the principal, if not exclusive, connection to memory and to
other devices on the bus.
50
a fixed value to facilitate certain control functions. A pre-
ferred implementation of an initialization sequence is
described below in more detail.
All modern DRAM, SRAM and ROM designs have
internal architectures with row (word) and column (bit) lines 65
to efficiently tile a 2-D area. Referring to FIG. 1, one bit of
data is stored at the intersection of each word line 5 and bit
All information sent between master devices and slave
devices is sent over the external bus, which, for example,
may be 8 bits wide. This is accomplished by defining a
protocol whereby a master device, such as a microprocessor,
seizes exclusive control of the external bus (i.e., becomes the
bus master) and initiates a bus transaction by sending a
request packet (a sequence of bytes comprising address and
control information) to one or more slave devices on the bus.
An address can consist of 16 to 40 or more bits according to
the teachings of this invention. Each slave on the bus must
decode the request packet to see if that slave needs to
respond to the packet. The slave that the packet is directed
to must then begin any internal processes needed to carry out
the requested bus transaction at the requested time. The
requesting master may also need to transact certain internal
A81
US 6,452,863 B2
7
processes before the bus transaction begins. After a specified
access time the slave(s) respond by returning one or more
bytes (8 bits) of data or by storing information made
available from the bus. More than one access time can be
provided to allow different types of responses to occur at 5
different times.
8
buffers (TLBs) which map virtual to physical (bus)
addresses. With relatively simple software, the TLBs can be
programmed to use only working memory (data structures
describing functional memories are easily generated). For
masters which don't contain TLBs (for example, a video
display generator), a small, simple RAM can be used to map
a contiguous range of addresses onto the addresses of the
functional memory devices.
Either scheme works and permits a system to have a
A request packet and the corresponding bus access are
separated by a selected number of bus cycles, allowing the
bus to be used in the intervening bus cycles by the same or
other masters for additional-requests or brief bus accesses.
Thus multiple, independent accesses are permitted, allowing
maximum utilization of the bus for transfer of short blocks
of data. Transfers of long blocks of data use the bus
efficiently even without overlap because the overhead due to
bus address, control and access times is small compared to
the total time to request and transfer the block.
10 significant percentage of non-functional devices and still
continue to operate with the memory which remains. This
means that systems built with this invention will have much
improved reliability over existing systems, including the
ability to build systems with almost no field failures.
15 Bus
Device Address Mapping
Another unique aspect of this invention is that each
memory device is a complete, independent memory sub-
system with all the functionality of a prior art memory board 20
in a conventional backplane-bus computer system. Indi-
vidual memory devices may contain a single memory sec-
tion or may be subdivided into more than one discrete
memory section. Memory devices preferably include
memory address registers for each discrete memory section. 25
A failed memory device (or even a subsection of a device)
can be "mapped out" with only the loss of a small fraction
The preferred bus architecture of this invention comprises
11 signals: BusData[0:7]; AddrValid; Clkl and Clk2; plus an
input reference level and power and ground lines connected
in parallel to each device. Signals are driven onto the bus
during conventional bus cycles. The notation "Signal[i:j]"
refers to a specific range of signals or lines, for examples,
BusData[0:7] means BusDataO, BusDatal, ... , BusData7.
The bus lines for BusData[0:7] signals form a byte-wide,
multiplexed data/address/control bus. AddrValid is used to
indicate when the bus is holding a valid address request, and
instructs a slave to decode the bus data as an address and, if
the address is included on that slave, to handle the pending
request. The two clocks together provide a synchronized,
high speed clock for all the devices on the bus. In addition
of the memory, maintaining essentially full system capabil-
ity. Mapping out bad devices can be accomplished in two
ways, both compatible with this invention.
The preferred method uses address registers in each
memory device (or independent discrete portion thereof) to
store information which defines the range of bus addresses
30 to the bused signals, there is one other line (Resetln,
ResetOut) connecting each device in series for use during
initialization to assign every device in the system a unique
device ID number (described below in detail).
to which this memory device will respond. This is similar to
prior art schemes used in memory boards in conventional 35
backplane bus systems. The address registers can include a
single pointer, usually pointing to a block of known size, a
pointer and a fixed or variable block size value or two
pointers, one pointing to the beginning and one to the end (or
to the "top" and "bottom") of each memory block. By 40
appropriate settings of the address registers, a series of
functional memory devices or discrete memory sections can
be made to respond to a contiguous range of addresses,
giving the system access to a contiguous block of good
memory, limited primarily by the number of good devices 45
connected to the bus. A block of memory in a first memory
device or memory section can be assigned a certain range of
addresses, then a block of memory in a next memory device
or memory section can be assigned addresses starting with
an address one higher (or lower, depending on the memory 50
structure) than the last address of the previous block.
Preferred devices for use in this invention include device-
type register information specifying the type of chip, includ-
ing how much memory is available in what configuration on
that device. A master can perform an appropriate memory 55
test, such as reading and writing each memory cell in one or
more selected orders, to test proper functioning of each
accessible discrete portion of memory (based in part on
information like device ID number and device-type) and
write address values (up to 40 bits in the preferred 60
embodiment, 10
12
bytes), preferably contiguous, into device
address-space registers. Non-functional or impaired
memory sections can be assigned a special address value
which the system can interpret to avoid using that memory.
The second approach puts the burden of avoiding the bad 65
devices on the system master or masters. CPUs and DMA
controllers typically have some sort of translation look-aside
To facilitate the extremely high data rate of this external
bus relative to the gate delays of the internal logic, the bus
cycles are grouped into pairs of even/odd cycles. Note that
all devices connected to a bus should preferably use the
same even/odd labeling of bus cycles and preferably should
begin operations on even cycles. This is enforced by the
clocking scheme.
Protocol and Bus Operation
The bus uses a relatively simple, synchronous, split-
transaction, block-oriented protocol for bus transactions.
One of the goals of the system is to keep the intelligence
concentrated in the masters, thus keeping the slaves an
simple as possible (since there are typically many more
slaves than masters). To reduce the complexity of the slaves,
a slave should preferably respond to a request in a specified
time, sufficient to allow the slave to begin or possibly
complete a device-internal phase including any internal
actions that must precede the subsequent bus access phase.
The time for this bus access phase is known to all devices on
the bus--each master being responsible for making sure that
the bus will be free when the bus access begins. Thus the
slaves never worry about arbitrating for the bus. This
approach eliminates arbitration in single master systems,
and also makes the slave-bus interface simpler.
In a preferred implementation of the invention, to initiate
a bus transfer over the bus, a master sends out a request
packet, a contiguous series of bytes containing address and
control information. It is preferable to use a request packet
containing an even number of bytes and also preferable to
start each packet on an even bus cycle.
The device-select function is handled using the bus data
lines. AddrValid is driven, which instructs all slaves to
decode the request packet address, determine whether they
contain the requested address, and if they do, provide the
A82
US 6,452,863 B2
9
data back to the master (in the case of a read request) or
accept data from the master (in the case of a write request)
in a data block transfer. A master can also select a specific
device by transmitting a device ID number in a request
packet. In a preferred implementation, a special device ID 5
number is chosen to indicate that the packet should be
interpreted by all devices on the bus. This allows a master to
broadcast a message, for example to set a selected control
register of all devices with the same value.
The data block transfer occurs later at a time specified in 10
the request packet control information, preferably beginning
on an even cycle. A device begins a data block transfer
almost immediately with a device-internal phase as the
device initiates certain functions, such as setting up memory
addressing, before the bus access phase begins. The time 15
after which a data block is driven onto the bus lines is
10
slave. In the preferred implementation of this invention,
AccessType[1:3] equal to zero indicates a control register
request and the address field of the packet indicates the
desired control register. For example, the most significant
two bytes can be the device ID number (specifying which
slave in being addressed) and the least significant three bytes
can specify a register address and may also represent or
include data to be loaded into that control register. Control
register accesses are used to initialize the access-time
registers, so it is preferable to use a fixed response time
which can be preprogrammed or even hard wired, for
example the value in AccessRegO, preferably 8 cycles.
Control register access can also be used to initialize or
modify other registers, including address registers.
The method of this invention provides for access mode
control specifically for the DRAMs. One such access mode
determines whether the access is page mode or normal RAS
access. In normal mode (in conventional DRAMS and in this
invention), the DRAM column sense amps or latches have
selected from values stored in slave access-time registers.
The timing of data for reads and writes is preferably the
same; the only difference is which device drives the bus. For
reads, the slave drives the bus and the master latches the
values from the bus. For writes the master drives the bus and
the selected slave latches the values from the bus.
In a preferred implementation of this invention shown in
FIG. 4, a request packet 22 contains 6 bytes of data--4.5
address bytes and 1.5 control bytes. Each request packet
uses all nine bits of the multiplexed data/address lines
(AddrValid 23+BusData[0:7] 24) for all six bytes of the
request packet. setting 23 AddrValid=1 in an otherwise
unused even cycle indicates the start of an request packet
(control information).
20 been precharged to a value intermediate between logical 0
and 1. This precharging allows access to a row in the R to
begin as soon as the access request for either inputs (writes)
or outputs (reads) is received and allows the column sense
amps to sense data quickly. In page mode (both conventional
25 and in this invention), the DRAM holds the data in the
column sense amps or latches from the previous read or
write operation. If a subsequent request to access data is
directed to the same row, the DRAM does not need to wait
for the data to be sensed (it has been sensed already) and
30 access time for this data is much shorter than the normal
In a valid request packet, AddrValid 27 must be 0 in the
last byte. Asserting this signal in the last byte invalidates the
request packet. This is used for the collision detection and
arbitration logic (described below). Bytes 25-26 contain the
first 35 address bits, Address[0:35]. The last byte contains 35
AddrValid 27 (the invalidation switch) and 28, the remain-
ing address bits, Address[36:39], and BlockSize[0:3]
(control information).
The first byte contains two 4 bit fields containing control
information, AccessType[0:3], an op code (operation code) 40
which, for example, specifies the type of access, and Master
[0:3], a position reserved for the master sending the packet
to include its master ID number. Only master numbers 1
through 15 are allowed-master number 0 is reserved for
special system commands. Any packet with Master[0:3]=0 45
is an invalid or special packet and is treated accordingly.
The AccessType field specifies whether the requested
operation is a read or write and the type of access, for
example, whether it is to the control registers or other parts
of the device, such as memory. In a preferred 50
implementation, AccessType[O] is a Read/Write switch: if it
is a 1, then the operation calls for a read from the slave (the
slave to read the requested memory block and drive the
memory contents onto the bus); if it is a 0, the operation calls
for a write into the slave (the slave to read data from the bus 55
and write it to memory). AccessType[1:3] provides up to 8
different access types for a slave. AccessType[1:2] prefer-
ably indicates the timing of the response, which is stored in
access time. Page mode generally allows much faster access
to data but to a smaller block of data (equal to the number
of sense amps). However, if the requested data is not in the
selected row, the access time is longer than the normal
access time, since the request must wait for the RAM to
precharge before the normal mode access can start. Two
access-time registers in each DRAM preferably contain the
access times to be used for normal and for page-mode
accesses, respectively.
The access mode also determines whether the DRAM
should precharge the-sense amplifiers or should save the
contents of the sense amps for a subsequent page mode
access. Typical settings are "precharge after normal access"
and "save after page mode access" but "precharge after page
mode access" or "save after normal access" are allowed,
selectable modes of operation. The DRAM can also be set to
precharge the sense amps if they are not accessed for a
selected period of time.
In page mode, the data stored in the DRAM sense
amplifiers may be accessed within much less time than it
takes to read out data in normal mode Cl0-20 nS vs. 40--100
nS). This data may be kept available for long periods.
However, if these sense amps (and hence bit lines) are not
precharged after an access, a subsequent access to a different
memory word (row) will suffer a precharge time penalty of
about 40--100 nS because the sense amps must precharge
before latching in a new value.
The contents of the sense amps thus may be held and used
as a cache, allowing faster, repetitive access to small blocks
of data. DRAM-based page-mode caches have been
attempted in the prior art using conventional DRAM orga-
nizations but they are not very effective because several
chips are required per computer word. Such a conventional
page-mode cache contains many bits (for example, 32
an access-time register, AccessRegN. The choice of access-
time register can be selected directly by having a certain op 60
code select that register, or indirectly by having a slave
respond to selected op codes with pre-selected access times
(see table below). The remaining bit, AccessType[3] may be
used to send additional information about the request to the
slaves. 65 chipsx4 Kbits) but has very few independent storage entries.
One special type of access is control register access,
which involves addressing a selected register in a selected
In other words, at any given point in time the sense amps
hold only a few different blocks or memory "locales" (a
A83
US 6,452,863 B2
11 12
single block of 4K words, in the example above). Simula-
tions have shown that upwards of 100 blocks are required to
achieve high hit rates (>90% of requests find the requested
data already in cache memory) regardless of the size of each
block. See, for example, Anant Agarwal, et. al., "An Ana-
5
lytic Cache Model," ACM Transactions on Computer
Systems, Vol. 7(2), pp. 184--215 (May 1989).
Retry Format
In some cases, a slave may not be able to respond
correctly to a request, e.g., for a read or write. In such a
situation, the slave should return an error message, some-
times called a N(o)ACK(nowledge) or retry message. The
retry message can include information about the condition
requiring a retry, but this increases system requirements for
circuitry in both slave and masters. A simple message
indicating only that an error has occurred allows for a less
complex slave, and the master can take whatever action is
needed to understand and correct the cause of the error.
The organization of memory in the present invention
allows each DRAM to hold one or more ( 4 for 4 MBit
DRAMS) separately-addressed and independent blocks of
10
data. A personal computer or workstation with 100 such
DRAMs (i.e. 400 blocks or locales) can achieve extremely
high, very repeatable hit rates (98-99% on average) as
compared to the lower (50--80%), widely varying hit rates
using DRAMS organized in the conventional fashion.
Further, because of the time penalty associated with the
15
deferred precharge on a "miss" of the page-mode cache, the
conventional DRAM-based page-mode cache generally has
been found to work less well than no cache at all.
For example, under certain conditions a slave might not
be able to supply the requested data. During a page-mode
access, the DRAM selected must be in page mode and the
requested address must match the address of the data held in
the sense amps or latches. Each DRAM can check for this
match during a page-mode access. If no match is found, the
DRAM begins precharging and returns a retry message to
the master during the first cycle of the data block (the rest of
the returned block is ignored). The master then must wait for
the precharge time (which in set to accommodate the type of
For DRAM slave access, the access types are preferably
used in the following way: 20
Access Type[ 1 :3] Use Access Time
0 Control Register Fixed, 8[ AccessRegO]
Access
Unused Fixed, 8[ AccessRegO]
2-3 Unused AccessReg1
4-5 Page Mode DRAM AccessReg2
access
6-7 Normal DRAM access AccessReg3
Persons skilled in the art will recognize that a series of
available bits could be designated as switches for controlling
these access modes. For example:
AccessType[2] page mode/normal switch
AccessType[3] precharge/save-data switch
BlockSize[0:3] specifies the site of the data block transfer.
If BlockSize[O] is 0, the remaining bits are the binary
representation of the block size (0--7). If BlockSize[O] is 1,
then the remaining bits give the block size as a binary power
of 2, from 8 to 1024. A zero-length block can be interpreted
as a special command, for example, to refresh a DRAM
without returning any data, or to change the DRAM from
page mode to normal access mode or vice-versa.
BlockSize[0:2] Number of Bytes in Block
0-7 0-7 respectively
8 8
9 16
10 32
11 64
12 128
13 256
14 512
15 1024
Persons skilled in the art will recognize that other block
size encoding schemes or values can be used.
In most cases, a slave will respond at the selected access
time by reading or writing data from or to the bus over bus
lines BusData[0:7] and AddrValid will be at logical 0. In a
preferred embodiment, substantially each memory access
will involve only a single memory device, that is, a single
block will be read from or written to a single memory
device.
25
slave in question, stored in a special register,
PreChargeReg), and then resend the request as a normal
DRAM access (AccessType=6 or 7).
In the preferred form of the present invention, a slave
signals a retry by drivingAddrValid true at the time the slave
was supposed to begin reading or writing data. A master
which expected to write to that slave must monitor
AddrValid during the write and take corrective action if it
30 detects a retry message. FIG. 5 illustrates the format of a
retry message 28 which is useful for read requests, consist-
ing of 23 AddrValid=1 with Master[0:3]=0 in the first (even)
cycle. Note that AddrValid is normally 0 for data block
transfers and that there is no master 0 (only 1 through 15 are
35 allowed). All DRAMs and masters can easily recognize such
a packet as an invalid request packet, and therefore a retry
message. In this type of bus transaction all of the fields
except for Master[0:3] and AddrValid 23 may be used an
information fields, although in the implementation
40 described, the contents are undefined. Persons skilled in the
art recognize that another method of signifying a retry
message is to add a Datainvalid line and signal to the bus.
This signal could be asserted in the case of a NACK.
45
50
Bus Arbitration
In the case of a single master, there are by definition no
arbitration problems. The master sends request packets and
keeps track of periods when the bus will be busy in response
to that packet. The master can schedule multiple requests so
that the corresponding data block transfers do not overlap.
The bus architecture of this invention is also useful in
configurations with multiple masters. When two or more
masters are on the same bus, each master must keep track of
all the pending transactions, so each master knows when it
can send a request packet and access the corresponding data
55 block transfer. Situations will arise, however, where two or
more masters send a request packet at about the same time
and the multiple requests must be detected, then sorted out
by some sort of bus arbitration.
There are many ways for each master to keep track of
60 when the bus is and will be busy. A simple method is for each
master to maintain a bus-busy data structure, for example by
maintaining two pointers, one to indicate the earliest point in
the future when the bus will be busy and the other to indicate
the earliest point in the future when the bus will be free, that
65 is, the end of the latest pending data block transfer. Using
this information, each master can determine whether and
when there is enough time to send a request packet (as
A84
US 6,452,863 B2
13
described above under Protocol) before the bus becomes
busy with another data block transfer and whether the
corresponding data block transfer will interfere with pending
bus transactions. Thus each master must read every request
packet and update its bus-busy data structure to maintain 5
information about when the bus is and will be free.
14
forcing an arbitration. The logic in the preferred implemen-
tation is fast enough that a master should detect a request
packet by another master by cycle 3 of the first request
packet, so no master is likely to attempt to send a potentially
colliding request packet later than cycle 2.
Slave devices do not need to detect a collision directly, but
they must wait to do anything irrecoverable until the last
byte (byte 5) is read to ensure that the packet is valid. A
request packet with Haster[0:3] equal to 0 (a retry signal) is
With two or more masters on the bus, masters will
occasionally transmit independent request packets during
the same bus cycle. Those multiple requests will collide as
each such master drives the bus simultaneously with differ-
ent information, resulting in scrambled request information
and neither desired data block transfer. In a preferred form
10 ignored and does not cause a collision. The subsequent bytes
of such a packet are ignored.
To begin arbitration after a collision, the masters wait a
preselected number of cycles after the aborted request
packet ( 4 cycles in a preferred implementation), then use the
of the invention, each device on the bus seeking to write a
logical1 on a BusData or AddrValid line drives that line with
a current sufficient to sustain a voltage greater than or equal
to the high-logic value for the system. Devices do not drive
lines that should have a logical 0; those lines are simply held
at a voltage corresponding to a low-logic value. Each master
tests the voltage on at least some, preferably all, bus data and
the AddrValid lines so the master can detect a logical '1'
where the expected level is '0' on a line that it does not drive
during a given bus cycle but another master does drive.
15 next free cycle to arbitrate for the bus (the next available
even cycle in the preferred implementation). Each colliding
master signals to all other colliding masters that it seeks to
send a request packet, a priority is assigned to each of the
colliding masters, then each master is allowed to make its
20 request in the order of that priority.
FIG. 6 illustrates one preferred way of implementing this
arbitration. Each colliding master signals its intent to send a
request packet by driving a single BusData line during a
single bus cycle corresponding to its assigned master num-
Another way to detect collisions is to select one or more
bus lines for collision signalling. Each master sending a
request drives that line or lines and monitors the selected
lines for more than the normal drive current (or a logical
value of "> 1"), indicating requests by more than one master.
Persons skilled in the art will recognize that this can be
implemented with a protocol involving BusData and
AddrValid lines or could be implemented using an additional
bus line.
25 ber (1-15 in the present example). During two-byte arbitra-
tion cycle 29, byte 0 is allocated to requests 1-7 from
masters 1-7, respectively, (bit 0 is not used) and byte 1 is
allocated to requests 8-15 from masters 8-15, respectively.
At least one device and preferably each colliding master
In the preferred form of this invention, each master
detects collisions by monitoring lines which it does not drive
30 reads the values on the bus during the arbitration cycles to
determine and store which masters desire to use the bus.
Persons skilled in the art will recognize that a single byte can
be allocated for arbitration requests if the system includes
more bus lines than masters. More than 15 masters can be to see if another master is driving those lines. "Referring to
FIG. 4, the first byte of the request packet includes the 35
number of each master attempting to use the bus (Master
[0:3]). If two masters send packet requests starting at the
same point in time, the master numbers will be logical
"or"ed together by at least those masters, and thus one or
both of the masters, by monitoring the data on the bus and 40
comparing what it sent, can detect a collision. For instance
if requests by masters number 2 (0010) and 5 (0101) collide,
the bus will be driven with the value Master[0:3]=7 (0010+
0101=0111). Master number 5 will detect that the signal
Master[2]=1 and master 2 will detect that Master[1] and 45
Master[3]=1, telling both masters that a collision has
occurred. Another example in masters 2 and 11, for which
the bus will be driven with the value Master[0:3]=11 (0010+
1011=1011), and although master 11 can't readily detect this
collision, master 2 can. When any collision is detected, each 50
master detecting a collision drives the value of AddrValid 27
in byte 5 of the request packet 22 to 1, which is detected by
all masters, including master 11 in the second example
above, and forces a bus arbitration cycle, described below.
Another collision condition-may arise where master A 55
sends a request packet in cycle 0 and master B tries to send
a request packet starting in cycle 2 of the first request packet,
thereby overlapping the first request packet. This will occur
from time to time because the bus operates at high speeds,
thus the logic in a second-initiating master may not be fast 60
enough to detect a request initiated by a first master in cycle
0 and to react fast enough by delaying its own request.
Master B eventually notices that it wasn't supposed to try to
send a request packet (and consequently almost surely
destroyed the address that master A was trying to send), and, 65
as in the example above of a simultaneous collision, drives
a 1 on AddrValid during byte 5 of the first request packet 27
accommodated by using additional bus cycles.
A fixed priority scheme (preferably using the master
numbers, selecting lowest numbers first) is then used to
prioritize, then sequence the requests in a bus arbitration
queue which is maintained by at least one device. These
requests are queued by each master in the bus-busy data
structure and no further requests are allowed until the bus
arbitration queue is cleared. Persons skilled in the art will
recognize that other priority schemes can be used, including
assigning priority according to the physical location of each
master.
System Configuration/Reset
In the bus-based system of this invention, a mechanism is
provided to give each device on the bus a unique device
identifier (device ID) after power-up or under other condi-
tions as desired or needed by the system. A master can then
use this device ID to access a specific device, particularly to
set or modify registers of the specified device, including the
control and address registers. In the preferred embodiment,
one master in assigned to carry out the entire system
configuration process. The master provides a series of
unique device ID numbers for each unique device connected
to the bus system. In the preferred embodiment, each device
connected to the bus contains a special device-type register
which specifies the type of device, for instance CPU, 4 KBit
memory, 64 MBit memory or disk controller. The configu-
ration master should check each device, determine the
device type and set appropriate control registers, including
access-time registers. The configuration master should
check each memory device and set all appropriate memory
address registers.
One means to set up unique device ID numbers in to have
each device to select a device ID in sequence and store the
A85
US 6,452,863 B2
15
value in an internal device ID register. For example, a master
can pass sequential device ID numbers through shift regis-
ters in each of a series of devices, or pass a token from
device to device whereby the device with the token reads in
device ID information from another line or lines. In a 5
preferred embodiment, device ID numbers are assigned to
devices according to their physical relationship, for instance,
their order along the bus.
16
(RAS) access time. If this condition is not met, the slave may
not deliver the correct data. The value stored in a slave
access-time register is preferably one-half the number of bus
cycles for which the slave device should wait before using
the bus in response to a request. Thus an access time value
of '1' would indicate that the slave should not access the bus
until at least two cycles after the. last byte of the request
packet has been received. The value of AccessRegO is
preferably fixed at 8 (cycles) to facilitate access to control In a preferred embodiment of this invention, the device ID
setting is accomplished using a pair of pins on each device,
Resetln and ResetOut. These pins handle normal logic
signals and are used only during device ID configuration. On
each rising edge of the clock, each device copies Resetln (an
input) into a four-stage reset shift register. The output of the
reset shift register is connected to ResetOut, which in turn
connects to Resetln for the next sequentially connected
device. Substantially all devices on the bus are thereby
daisy-chained together. A first reset signal, for example,
while Resetln at a device is a logical 1, or when a selected
10 registers.
The bus architecture of this invention can include more
than one master device. The reset or initialization sequence
should also include a determination of whether there are
multiple masters on the bus, and if so to assign unique
15 master ID numbers to each. Persons skilled in the art will
bit of the reset shift register goes from zero to non-zero, 20
causes the device to hard reset, for example by clearing all
internal registers and resetting all state machines. A second
reset signal, for example, the falling edge of Resetln com-
bined with changeable values on the external bus, causes
that device to latch the contents of the external bus into the 25
internal device ID register (Device[0:7]).
To reset all devices on a bus, a master sets the Resetln line
of the first device to a "1" for long enough to ensure that all
devices on the bus have been reset ( 4 cycles times the
number of devices-note that the maximum number of 30
devices on the preferred bus configuration is 256 (B bits), so
that 1024 cycles is always enough time to reset all devices.)
Then Resetln is dropped to "0" and the BusData lines are
driven with the first followed by successive device ID
numbers, changing after every 4 clock pulses. Successive 35
devices set those device ID numbers into the corresponding
device ID register an the falling edge of Resetln propagates
through the shift registers of the daisy-chained devices. FIG.
14 shows Resetln at a first device going low while a master
drives a first device ID onto the bus data lines BusData[0:3]. 40
The first device then latches in that first device ID. After four
clock cycles, the master changes BusData[0:3] to the next
device ID number and ResetOut at the first device goes low,
which pulls Resetln for the next daisy-chained device low,
allowing the next device to latch in the next device ID 45
number from BusData[0:3]. In the preferred embodiment,
one master is assigned device ID 0 and it is the responsibility
recognize that there are many ways of doing this. For
instance, the master could poll each device to determine
what type of device it is, for example, by reading a special
register then, for each master device, write the next available
master ID number into a special register.
Error detection and correction ("ECC") methods well
known in the art can be implemented in this system. ECC
information typically is calculated for a block of data at the
time that block of data is first written into memory. The data
block usually has an integral binary size, e.g. 256 bits, and
the ECC information uses significantly fewer bits. A poten-
tial problem arises in that each binary data block in prior art
schemes typically is stored with the ECC bits appended,
resulting in a block size that is not an integral binary power.
In a preferred embodiment of this invention, ECC infor-
mation is stored separately from the corresponding data,
which can then be stored in blocks having integral binary
size. ECC information and corresponding data can be stored,
for example, in separate DRAM devices. Data can be read
without ECC using a single request packet, but to write or
read error-corrected data requires two request packets, one
for the data and a second for the corresponding ECC
information. ECC information may not always be stored
permanently and in some situations the ECC information
may be available without sending a request packet or
without a bus data block transfer.
In a preferred embodiment, a standard data block size can
be selected for use with ECC, and the ECC method will
determine the required number of bits of information in a
corresponding ECC block. RAMs containing ECC informa-
tion can be programmed to store an access time that in equal
to: (1) the access time of the normal RAM (containing data)
plus the time to access a standard data block (for corrected
data) minus the time to send a request packet (6 bytes); or
of that master to control the Resetln line and to drive
successive device ID numbers onto the bus at the appropri-
ate times. In the preferred embodiment, each device waits
two clock cycles after Resetln goes low before latching in a
device ID number from BusData[0:3].
50 (2) the access time of a normal RAM minus the time to
access a standard ECC block minus the time to send a
Persons skilled in the art recognize that longer device ID
numbers could be distributed to devices by having each
device read in multiple bytes from the bus and latch the 55
values into the device ID register. Persons skilled in the art
also recognize that there are alternative ways of getting
device ID numbers to unique devices. For instance, a series
of sequential numbers could be clocked along the Resetln
line and at a certain time each device could be instructed to 60
latch the current reset shift register value into the device ID
register.
request packet. To read a data block and the corresponding
ECC block, the master simply issues a request for the data
immediately followed by a request for the ECC block. The
ECC RAM will wait for the selected access time then drive
its data onto the bus right after (in case (1) above)) the data
RAN has finished driving out the data block. Persons skilled
in the art will recognize that the access time described in
case (2) above can be used to drive ECC data before the data
is driven onto the bus lines and will recognize that writing
data can be done by analogy with the method described for
a read. Persons skilled in the art will also recognize the
adjustments that must be made in the bus-busy structure and
the request packet arbitration methods of this invention in
The configuration master should choose and set an access
time in each access-time register in each slave to a period
sufficiently long to allow the slave to perform an actual,
desired memory access. For example, for a normal DRAM
access, this time must be longer than the row address strobe
65 order to accommodate these paired ECC requests.
Since this system is quite flexible, the system designer can
choose the size of the data blocks and the number of ECC
A86
US 6,452,863 B2
17 18
rate of 500 MHz (2 ns cycles). The characteristics of the
transmission lines are strongly affected by the loading
caused by the DRAMs (or other slaves) mounted on the bus.
These devices add lumped capacitance to the lines which
bits using the memory devices of this invention. Note that
the data stream on the bus can be interpreted in various
ways. For instance the sequence can be 2n data bytes
followed by 2m ECC bytes (or vice versa), or the sequence
can be 2k iterations of 8 data bytes plus 1 ECC byte. Other
information, such an information used by a directory-based
cache coherence scheme, can also be managed this way. See,
for example, Anant Agarwal, et al., "Scale Directory
Schemes for Cache Consistency," 15th International Sym-
posium on Computer Architecture, June 1988, pp. 280-289.
Those skilled in the art will recognize alternative methods of
implementing ECC schemes that are within the teachings of
this invention.
5 both lowers the impedance of the lines and, decreases the
transmission speed. In the loaded environment, the bus
impedance is likely to be on the order of 25 ohms and the
propagation velocity about c/4 (c=the speed of light) or 7.5
cm/ns. To operate at a 2 ns data rate, the transit time on the
Low Power 3-D Packaging
10 bus should preferably be kept under 1 ns, to leave 1 ns for
the setup and hold time of the input receivers (described
below) plus clock skew. Thus the bus lines must be kept
quite short, under about 8 em for maximum performance.
Lower performance systems may have much longer lines,
Another major advantage of this invention is that it
drastically reduces the memory system power consumption.
Nearly all the power consumed by a prior art DRAM is
dissipated in performing row access. By using a single row
access in a single RAM to supply all the bits for a block
request (cared to a row-access in each of multiple RAMs in
conventional memory systems) the power per bit can be
made very small. Since the is power dissipated by memory
devices using this invention is significantly reduced, the
devices potentially can be placed much closer together than
with conventional designs.
15 e.g. a 4 ns bus may have 24 em lines (3 ns transit time, 1 ns
setup and hold time).
In the preferred embodiment, the bus uses current source
drivers. Each output must be able to sink 50 rnA, which
provides an output swing of about 500 m V or more. In the
20 preferred embodiment of this invention, the bus is active
low. The unasserted state (the high value) is preferably
considered a logical zero, and the asserted value (low state)
is therefore a logical 1. Those skilled in the art understand
that the method of this invention can also be implemented
25 using the opposite logical relation to voltage. The value of
the unasserted state is set by the voltage on the termination
resistors, and should be high enough to allow the outputs to
act as current sources, while being as low as possible to
reduce power dissipation. These constraints may yield a
The bus architecture of this invention makes possible an
innovative 3-D packaging technology. By using a narrow,
multiplexed (time-shared) bus, the pin count for an arbi-
trarily large memory device can be kept quite small---{)n the
order of 20 pins. Moreover, this pin count can be kept
constant from one generation of DRAM density to the next.
The low power dissipation allows each package to be
smaller, with narrower pin pitches (spacing between the IC
pins). With current surface mount technology supporting pin
pitches as low as 20 mils, all off-device connections can be 35
implemented on a single edge of the memory device. Semi-
conductor die useful in this invention preferably have con-
nections or pads along one edge of the die which can then
30 termination voltage about 2V above ground in the preferred
implementation. Current source drivers cause the output
voltage to be proportional to the sum of the sources driving
the bus.
be wired or otherwise connected to the package pins with
wires having similar lengths. This geometry also allows for 40
very short leads, preferably with an effective lead length of
less than 4 mm. Furthermore, this invention uses only bused
interconnections, i.e., each pad on each device is connected
by the bus to the corresponding pad of each other device.
Referring to FIGS. 7a and 7b although there is no stable
condition where two devices drive the bus at the same time,
conditions can arise because of propagation delay on the
wires where one device, A 41, can start driving its part of the
bus 44 while the bus is still being driven by another device,
B 42 (already asserting a logicall on the bus). in a system
using current drivers, when B 42 is driving the bus (before
time 46), the value at points 44 and 45 is logical 1. If B 42
switches off at time 46 just when A 41 switches on, the
additional drive by device A 41 causes the voltage at the
output 44 of A 41 to drop briefly below the normal value.
The voltage returns to its normal value at time 47 when the
effect of device B 42 turning off is felt. The voltage at point
45 goes to logical 0 when device B 42 turns off, then drops
at time 47 when the effect of device A 41 tuning on is felt.
Since the logical 1 driven by current from device A 41 is
propagated irrespective of the previous value on the bus, the
value on the bus is guaranteed to settle after one time of
flight (9 delay, that is, the time it takes a signal to propagate
from one end of the bus to the other. If a voltage drive was
used (as in ECL wired-ORing), a logicall on the bus (from
device B 42 being previously driven) would prevent the
transition put out by device A 41 being felt at the most
remote part of the system, e.g., device 43, until the turnoff
waveform from device B 42 reached device A 41 plus one
time of flight delay, giving a worst case settling time of twice
The use of a low pin count and an edge-connected bus 45
permits a simple 3-D package, whereby the devices are
stacked and the bus is connected along a single edge of the
stack. The fact that all of the signals are bused is important
for the implementation of a simple 3-D structure. Without
this, the complexity of the "backplane" would be too diffi- 50
cult to make cost effectively with current technology. The
individual devices in a stack of the present invention can be
packed quite tightly because of the low power dissipated by
the entire memory system, permitting the devices to be
stacked bumper-to-bumper or top to bottom. Conventional 55
plastic-injection molded small outline (SO) packages can be
used with a pitch of about 2.5 mm (100 mile), but the
ultimate limit would be the device die thickness, which is
about an order of magnitude smaller, 0.2-0.5 using current
wafer technology. 60 the time of flight delay.
Bus Electrical Description
By using devices with very low power dissipation and
close physical packing, the bus can be made quite short,
which in turn allows for short propagation times and high
data rates. The bus of a preferred embodiment of the present 65
invention consists of a set of resistor-terminated controlled
impedance transmission lines which can operate up to a data
Clocking
Clocking a high speed bus accurately without introducing
error due to propagation delays can be implemented by
having each device monitor two bus clock signals and then
derive internally a device clock, the true system clock. The
bus clock information can be sent on one or two lines to
A87
US 6,452,863 B2
19 20
that all memory accesses experience an equivalent trans-
ceiver delay, but persons skilled in the art will recognize
how to implement systems which have masters on more than
one bus unit and memory devices on the transceiver bus as
provide a mechanism for each bused device to generate an
internal device clock with zero skew relative to all the other
device clocks. Referring to FIG. Sa, in the preferred
implementation, a bus clock generator 50 at one end of the
bus propagates an early bus clock signal in one direction
along the bus, for example on line 53 from right to left, to
the far and of the bus. The same clock signal then in passed
through the direct connection shown to a second line 54, and
returns as a late bus clock signal along the bus from the far
end to the origin, propagating from left to right. A single bus
clock line can be used if it is left unterminated at the far end
of the bus, allowing the early bus clock signal to reflect back
along the same line as a late bus clock signal.
5 well as on primary bus units. In general, each teaching of
this invention which refers to a memory device can be
practiced using a transceiver device and one or more
memory devices on an attached primary bus unit. Other
devices, generically referred to as peripheral devices, includ-
10 ing disk controllers, video controllers or 1!0 devices can also
be attached to either the transceiver bus or a primary bus
unit, as desired. Persons skilled in the art will recognize how
to use a single primary bus unit or multiple primary bus units
FIG. Sb illustrates how each device 51, 52 receives each
needed with a transceiver bus in certain system designs.
The transceivers are quite simple in function. They detect
request packets on the transceiver bus and transmit them to
their primary bus unit. If the request packet calls for a write
to a device on a transceiver's primary bus unit, that trans-
ceiver keeps track of the access time and block size and
of the two bus clock signals at a different time (because of 15
is propagation delay along the wires), with constant mid-
point in time between the two bus clocks along the bus. At
each device 51, 52, the rising edge 55 of Clock1 53 is
followed by the rising edge 56 of Clock2 54. Similarly, the
falling edge 57 of Clock1 53 is followed by the falling edge
20 forwards all data from the transceiver bus to the primary bus
unit during that time. The transceivers also watch their
primary bus unit, forwarding any data that occurs there to
the transceiver bus. The high speed of the buses means that
the transceivers will need to be pipe lined, and will require an
58 of Clock2 54. This waveform relationship is observed at
all other devices along the bus. Devices which are closer to
the clock generator have a greater separation between
Clock1 and Clock2 relative to devices farther from the
generator because of the longer time required for each clock
pulse to traverse the bus and return along line 54, but the
midpoint in time 59, 60 between corresponding rising or
falling edges in fixed because, for any given device, the
length of each clock line between the far end of the bus and
that device is equal. Each device must sample the two bus 30
clocks and generate its own internal device clock at the
midpoint of the two.
25 additional one or two cycle delay for data to pass through the
transceiver in either direction. Access times stored in mas-
Clock distribution problem can be further reduced by
using a bus clock and device clock rate equal to the bus cycle
data rate divided by two, that is, the bus clock period is twice 35
the bus cycle period. Thus a 500 MHz bus preferably uses
a 250 MHz clock rate. This reduction in frequency provides
two benefits. First it makes all signals on the bus have the
same worst case data rates--data on a 500 MHz bus can only
change every 2 ns. Second, clocking at half the bus cycle 40
data rate makes the labeling of the odd and even bus cycles
trivial, for example, by defining even cycles to be those
when the internal device clock is 0 and odd cycles when the
internal device clock is 1.
ters on the transceiver bus must be increased to account for
transceiver delay but access times stored in slaves on a
primary bus unit should not be modified.
Persons skilled in the art will recognize that a more
sophisticated transceiver can control transmissions to and
from primary bus units. An additional control line,
TrncvrRW can be bused to all devices on the transceiver bus,
using that line in conjunction with the AddrValid line to
indicate to all devices on the transceiver bus that the
information on the data lines is: 1) a request packet, 2) valid
data to a slave, 3) valid data from a slave, or 4) invalid data
(or idle bus). Using this extra control line obviates the need
for the transceivers to keep track of when data needs to be
forwarded from its primary to the transceiver bus-all
transceivers send all data from their primary bus to the
transceiver bus whenever the control signal indicates con-
dition 2) above. In a preferred implementation of this
invention, if AddrValid and TrncvrRW are both low, there is
Multiple Buses 45 no bus activity and the transceivers should remain in an idle
state. A controller sending a request packet will drive
AddrValid high, indicating to all devices on the transceiver
bus that a request packet is being sent which each transceiver
should forward to its primary bus unit. Bach controller
The limitation on bus length described above restricts the
total number of devices that can be placed on a single bus.
Using 2.5 spacing between devices, a single 8 em bus will
hold about 32 devices. Persons skilled in the art will
recognize certain applications of the present invention
wherein the overall data rate on the bus is adequate but
memory or processing requirements necessitate a much
larger number of devices (many more than 32). Larger
systems can easily be built using the teachings of this
invention by using one or more memory subsystems, des- 55
ignated primary bus units, each of which consists of two or
more devices, typically 32 or close to the maximum allowed
by bus design requirements, connected to a transceiver
device.
50 seeking to rite to a slave should drive both AddrValid and
TrncrRW high, indicating valid data for a slave is present on
the data lines. Each transceiver device will then transmit all
data from the transceiver bus lines to each primary bus unit.
Any controller expecting to receive information from a slave
should also drive the TrncvrRW line high, but not drive
AddrValid, thereby indicating to each transceiver to transmit
any data coming from any slave on its primary local bus to
the transceiver bus. A still more sophisticated transceiver
would recognize signals addressed to or coming from its
primary bus unit and transmit signals only at requested
times.
Referring to FIG. 9, each primary bus unit can be mounted 60
on a single circuit board 66, sometimes called a memory
stick. Each transceiver device 19 in turn connects to a
transceiver bus 65, similar or identical in electrical and other
respects to the primary bus 18 described at length above. In
An example of the physical mounting of the transceivers
is shown in FIG. 9. One important feature of this physical
arrangement is to integrate the bus of each transceiver 19
65 with the original bus of DRAMs or other devices 15, 16, 17
on the primary bus unit 66. The transceivers 19 have pins on
two sides, and are preferably mounted fiat on the primary
a preferred implementation, all masters are situated on the
transceiver bus so there are no transceiver delays between
masters and all memory devices are on primary bus units so
A88
US 6,452,863 B2
21
bus unit with a first set of pins connected to primary bus 18.
A second set of transceiver pins 20, preferably orthogonal to
the first set of pins, are oriented to allow the transceiver 19
to be attached to the transceiver bus 65 in much the same
way as the DRAMs were attached to the primary bus unit.
The transceiver bus can be generally planar and in a different
plane, preferably orthogonal to the plane of each primary
bus unit. The transceiver bus can also be generally circular
with primary bus units mounted perpendicular and tangen-
tial to the transceiver bus.
Using this two level scheme allows one to easily build a
system that contains over 500 slaves (16 buses of 32
DRAMs each). Persons skilled in the art can modify the
device ID scheme described above to accommodate more
than 256 devices, for example by using a longer device ID
or by using additional registers to hold some of the device
ID. This scheme can be extended in yet a third dimension to
make a second-order transceiver bus, connecting multiple
transceiver buses by aligning transceiver bus units parallel to
and on top of each other and busing corresponding signal
lines through a suitable transceiver. Using such a second-
order transceiver bus, one could connect many thousands of
slave devices into what is effectively a single bus.
Device Interface
The device interface to the high-speed bus can be divided
into three main parts. The first part is the electrical interface.
This part includes the input receivers, bus drivers and clock
generation circuitry. The second part contains the address
comparison circuitry and timing registers. This part takes the
input request packet and determines if the request is for this
device, and if it is, starts the internal access and delivers the
data to the pins at the correct time. The final part, specifically
for memory devices such as DRAMs, is the DRAM column
access path. This part needs to provide bandwidth into and
out of the DRAM sense amps greater than the bandwidth
provided by conventional DRAMs. The implementation of
the electrical interface and DRAM column access path are
described in more detail in the following sections. Persons
skilled in the art recognize how to modify prior -art address
comparison circuitry and prior-art register circuitry in order
to practice the present invention.
Electrical Interface-Input/Output Circuitry
A block diagram of the preferred input/output circuit for
address/data/control lines is shown in FIG. 10. This circuitry
is particularly well-suited for use in DRAM devices but it
can be used or modified by one skilled in the art for use in
other devices connected to the bus of this invention. It
consists of a set of input receivers 71, 72 and output driver
76 connected to input/output line 69 and pad 75 and circuitry
to use the internal clock 73 and internal clock complement
22
The output drivers are quite simple, and consist of a single
RHOS pulldown transistor 76. This transistor is sized so that
under worst case conditions it can still sink the 50 rnA
required by the bus. For 0.8 micron CMOS technology, the
5 transistor will need to be about 200 microns long. Overall
bus performance can be improved by using feedback tech-
niques to control output transistor current so that the current
through the device is roughly 50 rnA under all operating
conditions, although this is not absolutely necessary for
10 proper bus operation. An example of one of many methods
known to persons skilled in the art for using feedback
techniques to control current is described in Hans
Schumacher, et al., CMOS Subnanosecond True-ECL Out-
put Buffer," J. Solid State Circuits, Vol. 25 (1), pp. 150--154
15 (February 1990). Controlling this current improves perfor-
mance and reduces power dissipation. This output driver
which can be operated at 500 Hz, can in turn be controlled
by a suitable multiplexer with two or more (preferably four)
inputs connected to other internal chip circuitry, all of which
20 can be designed according to well known prior art.
The input receivers of every slave must be able to operate
during every cycle to determine whether the signal on the
bus is a valid request packet. This requirement leads to a
number of constraints on the input circuitry. In addition to
25 requiring small acquisition and resolution delays, the cir-
cuits must take little or no DC power, little AC power and
inject very little current back into the input or reference
lines. The standard clocked DRAM sense amp shown in
FIG. 11 satisfies all these requirements except the need for
30 low input currents. When this sense amp goes from sense to
sample, the capacitance of the internal nodes 93 and 84 in
FIG. 11 is discharged through the reference line 68 and input
69, respectively. This particular current is small, but the sum
of such currents from all the inputs into the reference lines
35 summed over all devices can be reasonably large.
The fact that the sign of the current depends upon on the
previous received data makes matters worse. One way to
solve this problem is to divide the sample period into two
phases. During the first phase, the inputs are shorted to a
40 buffered version of the reference level (which may have an
offset). During the second phase, the inputs are connected to
the true inputs. This scheme does not remove the input
current completely, since the input must still charge nodes
83 and 84 from the reference value to the current input value,
45 but it does reduce the total charge required by about a factor
of 10 (requiring only a 0.25V change rather than a 2.5V
change). Persons skilled in the art will recognize that many
other methods can be used to provide a clocked amplifier
that will operate on very low input currents.
One important part of the input/output circuitry generates
an internal device clock based on early and late bus clocks.
Controlling clock skew (the difference in clock timing
between devices) is important in a system running with 2 ns
cycles, thus the internal device clock is generated so the
55 input sampler and the output driver operate as close in time
as possible to midway between the two bus clocks.
74 to drive the input interface. The clocked input receivers 50
take advantage of the synchronous nature of the bus. To
further reduce the performance requirements for device
input receivers, each device pin, and thus each bus line, is
connected to two clocked receivers, one to sample the even
cycle inputs, the other to sample the odd cycle inputs. By
thus de-multiplexing the input 69 at the pin, each clocked
amplifier is given a full 2 ns cycle to amplify the bus
low-voltage-swing signal into a full value CMOS logic
signal. Persons skilled in the art will recognize that addi-
tional clocked input receivers can be used within the teach-
ings of this invention. For example, four input receivers
could be connected to each device pin and clocked by a
modified internal device clock to transfer sequential bits
from the bus to internal device circuits, allowing still higher
external bus speeds or still longer settling times to amplify
the bus low-voltage-swing signal into a full value CMOS
logic signal.
A block diagram of the internal device clock generating
circuit is shown in FIG. 12 and the corresponding timing
diagram in FIG. 13. The basic idea behind this circuit is
60 relatively simple. A DC amplifier 102 is used to convert the
small-swing bus clock into a full-swing CMOS signal. This
signal is then fed into a variable delay line 103. The output
of delay line 103 feeds three additional delay lines: 104
having a fixed delay; 105 having the same fixed delay plus
65 a second variable delay; and 106 having the same fixed delay
plus one half of the second variable delay. The outputs 107,
108 of the delay lines 104 and 105 drive clocked input
A89
US 6,452,863 B2
23
receivers 101 and 111 connected to early and late bus clock
inputs 100 and 110, respectively. These input receivers 101
and 111 have the same design as the receivers described
above and shown in FIG. 11. Variable delay lines 103 and
105 are adjusted via feedback lines 116, 115 so that input
5
receivers 101 and 111 sample the bus clocks just as they
transition. Delay lines 103 and 105 are adjusted so that the
falling edge 120 of output 107 precedes the falling edge 121
of the early bus clock, Clock1 53, by an amount of time 128
equal to the delay in input sampler 101. Delay line 108 is
10
adjusted in the same way so that falling edge 122 precedes
the falling edge 123 of late bus clock, Clock2 54, by the
delay 128 in input sampler 111.
Since the outputs 107 and 108 are synchronized with the
two bus clocks and the output 73 of the last delay line 106
24
several (preferably 4) bytes are read or written during each
cycle and the column access path is modified to run at a
lower rate (the inverse of the number of bytes accessed per
cycle, preferably '14 of the bus cycle rate). Three different
techniques are used to provide the additional internal 1!0
lines required and to supply data to memory cells at this rate.
First, the number of 1!0 bit lines in each subarray running
through the column decoder 147A, B is increased, for
example, to 16, eight for each of the two columns of column
sense amps and the column decoder selects one set of
columns from the "top" half 148 of subarray 150 and one set
of columns from the "bottom" half 149 during each cycle,
where the column decoder selects one column sense amp per
1!0 bit line. Second, each column 1!0 line is divided into two
halves, carrying data independently over separate internal
1!0 lines from the left half147A and right half 147B of each
subarray (dividing each subarray into quadrants) and the
column decoder selects sense amps from each right and left
half of the subarray, doubling the number of bits available at
each cycle. Thus each column decode selection turns on n
column sense amps, where n equals four (top left and right,
bottom left and right quadrants) times the number of 1!0
lines in the bus to each subarray quadrant (8lines eachx4=32
lines in the preferred implementation). Finally, during each
is midway between outputs 107 and 108, that is, output 73 15
follows output 107 by the same amount of time 129 that
output 73 precedes output 108, output 73 provides an
internal device clock midway between the bus clocks. The
falling edge 124 of internal device clock 73 precedes the
time of actual input sampling 125 by one sampler delay. 20
Note that this circuit organization automatically balances the
delay in substantially all device input receivers 71 and 72
(FIG. 10), since outputs 107 and 108 are adjusted so the bus
clocks are sampled by input receivers 101 and 111 just as the
bus clocks transition.
In the preferred embodiment, two sets of these delay lines
are used, one to generate the true value of the internal device
clock 73, and the other to generate the complement 74
without adding any inverter delay. The dual circuit allows
generation of truly complementary clocks, with extremely 30
small skew. The complement internal device clock is used to
clock the 'even' input receivers to sample at time 127, while
the true internal device clock is used to clock the 'odd' input
receivers to sample at time 125. The true and complement
internal device clocks are also used to select which data is 35
driven to the output drivers. The gate delay between the
internal device clock and output circuits driving the bus in
slightly greater than the corresponding delay for the input
circuits, which means that the new data always will be
driven on the bus slightly after the old data has been 40
sampled.
25 RAS cycle, two different subarrays, e.g. 157 and 153, are
accessed. This doubles again the available number of 1!0
lines containing data. Taken together, these changes increase
the internal 1!0 bandwidth by at least a factor of 8. Four
internal buses are used to route these internal 1!0 lines.
DRAM Column Access Modification
A block diagram of a conventional 4 MBit DRAM 130 is
shown in FIG. 15. The DRAM memory array is divided into
a number of subarrays 150-157, for example, 8. Each
subarray is divided into arrays 148, 149 of memory cells.
Row address selection in performed by decoders 146. A
column decoder 147A, 147B, including column sense amps
on either side of the decoder, runs through the core of each
subarray. These column sense amps can be set to precharge
or latch the most-recently stored value, as described in detail
above. Internal I/O lines connect each set of sense-amps, as
gated by corresponding column decoders, to input and
output circuitry connected ultimately to the device pins.
These internal I/O lines are used to drive the data from the
selected bit lines to the data pins (some of pins 131-145), or
Increasing the number of 1!0 lines and then splitting them in
the middle greatly reduces the capacitance of each internal
1!0 line which in turn reduces the column access time,
increasing the column access bandwidth even further.
The multiple, gated input receivers described above allow
high speed input from the device pins onto the internal I/O
lines and ultimately into memory. The multiplexed output
driver described above is used to keep up with the data flow
available using these techniques. Control means are pro-
vided to select whether information at the device pins should
be treated as an address, and therefore to be decoded, or
input or output data to be driven onto or read from the
internal 1!0 lines.
Each subarray can access 32 bits per cycle, 16 bits from
the left subarray and 16 from the right subarray. With 8 1!0
45 lines per sense-amplifier column and accessing two subar-
rays at a time, the DRAM can provide 64 bits per cycle. This
extra 1!0 bandwidth is not needed for reads (and is probably
not used), but may be needed for writes. Availability of write
bandwidth is a more difficult problem than read bandwidth
50 because over-writing a value in a sense-amplifier may be a
slow operation, depending on how the sense amplifier is
connected to the bit line. The extra set of internal I/O lines
provides some bandwidth margin for write operations.
Persons skilled in the art will recognize that many varia-
55 tions of the teachings of this invention can be practiced that
still fall within the claims of this invention which follow.
to take the data from the pins and write the selected bit lines.
Such a column access path organized by prior art constraints
does not have sufficient bandwidth to interface with a high
speed bus. The method of this invention does not require 60
changing the overall method used for column access, but
does change implementation details. Many of these details
have been implemented selectively in certain fast memory
devices abut never in conjunction with the bus architecture
What is claimed is:
1. A method of controlling a memory device by a memory
controller, wherein the memory device includes a plurality
of memory cells, the method of controlling the memory
device comprises:
providing first block size information to the memory
device, wherein the memory device is capable of pro-
cessing the first block size information, wherein the
first block size information is provided by the memory
controller and is representative of a first amount of data
to be input by the memory device; and
of this invention.
Running the internal I/O lines in the conventional way at
high bus cycle rates is not possible. In the preferred method,
65
A90
US 6,452,863 B2
25
issuing a first operation code to the memory device,
wherein in response to the first operation code, the
memory device inputs the first amount of data.
2. The method of claim 1 wherein the memory device
inputs the first amount of data synchronously with respect to 5
an external clock signal.
3. The method of claim 1 further including:
providing second block size information to the memory
device, wherein the second block size information
defines a second amount of data to be input by the 10
memory device; and
issuing a second operation code to the memory device,
wherein in response to the second operation code, the
memory device inputs the second amount of data.
4. The method of claim 1 wherein the first block size
15
information and the first operation code are included in a
request packet.
26
information and the operation code are included in the same
request packet.
information is a binary representation of the first amount of
data to be input in response to the operation code.
20. The method of claim 11 wherein the first amount of
data is output, by the memory controller, synchronously
during a plurality of clock cycles of the external clock
signal.
an internal clock signal, using a delay locked loop and the
external clock signal wherein the first amount of data is input
synchronously with respect to the internal clock signal.
first and second internal clock signals using clock generation
circuitry and the external clock signal, wherein the first
amount of data is input synchronously with respect to the
information and the first operation code are included in the
same request packet.
20 first and second internal clock signals.
6. The method of claim 1 further including providing the
first amount of data to the memory device.
7. The method of claim 6 wherein the first amount of data
23. The method of claim 22 wherein the first and second
internal clock signals are generated by a delay lock loop.
24. The method of claim 14 wherein the operation code,
the first block size information and address information are
is provided to the memory device after a delay time tran-
spires. 25 included in a packet.
8. The method of claim 7 wherein the delay time is 25. The method of claim 14 further including receiving
representative of a number of clock cycles of an external address information from the memory controller.
clock signal. 26. The method of claim 14 wherein the first block size
9. The method of claim 1 in wherein the first block size information, and the operation code are received from an
information is a binary representation of the first amount of
30
external bus.
data. 27. The method of claim 26 wherein the first block size
information, and the operation code are received from the
same external bus.
data is output, by the memory controller, synchronously with
respect to an external clock signal and during a plurality of
clock cycles of the external clock signal.
11. The method of claim 1 wherein the first operation code
is issued onto a bus.
28. The method of claim 27 wherein the external bus is
35
used to multiplex address information, control information
and data.
12. The method of claim 11 wherein the bus includes a
plurality of signal lines to multiplex control information,
address information and data.
40
13. The method of claim 1 further including providing
address information to the memory device.
14. A method of operation in a synchronous memory
device, wherein the memory device includes a plurality of
memory cells, the method of operation of the memory
45
device comprises:
receiving first block size information from a memory
controller, wherein the memory device is capable of
processing the first block size information, wherein the
50
first block size information represents a first amount of
data to be input by the memory device in response to an
operation code;
receiving the operation code, from the memory controller,
synchronously with respect to an external clock signal;
55
and
inputting the first amount of data in response to the
operation code.
15. The method of claim 14 wherein inputting the first
amount of data includes receiving the first amount of data 60
synchronously with respect to the external clock signal.
data is sampled over a plurality of clock cycles of the
external clock signal.
17. The method of claim 14 wherein the first block size 65
information and the operation code are included in a request
packet.
29. A method of operation of an integrated circuit,
wherein the integrated circuit includes a dynamic random
access memory array having a plurality of memory cells, the
method of operation comprises:
receiving block size information from a controller,
memory device is capable of processing the first block
size information wherein the block size information
represents an amount of data to be input in response to
an operation code;
receiving the operation code from the controller; and
inputting the amount of data in response to the operation
code.
30. The method of claim 29 further including storing the
amount of data in the memory array.
31. The method of claim 29 wherein the block size
information and the operation code are included in a request
packet.
32. The method of claim 29 wherein the block size
information is a binary representation of the amount of data
to be input in response to the operation code.
33. The method of claim 29 wherein the amount of data
is input, in response to the operation code, after a delay time
transpires.
34. The method of claim 33 wherein the delay, time is
representative of a number of clock cycles of the external
clock signal.
35. The method of claim 29 further including receiving
address information from the controller.
* * * * *
A91
CERTIFICATE OF CORRECTION
PATENT NO. : 6,452,863 B2
DATED : September 17, 2002
INVENTOR(S) : Farmwald et al.
Page 1 of 1
It is certified that error appears in the above-identified patent and that said Letters Patent is
hereby corrected as shown below:
Column 26,
Line 7, delete "11" and substitute-- 14 --.
Line 43, insert-- wherein the-- before "memory device".
Line 61, delete"," appearing between "delay" and "time".
Signed and Sealed this
First Day of April, 2003
JAMES E. ROGAN
Director of the United States Patent and Trademark Office

CERTIFICATE OF COMPLIANCE

I certify that the foregoing BRIEF FOR APPELLANT RAMBUS INC.
contains 11,398 words as measured by the word-processing software used to
prepare this brief.

Dated: October 11, 2013 Respectfully submitted,
/s/ J ason E. Stach
J . Michael J akes
J ason E. Stach
Aidan C. Skoyles
(202) 408-4000


CERTIFICATE OF SERVICE
I certify that I electronically filed the foregoing BRIEF FOR
APPELLANT RAMBUS INC. using the Courts CM/ECF filing system.
Counsel registered with the CM/ECF system have been served by operation of the
Courts CM/ECF SYSTEM per Fed. R. App. P. 25 and Fed. Cir. R. 25(c) on this
11
th
day of October, 2013:
Henry A. Petri, J r.
Novak Druce Connolly Bove +Quigg, LLP
1875 Eye Street, NW, 11
th
Floor
henry.petri@novakdruce.com

/s/ Kay Wylie


863

Transféré par

Informations du document

Copyright

Formats disponibles

Partager ce document

Partager ou intégrer le document

Options de partage

Avez-vous trouvé ce document utile ?

Ce contenu est-il inapproprié ?

Droits d'auteur :

Formats disponibles

863

Transféré par

Droits d'auteur :

Formats disponibles

2013-1426

(Reexamination Nos. 95/000,250 & 95/001,124)

Vous aimerez peut-être aussi